1# 2# Copyright (c) 2016-2023, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 67# must be set to 1 if the platform wants to use this feature in the Secure 68# world. It is not needed to use it in the Non-secure world. 69CTX_INCLUDE_PAUTH_REGS := 0 70 71# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 72# This must be set to 1 if architecture implements Nested Virtualization 73# Extension and platform wants to use this feature in the Secure world 74CTX_INCLUDE_NEVE_REGS := 0 75 76# Debug build 77DEBUG := 0 78 79# By default disable authenticated decryption support. 80DECRYPTION_SUPPORT := none 81 82# Build platform 83DEFAULT_PLAT := fvp 84 85# Disable the generation of the binary image (ELF only). 86DISABLE_BIN_GENERATION := 0 87 88# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 89# compatibility. 90DISABLE_MTPMU := 0 91 92# Enable capability to disable authentication dynamically. Only meant for 93# development platforms. 94DYN_DISABLE_AUTH := 0 95 96# Build option to enable MPAM for lower ELs 97ENABLE_MPAM_FOR_LOWER_ELS := 0 98 99# Enable the Maximum Power Mitigation Mechanism on supporting cores. 100ENABLE_MPMM := 0 101 102# Enable MPMM configuration via FCONF. 103ENABLE_MPMM_FCONF := 0 104 105# Flag to Enable Position Independant support (PIE) 106ENABLE_PIE := 0 107 108# Flag to enable Performance Measurement Framework 109ENABLE_PMF := 0 110 111# Flag to enable PSCI STATs functionality 112ENABLE_PSCI_STAT := 0 113 114# Flag to enable Realm Management Extension (FEAT_RME) 115ENABLE_RME := 0 116 117# Flag to enable runtime instrumentation using PMF 118ENABLE_RUNTIME_INSTRUMENTATION := 0 119 120# Flag to enable stack corruption protection 121ENABLE_STACK_PROTECTOR := 0 122 123# Flag to enable exception handling in EL3 124EL3_EXCEPTION_HANDLING := 0 125 126# Flag to enable Branch Target Identification. 127# Internal flag not meant for direct setting. 128# Use BRANCH_PROTECTION to enable BTI. 129ENABLE_BTI := 0 130 131# Flag to enable Pointer Authentication. 132# Internal flag not meant for direct setting. 133# Use BRANCH_PROTECTION to enable PAUTH. 134ENABLE_PAUTH := 0 135 136# Flag to enable AMUv1p1 extension. 137ENABLE_FEAT_AMUv1p1 := 0 138 139# Flag to enable CSV2_2 extension. 140ENABLE_FEAT_CSV2_2 := 0 141 142# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 143ENABLE_FEAT_HCX := 0 144 145# Flag to enable access to the HDFGRTR_EL2 register 146ENABLE_FEAT_FGT := 0 147 148# Flag to enable access to the CNTPOFF_EL2 register 149ENABLE_FEAT_ECV := 0 150 151# Flag to enable use of the DIT feature. 152ENABLE_FEAT_DIT := 0 153 154# Flag to enable access to Privileged Access Never bit of PSTATE. 155ENABLE_FEAT_PAN := 0 156 157# Flag to enable access to the Random Number Generator registers 158ENABLE_FEAT_RNG := 0 159 160# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS 161# registers, by setting SCR_EL3.TRNDR. 162ENABLE_FEAT_RNG_TRAP := 0 163 164# Flag to enable Speculation Barrier Instruction 165ENABLE_FEAT_SB := 0 166 167# Flag to enable Secure EL-2 feature. 168ENABLE_FEAT_SEL2 := 0 169 170# Flag to enable Virtualization Host Extensions 171ENABLE_FEAT_VHE := 0 172 173# Flag to enable delayed trapping of WFE instruction (FEAT_TWED) 174ENABLE_FEAT_TWED := 0 175 176# Flag to enable access to TCR2 (FEAT_TCR2) 177ENABLE_FEAT_TCR2 := 0 178 179# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE) 180ENABLE_FEAT_S2PIE := 0 181 182# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE) 183ENABLE_FEAT_S1PIE := 0 184 185# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE) 186ENABLE_FEAT_S2POE := 0 187 188# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE) 189ENABLE_FEAT_S1POE := 0 190 191# Flag to enable access to Guarded Control Stack (FEAT_GCS) 192ENABLE_FEAT_GCS := 0 193 194# By default BL31 encryption disabled 195ENCRYPT_BL31 := 0 196 197# By default BL32 encryption disabled 198ENCRYPT_BL32 := 0 199 200# Default dummy firmware encryption key 201ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 202 203# Default dummy nonce for firmware encryption 204ENC_NONCE := 1234567890abcdef12345678 205 206# Build flag to treat usage of deprecated platform and framework APIs as error. 207ERROR_DEPRECATED := 0 208 209# Fault injection support 210FAULT_INJECTION_SUPPORT := 0 211 212# Flag to enable architectural features detection mechanism 213FEATURE_DETECTION := 0 214 215# Byte alignment that each component in FIP is aligned to 216FIP_ALIGN := 0 217 218# Default FIP file name 219FIP_NAME := fip.bin 220 221# Default FWU_FIP file name 222FWU_FIP_NAME := fwu_fip.bin 223 224# By default firmware encryption with SSK 225FW_ENC_STATUS := 0 226 227# For Chain of Trust 228GENERATE_COT := 0 229 230# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 231# default, they are for Secure EL1. 232GICV2_G0_FOR_EL3 := 0 233 234# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 235# by lower ELs. 236HANDLE_EA_EL3_FIRST_NS := 0 237 238# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 239# The default value is sha256. 240HASH_ALG := sha256 241 242# Whether system coherency is managed in hardware, without explicit software 243# operations. 244HW_ASSISTED_COHERENCY := 0 245 246# Flag to enable trapping of implementation defined sytem registers 247IMPDEF_SYSREG_TRAP := 0 248 249# Set the default algorithm for the generation of Trusted Board Boot keys 250KEY_ALG := rsa 251 252# Set the default key size in case KEY_ALG is rsa 253ifeq ($(KEY_ALG),rsa) 254KEY_SIZE := 2048 255endif 256 257# Option to build TF with Measured Boot support 258MEASURED_BOOT := 0 259 260# NS timer register save and restore 261NS_TIMER_SWITCH := 0 262 263# Include lib/libc in the final image 264OVERRIDE_LIBC := 0 265 266# Build PL011 UART driver in minimal generic UART mode 267PL011_GENERIC_UART := 0 268 269# By default, consider that the platform's reset address is not programmable. 270# The platform Makefile is free to override this value. 271PROGRAMMABLE_RESET_ADDRESS := 0 272 273# Flag used to choose the power state format: Extended State-ID or Original 274PSCI_EXTENDED_STATE_ID := 0 275 276# Enable PSCI OS-initiated mode support 277PSCI_OS_INIT_MODE := 0 278 279# Enable RAS Support 280ENABLE_FEAT_RAS := 0 281RAS_FFH_SUPPORT := 0 282 283# By default, BL1 acts as the reset handler, not BL31 284RESET_TO_BL31 := 0 285 286# For Chain of Trust 287SAVE_KEYS := 0 288 289# Software Delegated Exception support 290SDEI_SUPPORT := 0 291 292# True Random Number firmware Interface support 293TRNG_SUPPORT := 0 294 295# Check to see if Errata ABI is supported 296ERRATA_ABI_SUPPORT := 0 297 298# Check to enable Errata ABI for platforms with non-arm interconnect 299ERRATA_NON_ARM_INTERCONNECT := 0 300 301# SMCCC PCI support 302SMC_PCI_SUPPORT := 0 303 304# Whether code and read-only data should be put on separate memory pages. The 305# platform Makefile is free to override this value. 306SEPARATE_CODE_AND_RODATA := 0 307 308# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 309# separate memory region, which may be discontiguous from the rest of BL31. 310SEPARATE_NOBITS_REGION := 0 311 312# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 313# region, platform Makefile is free to override this value. 314SEPARATE_BL2_NOLOAD_REGION := 0 315 316# If the BL31 image initialisation code is recalimed after use for the secondary 317# cores stack 318RECLAIM_INIT_CODE := 0 319 320# SPD choice 321SPD := none 322 323# Enable the Management Mode (MM)-based Secure Partition Manager implementation 324SPM_MM := 0 325 326# Use the FF-A SPMC implementation in EL3. 327SPMC_AT_EL3 := 0 328 329# Use SPM at S-EL2 as a default config for SPMD 330SPMD_SPM_AT_SEL2 := 1 331 332# Flag to introduce an infinite loop in BL1 just before it exits into the next 333# image. This is meant to help debugging the post-BL2 phase. 334SPIN_ON_BL1_EXIT := 0 335 336# Flags to build TF with Trusted Boot support 337TRUSTED_BOARD_BOOT := 0 338 339# Build option to choose whether Trusted Firmware uses Coherent memory or not. 340USE_COHERENT_MEM := 1 341 342# Build option to add debugfs support 343USE_DEBUGFS := 0 344 345# Build option to fconf based io 346ARM_IO_IN_DTB := 0 347 348# Build option to support SDEI through fconf 349SDEI_IN_FCONF := 0 350 351# Build option to support Secure Interrupt descriptors through fconf 352SEC_INT_DESC_IN_FCONF := 0 353 354# Build option to choose whether Trusted Firmware uses library at ROM 355USE_ROMLIB := 0 356 357# Build option to choose whether the xlat tables of BL images can be read-only. 358# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 359# which is the per BL-image option that actually enables the read-only tables 360# API. The reason for having this additional option is to have a common high 361# level makefile where we can check for incompatible features/build options. 362ALLOW_RO_XLAT_TABLES := 0 363 364# Chain of trust. 365COT := tbbr 366 367# Use tbbr_oid.h instead of platform_oid.h 368USE_TBBR_DEFS := 1 369 370# Build verbosity 371V := 0 372 373# Whether to enable D-Cache early during warm boot. This is usually 374# applicable for platforms wherein interconnect programming is not 375# required to enable cache coherency after warm reset (eg: single cluster 376# platforms). 377WARMBOOT_ENABLE_DCACHE_EARLY := 0 378 379# Build option to enable/disable the Statistical Profiling Extensions 380ENABLE_SPE_FOR_NS := 2 381 382# SPE is only supported on AArch64 so disable it on AArch32. 383ifeq (${ARCH},aarch32) 384 override ENABLE_SPE_FOR_NS := 0 385endif 386 387# Include Memory Tagging Extension registers in cpu context. This must be set 388# to 1 if the platform wants to use this feature in the Secure world and MTE is 389# enabled at ELX. 390CTX_INCLUDE_MTE_REGS := 0 391 392ENABLE_FEAT_AMU := 0 393ENABLE_AMU_AUXILIARY_COUNTERS := 0 394ENABLE_AMU_FCONF := 0 395AMU_RESTRICT_COUNTERS := 0 396 397# Enable SVE for non-secure world by default 398ENABLE_SVE_FOR_NS := 2 399# SVE is only supported on AArch64 so disable it on AArch32. 400ifeq (${ARCH},aarch32) 401 override ENABLE_SVE_FOR_NS := 0 402endif 403ENABLE_SVE_FOR_SWD := 0 404 405# Default SVE vector length to maximum architected value 406SVE_VECTOR_LEN := 2048 407 408# SME defaults to disabled 409ENABLE_SME_FOR_NS := 0 410ENABLE_SME_FOR_SWD := 0 411ENABLE_SME2_FOR_NS := 0 412 413SANITIZE_UB := off 414 415# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 416# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 417# Default: disabled 418USE_SPINLOCK_CAS := 0 419 420# Enable Link Time Optimization 421ENABLE_LTO := 0 422 423# This option will include EL2 registers in cpu context save and restore during 424# EL2 firmware entry/exit. Internal flag not meant for direct setting. 425# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 426# CTX_INCLUDE_EL2_REGS. 427CTX_INCLUDE_EL2_REGS := 0 428 429# Enable Memory tag extension which is supported for architecture greater 430# than Armv8.5-A 431# By default it is set to "no" 432SUPPORT_STACK_MEMTAG := no 433 434# Select workaround for AT speculative behaviour. 435ERRATA_SPECULATIVE_AT := 0 436 437# Trap RAS error record access from Non secure 438RAS_TRAP_NS_ERR_REC_ACCESS := 0 439 440# Build option to create cot descriptors using fconf 441COT_DESC_IN_DTB := 0 442 443# Build option to provide OpenSSL directory path 444OPENSSL_DIR := /usr 445 446# Select the openssl binary provided in OPENSSL_DIR variable 447ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 448 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 449else 450 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 451endif 452 453# Build option to use the SP804 timer instead of the generic one 454USE_SP804_TIMER := 0 455 456# Build option to define number of firmware banks, used in firmware update 457# metadata structure. 458NR_OF_FW_BANKS := 2 459 460# Build option to define number of images in firmware bank, used in firmware 461# update metadata structure. 462NR_OF_IMAGES_IN_FW_BANK := 1 463 464# Disable Firmware update support by default 465PSA_FWU_SUPPORT := 0 466 467# By default, disable access of trace buffer control registers from NS 468# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 469# if FEAT_TRBE is implemented. 470# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 471# AArch32. 472ifneq (${ARCH},aarch32) 473 ENABLE_TRBE_FOR_NS := 0 474else 475 override ENABLE_TRBE_FOR_NS := 0 476endif 477 478# By default, disable access to branch record buffer control registers from NS 479# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 480# if FEAT_BRBE is implemented. 481ENABLE_BRBE_FOR_NS := 0 482 483# By default, disable access of trace system registers from NS lower 484# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 485# system register trace is implemented. 486ENABLE_SYS_REG_TRACE_FOR_NS := 0 487 488# By default, disable trace filter control registers access to NS 489# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 490# if FEAT_TRF is implemented. 491ENABLE_TRF_FOR_NS := 0 492 493# In v8.6+ platforms with delayed trapping of WFE being supported 494# via FEAT_TWED, this flag takes the delay value to be set in the 495# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented. 496# By default it takes 0, and need to be updated by the platforms. 497TWED_DELAY := 0 498 499# By default, disable the mocking of RSS provided services 500PLAT_RSS_NOT_SUPPORTED := 0 501 502# Dynamic Root of Trust for Measurement support 503DRTM_SUPPORT := 0 504 505# Check platform if cache management operations should be performed. 506# Disabled by default. 507CONDITIONAL_CMO := 0 508
