1/* 2 * Copyright (c) 2022 Renesas Electronics Corporation and/or its affiliates 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6#include <arm/armv8-m.dtsi> 7#include <mem.h> 8#include <freq.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/adc/smartbond-adc.h> 11#include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h> 12#include <zephyr/dt-bindings/dma/dma_smartbond.h> 13 14/ { 15 chosen { 16 zephyr,entropy = &trng; 17 zephyr,flash-controller = &flash_controller; 18 }; 19 20 lvgl_pointer { 21 compatible = "zephyr,lvgl-pointer-input"; 22 }; 23 24 cpus: cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu@0 { 29 compatible = "arm,cortex-m33f"; 30 reg = <0>; 31 clock-frequency = <32000000>; 32 cpu-power-states = <&standby>; 33 }; 34 35 power-states { 36 standby: standby { 37 compatible = "zephyr,power-state"; 38 power-state-name = "standby"; 39 min-residency-us = <500>; 40 exit-latency-us = <100>; 41 }; 42 }; 43 }; 44 45 crg { 46 osc: osc { 47 rc32k: rc32k { 48 compatible = "renesas,smartbond-lp-osc"; 49 clock-frequency = <DT_FREQ_K(32)>; 50 #clock-cells = <0>; 51 status = "okay"; 52 }; 53 xtal32k: xtal32k { 54 compatible = "renesas,smartbond-lp-osc"; 55 clock-frequency = <32768>; 56 settle-time = <8000>; 57 #clock-cells = <0>; 58 status = "disabled"; 59 }; 60 rcx: rcx { 61 compatible = "renesas,smartbond-lp-osc"; 62 clock-frequency = <DT_FREQ_K(15)>; 63 #clock-cells = <0>; 64 status = "okay"; 65 }; 66 rc32m: rc32m { 67 compatible = "fixed-clock"; 68 clock-frequency = <DT_FREQ_M(32)>; 69 #clock-cells = <0>; 70 status = "okay"; 71 }; 72 xtal32m: xtal32m { 73 compatible = "fixed-clock"; 74 clock-frequency = <DT_FREQ_M(32)>; 75 #clock-cells = <0>; 76 status = "disabled"; 77 }; 78 pll: pll { 79 compatible = "fixed-clock"; 80 clock-frequency = <DT_FREQ_M(96)>; 81 #clock-cells = <0>; 82 status = "disabled"; 83 }; 84 }; 85 divn_clk: divn_clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <DT_FREQ_M(32)>; 88 #clock-cells = <0>; 89 status = "okay"; 90 }; 91 sys_clk: sys_clk { 92 compatible = "renesas,smartbond-sys-clk"; 93 status = "okay"; 94 clock-src = <&rc32m>; 95 status = "okay"; 96 }; 97 lp_clk: lp_clk { 98 compatible = "renesas,smartbond-lp-clk"; 99 clock-src = <&rcx>; 100 status = "okay"; 101 }; 102 103 regulators { 104 compatible = "renesas,smartbond-regulator"; 105 vdd: VDD { 106 regulator-init-microvolt = <900000>; 107 regulator-boot-on; 108 renesas,regulator-sleep-ldo; 109 renesas,regulator-dcdc-vbat-high; 110 renesas,regulator-dcdc-vbat-low; 111 }; 112 vdd_clamp: VDD_CLAMP { 113 regulator-boot-on; 114 regulator-always-on; 115 regulator-init-microvolt = <706000>; 116 }; 117 vdd_sleep: VDD_SLEEP { 118 regulator-boot-on; 119 regulator-init-microvolt = <750000>; 120 }; 121 v14: V14 { 122 regulator-init-microvolt = <1400000>; 123 regulator-boot-on; 124 renesas,regulator-dcdc-vbat-high; 125 renesas,regulator-dcdc-vbat-low; 126 }; 127 v18: V18 { 128 regulator-init-microvolt = <1800000>; 129 regulator-boot-on; 130 renesas,regulator-dcdc-vbat-high; 131 }; 132 v18p: V18P { 133 regulator-init-microvolt = <1800000>; 134 regulator-boot-on; 135 renesas,regulator-sleep-ldo; 136 renesas,regulator-dcdc-vbat-high; 137 }; 138 v30: V30 { 139 regulator-init-microvolt = <3000000>; 140 regulator-boot-on; 141 renesas,regulator-sleep-ldo; 142 renesas,regulator-v30-vbus; 143 renesas,regulator-v30-vbat; 144 renesas,regulator-v30-clamp; 145 renesas,regulator-v30-ref-bandgap; 146 }; 147 }; 148 }; 149 150 soc { 151 sram0: memory@20000000 { 152 compatible = "mmio-sram"; 153 }; 154 155 psram: memory@32000000 { 156 compatible = "zephyr,memory-region"; 157 device_type = "memory"; 158 reg = <0x32000000 DT_SIZE_K(32768)>; 159 zephyr,memory-region = "PSRAM"; 160 status = "disabled"; 161 }; 162 163 qspif: memory@16000000 { 164 compatible = "zephyr,memory-region"; 165 reg = <0x16000000 DT_SIZE_K(32768)>; 166 zephyr,memory-region = "QSPIF"; 167 }; 168 169 flash_controller: flash-controller@38000000 { 170 compatible = "renesas,smartbond-flash-controller"; 171 reg = <0x38000000 0xb0>; 172 173 #address-cells = <1>; 174 #size-cells = <1>; 175 176 read-cs-idle-delay = <50>; 177 erase-cs-idle-delay = <50>; 178 179 flash0: flash@16000000 { 180 compatible = "soc-nv-flash"; 181 erase-block-size = <4096>; 182 write-block-size = <1>; 183 }; 184 }; 185 186 pinctrl: pin-controller@50020a00 { 187 compatible = "renesas,smartbond-pinctrl"; 188 reg = <0x50020a00 0x100>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 192 gpio0: gpio@50020a00 { 193 compatible = "renesas,smartbond-gpio"; 194 gpio-controller; 195 #gpio-cells = <2>; 196 ngpios = <32>; 197 reg = <0x50020a00 20 198 0x50020a18 128 199 0x50000070 12 200 0x50000114 36>; 201 reg-names = "data", "mode", "latch", "wkup"; 202 interrupts = <38 0>; 203 }; 204 205 gpio1: gpio@50020a04 { 206 compatible = "renesas,smartbond-gpio"; 207 gpio-controller; 208 #gpio-cells = <2>; 209 ngpios = <23>; 210 reg = <0x50020a04 20 211 0x50020a98 92 212 0x5000007c 12 213 0x50000118 36>; 214 reg-names = "data", "mode", "latch", "wkup"; 215 interrupts = <39 0>; 216 }; 217 }; 218 219 rtc: rtc@50000400 { 220 compatible = "renesas,smartbond-rtc"; 221 reg = <0x50000400 0x98>; 222 interrupts = <18 0>; 223 alarms-count = <1>; 224 status = "disabled"; 225 }; 226 227 wdog: watchdog@50000700 { 228 compatible = "renesas,smartbond-watchdog"; 229 reg = <0x50000700 0x8>; 230 status = "okay"; 231 }; 232 233 timer1: timer@50010200 { 234 compatible = "renesas,smartbond-timer"; 235 reg = <0x50010200 0x300>; 236 clock-src = <&lp_clk>; 237 interrupts = <16 0>; 238 prescaler = <1>; 239 status = "disabled"; 240 }; 241 242 timer2: timer@50010300 { 243 compatible = "renesas,smartbond-timer"; 244 reg = <0x50010300 0x300>; 245 clock-src = <&divn_clk>; 246 interrupts = <17 0>; 247 prescaler = <32>; 248 status = "disabled"; 249 }; 250 251 timer3: timer@50040a00 { 252 compatible = "renesas,smartbond-timer"; 253 reg = <0x50040a00 0x300>; 254 clock-src = <&lp_clk>; 255 interrupts = <34 0>; 256 prescaler = <31>; 257 status = "disabled"; 258 }; 259 260 timer4: timer@50040b00 { 261 compatible = "renesas,smartbond-timer"; 262 reg = <0x50040b00 0x300>; 263 clock-src = <&divn_clk>; 264 interrupts = <35 0>; 265 prescaler = <32>; 266 status = "disabled"; 267 }; 268 269 uart: uart@50020000 { 270 compatible = "renesas,smartbond-uart"; 271 reg = <0x50020000 0x100>; 272 periph-clock-config = <0x01>; 273 interrupts = <5 0>; 274 status = "disabled"; 275 }; 276 277 uart2: uart@50020100 { 278 compatible = "renesas,smartbond-uart"; 279 reg = <0x50020100 0x100>; 280 periph-clock-config = <0x02>; 281 interrupts = <6 0>; 282 hw-flow-control-supported; 283 status = "disabled"; 284 }; 285 286 uart3: uart@50020200 { 287 compatible = "renesas,smartbond-uart"; 288 reg = <0x50020200 0x100>; 289 periph-clock-config = <0x08>; 290 interrupts = <7 0>; 291 hw-flow-control-supported; 292 status = "disabled"; 293 }; 294 295 adc: adc@50030900 { 296 compatible = "renesas,smartbond-adc"; 297 reg = <0x50030900 0x1C>; 298 interrupts = <27 0>; 299 status = "disabled"; 300 #io-channel-cells = <1>; 301 }; 302 303 sdadc: sdadc@50020800 { 304 compatible = "renesas,smartbond-sdadc"; 305 reg = <0x50020800 0x1C>; 306 interrupts = <28 0>; 307 clock-freq = <2>; 308 status = "disabled"; 309 #io-channel-cells = <1>; 310 }; 311 312 crypto: crypto@30040000 { 313 compatible = "renesas,smartbond-crypto"; 314 reg = <0x30040000 0x200>; 315 interrupts = <29 0>; 316 status = "disabled"; 317 }; 318 319 trng: trng@50040c00 { 320 compatible = "renesas,smartbond-trng"; 321 reg = <0x50040c00 0x0C>; 322 interrupts = <24 0>; 323 status = "okay"; 324 }; 325 326 i2c: i2c@50020600 { 327 compatible = "renesas,smartbond-i2c"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <0x50020600 0x100>; 331 periph-clock-config = <0x0200>; 332 interrupts = <8 0>; 333 status = "disabled"; 334 }; 335 336 i2c2: i2c@50020700 { 337 compatible = "renesas,smartbond-i2c"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <0x50020700 0x100>; 341 periph-clock-config = <0x0800>; 342 interrupts = <9 0>; 343 status = "disabled"; 344 }; 345 346 lcdc: lcdc@30030000 { 347 compatible = "renesas,smartbond-display"; 348 reg = <0x30030000 0x18C>; 349 interrupts = <32 0>; 350 status = "disabled"; 351 }; 352 353 spi: spi@50020300 { 354 compatible = "renesas,smartbond-spi"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 reg = <0x50020300 0x100>; 358 periph-clock-config = <0x20>; 359 interrupts = <10 0>; 360 status = "disabled"; 361 }; 362 363 spi2: spi@50020400 { 364 compatible = "renesas,smartbond-spi"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <0x50020400 0x100>; 368 periph-clock-config = <0x80>; 369 interrupts = <11 0>; 370 status = "disabled"; 371 }; 372 usbd: usb@50040000 { 373 compatible = "renesas,smartbond-usbd"; 374 reg = <0x50040000 0x1B0>; 375 dmas = <&dma 0 DMA_SMARTBOND_TRIG_MUX_USB>, 376 <&dma 1 DMA_SMARTBOND_TRIG_MUX_USB>; 377 dma-names = "rx", "tx"; 378 dma-min-transfer-size = <65>; 379 fifo-read-threshold = <4>; 380 ep-out-buf-size = <8 64 64 64>; 381 interrupts = <15 0>, <21 0>; 382 status = "disabled"; 383 }; 384 385 dma: dma@50040800 { 386 compatible = "renesas,smartbond-dma"; 387 reg = <0x50040800 0x110>; 388 interrupts = <1 0>; 389 status = "okay"; 390 dma-channels = <8>; 391 block-count = <1>; 392 #dma-cells = <2>; 393 }; 394 395 memc: qspic2@34000000 { 396 compatible = "renesas,smartbond-nor-psram"; 397 reg = <0x34000000 0x48>; 398 status = "disabled"; 399 }; 400 401 bt_hci_da1469x: bt_hci_da1469x { 402 compatible = "renesas,bt-hci-da1469x"; 403 status = "disabled"; 404 }; 405 }; 406}; 407 408&nvic { 409 arm,num-irq-priority-bits = <4>; 410}; 411