1#! armclang -E  --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5/***************************************************************************//**
6* \file cyw20829_ns_flash_sahb.sct
7* \version 1.1.0
8*
9* Linker file for the ARMCC compiler.
10*
11* The main purpose of the linker script is to describe how the sections in the
12* input files should be mapped into the output file, and to control the memory
13* layout of the output file.
14*
15* \note The entry point location starts at 0x0401e000. The valid
16* application image should be placed there.
17*
18* \note The linker files included with the PDL template projects must be generic
19* and handle all common use cases. Your project may not use every section
20* defined in the linker files. In that case you may see warnings during the
21* build process. In your project, you can simply comment out or remove the
22* relevant code in the linker file.
23*
24********************************************************************************
25* \copyright
26* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
27* an affiliate of Cypress Semiconductor Corporation.
28* SPDX-License-Identifier: Apache-2.0
29*
30* Licensed under the Apache License, Version 2.0 (the "License");
31* you may not use this file except in compliance with the License.
32* You may obtain a copy of the License at
33*
34*     http://www.apache.org/licenses/LICENSE-2.0
35*
36* Unless required by applicable law or agreed to in writing, software
37* distributed under the License is distributed on an "AS IS" BASIS,
38* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
39* See the License for the specific language governing permissions and
40* limitations under the License.
41*******************************************************************************/
42
43#define flash_start_addr_cbus 0x08000000
44#define ram_start_addr_sahb 0x20000000
45#define ram_start_addr_cbus 0x04000000
46#define ram_end_addr_sahb 0x20040000
47
48#ifndef APP_BOOTSTRAP_SIZE
49#define APP_BOOTSTRAP_SIZE 0x00002400
50#endif
51#define BOOTSTRAP_SIZE APP_BOOTSTRAP_SIZE
52
53#define FLASH_ALIGNMENT_SIZE 0x00000200
54
55; The size of the stack section at the end of CM33 SRAM
56#define STACK_SIZE              0x00001000
57
58/* VMA for bootstrap Text */
59#define bootstrapText_vma ram_start_addr_cbus + ram_end_addr_sahb - ram_start_addr_sahb - BOOTSTRAP_SIZE /* 0x0401DC00 */
60/* Size of bootstrap section */
61#define bootstrapText_size BOOTSTRAP_SIZE
62
63/* VMA for bootstrap Data */
64#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */
65
66/* VMA for flash */
67#define appText_vma flash_start_addr_cbus + BOOTSTRAP_SIZE + FLASH_ALIGNMENT_SIZE/* 0x08002600 */
68
69; Cortex-M33 application flash area
70LR_1 bootstrapText_vma BOOTSTRAP_SIZE
71{
72    bootstrap bootstrapText_vma bootstrapText_size
73    {
74        * (RESET, +FIRST)
75        * (InRoot$$Sections)
76
77        startup_cat1b_cm33.o (+RO)
78        system_cyw20829.o (+RO)
79
80        /* drivers */
81        cy_device.o (+RO)
82        cy_btss.o (+RO)
83        cy_sysclk_v2.o (+RO)
84        cy_syspm_v2.o (+RO)
85        cy_sysint_v2.o (+RO)
86        cy_syslib*.o (+RO)
87        ppu_v1.o (+RO)
88        cy_mpc.o (+RO)
89        cy_syspm_ppu.o (+RO)
90        *memcpy*.o (+RO)
91        *memmov*.o (+RO)
92        *memset*.o (+RO)
93        rt_mem*.o (+RO)
94        *(.cy_l1func*)
95    }
96
97/* converting c-bus to sahb address */
98#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4)
99
100    bootstrapData bootstrapData_vma ALIGN 4
101    {
102        startup_cat1b_cm33.o (+RW, +ZI)
103        system_cyw20829.o (+RW, +ZI)
104
105        /* drivers */
106        cy_device.o (+RW, +ZI)
107        cy_btss.o (+RW, +ZI)
108        cy_sysclk_v2.o (+RW, +ZI)
109        cy_syspm_v2.o (+RW, +ZI)
110        cy_sysint_v2.o (+RW, +ZI)
111        cy_syslib*.o (+RW, +ZI)
112        ppu_v1.o (+RW, +ZI)
113        cy_mpc.o (+RW, +ZI)
114        cy_syspm_ppu.o (+RW, +ZI)
115        *(.cy_l1data*)
116    }
117
118    bootstrap_vector bootstrapRamVect_vma UNINIT
119    {
120        * (.bss.noinit.RESET_RAM, +FIRST)
121    }
122}
123
124#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 16)
125
126LR_2 appText_vma
127{
128    app appText_vma
129    {
130        * (+RO)
131    }
132
133    appTextRam appTextRam_vma
134    {
135        * (.cy_ramfunc)
136        * (.text.cy_os_common)
137        * (.text.cy_btstack_common)
138        * (.text.cy_btstack_gatt)
139        * (.text.cy_ipc)
140        * (.text.cy_btstack_porting)
141        cy_smif.o (+RO)
142        cy_smif_memslot.o (+RO)
143        cy_smif_sfdp.o (+RO)
144     }
145
146#define appData_vma AlignExpr(ImageLimit(appTextRam), 8)
147
148    appData appData_vma
149    {
150        * (+RW, +ZI)
151    }
152
153    ; Place variables in the section that should not be initialized during the
154    ; device startup.
155    appData_noinit +0 UNINIT
156    {
157        * (.noinit)
158        * (.bss.noinit)
159    }
160
161    ; Application heap area (HEAP)
162    ARM_LIB_HEAP  +0 ALIGN 8 EMPTY ((ram_end_addr_sahb - BOOTSTRAP_SIZE)-AlignExpr(ImageLimit(appData_noinit), 8))
163    {
164    }
165
166    ; Stack region growing down
167    ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE
168    {
169    }
170}
171/* [] END OF FILE */
172