1 /***************************************************************************//** 2 * \file cyw20829A0_config.h 3 * 4 * \brief 5 * CYW20829A0 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYW20829A0_CONFIG_H_ 28 #define _CYW20829A0_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_CPUSS_CLOCK_TRACE_IN_POS_EN = 0x0000u, /* cpuss.clock_trace_in_pos_en */ 34 PCLK_SCB0_CLOCK_SCB_EN = 0x0100u, /* scb[0].clock_scb_en */ 35 PCLK_SCB1_CLOCK_SCB_EN = 0x0101u, /* scb[1].clock_scb_en */ 36 PCLK_SCB2_CLOCK_SCB_EN = 0x0102u, /* scb[2].clock_scb_en */ 37 PCLK_TCPWM0_CLOCK_COUNTER_EN0 = 0x0103u, /* tcpwm[0].clock_counter_en[0] */ 38 PCLK_TCPWM0_CLOCK_COUNTER_EN1 = 0x0104u, /* tcpwm[0].clock_counter_en[1] */ 39 PCLK_TCPWM0_CLOCK_COUNTER_EN256 = 0x0105u, /* tcpwm[0].clock_counter_en[256] */ 40 PCLK_TCPWM0_CLOCK_COUNTER_EN257 = 0x0106u, /* tcpwm[0].clock_counter_en[257] */ 41 PCLK_TCPWM0_CLOCK_COUNTER_EN258 = 0x0107u, /* tcpwm[0].clock_counter_en[258] */ 42 PCLK_TCPWM0_CLOCK_COUNTER_EN259 = 0x0108u, /* tcpwm[0].clock_counter_en[259] */ 43 PCLK_TCPWM0_CLOCK_COUNTER_EN260 = 0x0109u, /* tcpwm[0].clock_counter_en[260] */ 44 PCLK_TCPWM0_CLOCK_COUNTER_EN261 = 0x010Au, /* tcpwm[0].clock_counter_en[261] */ 45 PCLK_TCPWM0_CLOCK_COUNTER_EN262 = 0x010Bu, /* tcpwm[0].clock_counter_en[262] */ 46 PCLK_LIN0_CLOCK_CH_EN0 = 0x010Cu, /* lin[0].clock_ch_en[0] */ 47 PCLK_LIN0_CLOCK_CH_EN1 = 0x010Du, /* lin[0].clock_ch_en[1] */ 48 PCLK_CANFD0_CLOCK_CAN_EN0 = 0x010Eu, /* canfd[0].clock_can_en[0] */ 49 PCLK_IOSS_CLOCK_SMARTIO_PCLK_POS_EN3 = 0x010Fu, /* ioss.clock_smartio_pclk_pos_en[3] */ 50 PCLK_SMIF_CLK_MEM = 0x0200u, /* smif.clk_mem */ 51 PCLK_SMIF_CLK_FAST = 0x0201u, /* smif.clk_fast */ 52 PCLK_SMIF_CLK_SLOW = 0x0202u, /* smif.clk_slow */ 53 PCLK_BTSS_CLK_CPUSS_EXP = 0x0203u, /* btss.clk_cpuss_exp */ 54 PCLK_BTSS_CLK_PERI = 0x0204u, /* btss.clk_peri */ 55 PCLK_CRYPTO_CLK_HF = 0x0205u, /* crypto.clk_hf */ 56 PCLK_PDM0_CLK_IF_SRSS = 0x0300u, /* pdm[0].clk_if_srss */ 57 PCLK_TDM0_CLK_IF_SRSS0 = 0x0301u, /* tdm[0].clk_if_srss[0] */ 58 PCLK_ADCMIC_CLK_HF = 0x0500u, /* adcmic.clk_hf */ 59 PCLK_SMIF_CLK_IF = 0x0600u, /* smif.clk_if */ 60 PCLK_IOSS_CLK_HF = 0x0601u /* ioss.clk_hf */ 61 } en_clk_dst_t; 62 63 /* Trigger Group */ 64 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 65 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 66 */ 67 /* Trigger Group Inputs */ 68 /* Trigger Input Group 0 - P-DMA0 Request Assignments */ 69 typedef enum 70 { 71 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 72 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 73 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 74 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 75 TRIG_IN_MUX_0_TCPWM0_TR_OUT00 = 0x00000005u, /* tcpwm[0].tr_out0[0] */ 76 TRIG_IN_MUX_0_TCPWM0_TR_OUT10 = 0x00000006u, /* tcpwm[0].tr_out1[0] */ 77 TRIG_IN_MUX_0_TCPWM0_TR_OUT01 = 0x00000007u, /* tcpwm[0].tr_out0[1] */ 78 TRIG_IN_MUX_0_TCPWM0_TR_OUT11 = 0x00000008u, /* tcpwm[0].tr_out1[1] */ 79 TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000009u, /* ioss.peri_tr_io_input_in[0] */ 80 TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x0000000Au, /* ioss.peri_tr_io_input_in[1] */ 81 TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x0000000Bu, /* ioss.peri_tr_io_input_in[2] */ 82 TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x0000000Cu, /* ioss.peri_tr_io_input_in[3] */ 83 TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x0000000Du, /* ioss.peri_tr_io_input_in[4] */ 84 TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000000Eu, /* ioss.peri_tr_io_input_in[5] */ 85 TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000000Fu, /* ioss.peri_tr_io_input_in[6] */ 86 TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x00000010u, /* ioss.peri_tr_io_input_in[7] */ 87 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000011u, /* cpuss.cti_tr_out[0] */ 88 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000012u, /* cpuss.cti_tr_out[1] */ 89 TRIG_IN_MUX_0_ADCMIC_DC_DONE = 0x00000013u, /* adcmic.tr_adcmic_dc */ 90 TRIG_IN_MUX_0_ADCMIC_DATA_AVAIL = 0x00000014u, /* adcmic.tr_adcmic_data */ 91 TRIG_IN_MUX_0_I2S_TDM_TX0 = 0x00000015u, /* tdm.tr_tx_req[0] */ 92 TRIG_IN_MUX_0_I2S_TDM_RX0 = 0x00000016u, /* tdm.tr_rx_req[0] */ 93 TRIG_IN_MUX_0_PDM_RX0 = 0x00000017u, /* pdm.tr_rx_req[0] */ 94 TRIG_IN_MUX_0_PDM_RX1 = 0x00000018u /* pdm.tr_rx_req[1] */ 95 } en_trig_input_pdma0_tr_t; 96 97 /* Trigger Input Group 1 - TCPWM0 trigger multiplexer */ 98 typedef enum 99 { 100 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 101 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 102 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 103 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 104 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 105 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 106 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 107 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 108 TRIG_IN_MUX_1_TCPWM0_TR_OUT00 = 0x00000109u, /* tcpwm[0].tr_out0[0] */ 109 TRIG_IN_MUX_1_TCPWM0_TR_OUT10 = 0x0000010Au, /* tcpwm[0].tr_out1[0] */ 110 TRIG_IN_MUX_1_TCPWM0_TR_OUT01 = 0x0000010Bu, /* tcpwm[0].tr_out0[1] */ 111 TRIG_IN_MUX_1_TCPWM0_TR_OUT11 = 0x0000010Cu, /* tcpwm[0].tr_out1[1] */ 112 TRIG_IN_MUX_1_TCPWM0_TR_OUT0256 = 0x0000010Du, /* tcpwm[0].tr_out0[256] */ 113 TRIG_IN_MUX_1_TCPWM0_TR_OUT1256 = 0x0000010Eu, /* tcpwm[0].tr_out1[256] */ 114 TRIG_IN_MUX_1_TCPWM0_TR_OUT0257 = 0x0000010Fu, /* tcpwm[0].tr_out0[257] */ 115 TRIG_IN_MUX_1_TCPWM0_TR_OUT1257 = 0x00000110u, /* tcpwm[0].tr_out1[257] */ 116 TRIG_IN_MUX_1_TCPWM0_TR_OUT0258 = 0x00000111u, /* tcpwm[0].tr_out0[258] */ 117 TRIG_IN_MUX_1_TCPWM0_TR_OUT1258 = 0x00000112u, /* tcpwm[0].tr_out1[258] */ 118 TRIG_IN_MUX_1_TCPWM0_TR_OUT0259 = 0x00000113u, /* tcpwm[0].tr_out0[259] */ 119 TRIG_IN_MUX_1_TCPWM0_TR_OUT1259 = 0x00000114u, /* tcpwm[0].tr_out1[259] */ 120 TRIG_IN_MUX_1_TCPWM0_TR_OUT0260 = 0x00000115u, /* tcpwm[0].tr_out0[260] */ 121 TRIG_IN_MUX_1_TCPWM0_TR_OUT1260 = 0x00000116u, /* tcpwm[0].tr_out1[260] */ 122 TRIG_IN_MUX_1_TCPWM0_TR_OUT0261 = 0x00000117u, /* tcpwm[0].tr_out0[261] */ 123 TRIG_IN_MUX_1_TCPWM0_TR_OUT1261 = 0x00000118u, /* tcpwm[0].tr_out1[261] */ 124 TRIG_IN_MUX_1_TCPWM0_TR_OUT0262 = 0x00000119u, /* tcpwm[0].tr_out0[262] */ 125 TRIG_IN_MUX_1_TCPWM0_TR_OUT1262 = 0x0000011Au, /* tcpwm[0].tr_out1[262] */ 126 TRIG_IN_MUX_1_SCB_I2C_SCL0 = 0x0000011Bu, /* scb[0].tr_i2c_scl_filtered */ 127 TRIG_IN_MUX_1_SCB_TX0 = 0x0000011Cu, /* scb[0].tr_tx_req */ 128 TRIG_IN_MUX_1_SCB_RX0 = 0x0000011Du, /* scb[0].tr_rx_req */ 129 TRIG_IN_MUX_1_TIE_LOW = 0x0000011Eu, /* cpuss.zero */ 130 TRIG_IN_MUX_1_SCB_TX1 = 0x0000011Fu, /* scb[1].tr_tx_req */ 131 TRIG_IN_MUX_1_SCB_RX1 = 0x00000120u, /* scb[1].tr_rx_req */ 132 TRIG_IN_MUX_1_SCB_I2C_SCL2 = 0x00000121u, /* scb[2].tr_i2c_scl_filtered */ 133 TRIG_IN_MUX_1_SCB_TX2 = 0x00000122u, /* scb[2].tr_tx_req */ 134 TRIG_IN_MUX_1_SCB_RX2 = 0x00000123u, /* scb[2].tr_rx_req */ 135 TRIG_IN_MUX_1_SMIF_TX = 0x00000124u, /* smif.tr_tx_req */ 136 TRIG_IN_MUX_1_SMIF_RX = 0x00000125u, /* smif.tr_rx_req */ 137 TRIG_IN_MUX_1_I2S_TDM_TX0 = 0x00000126u, /* tdm.tr_tx_req[0] */ 138 TRIG_IN_MUX_1_I2S_TDM_RX0 = 0x00000127u, /* tdm.tr_rx_req[0] */ 139 TRIG_IN_MUX_1_PDM_RX0 = 0x00000128u, /* pdm.tr_rx_req[0] */ 140 TRIG_IN_MUX_1_PDM_RX1 = 0x00000129u, /* pdm.tr_rx_req[1] */ 141 TRIG_IN_MUX_1_PDM_RX_REQ_ALL = 0x0000012Au, /* pdm.tr_rx_req_all */ 142 TRIG_IN_MUX_1_HSIOM_TR_OUT0 = 0x0000012Bu, /* ioss.peri_tr_io_input_in[0] */ 143 TRIG_IN_MUX_1_HSIOM_TR_OUT1 = 0x0000012Cu, /* ioss.peri_tr_io_input_in[1] */ 144 TRIG_IN_MUX_1_HSIOM_TR_OUT2 = 0x0000012Du, /* ioss.peri_tr_io_input_in[2] */ 145 TRIG_IN_MUX_1_HSIOM_TR_OUT3 = 0x0000012Eu, /* ioss.peri_tr_io_input_in[3] */ 146 TRIG_IN_MUX_1_CTI_TR_OUT0 = 0x0000012Fu, /* cpuss.cti_tr_out[0] */ 147 TRIG_IN_MUX_1_CTI_TR_OUT1 = 0x00000130u, /* cpuss.cti_tr_out[1] */ 148 TRIG_IN_MUX_1_ADCMIC_DC_DONE = 0x00000131u, /* adcmic.tr_adcmic_dc */ 149 TRIG_IN_MUX_1_ADCMIC_DATA_AVAIL = 0x00000132u, /* adcmic.tr_adcmic_data */ 150 TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000133u, /* canfd[0].tr_tmp_rtp_out[0] */ 151 TRIG_IN_MUX_1_BTSS_TR_TX = 0x00000134u, /* btss.tr_tx_start */ 152 TRIG_IN_MUX_1_BTSS_TR_RX = 0x00000135u /* btss.tr_rx_packet_sync */ 153 } en_trig_input_tcpwm0_t; 154 155 /* Trigger Input Group 2 - TCPWM1 trigger multiplexer */ 156 typedef enum 157 { 158 TRIG_IN_MUX_2_PDMA0_TR_OUT8 = 0x00000201u, /* cpuss.dw0_tr_out[8] */ 159 TRIG_IN_MUX_2_PDMA0_TR_OUT9 = 0x00000202u, /* cpuss.dw0_tr_out[9] */ 160 TRIG_IN_MUX_2_PDMA0_TR_OUT10 = 0x00000203u, /* cpuss.dw0_tr_out[10] */ 161 TRIG_IN_MUX_2_PDMA0_TR_OUT11 = 0x00000204u, /* cpuss.dw0_tr_out[11] */ 162 TRIG_IN_MUX_2_PDMA0_TR_OUT12 = 0x00000205u, /* cpuss.dw0_tr_out[12] */ 163 TRIG_IN_MUX_2_PDMA0_TR_OUT13 = 0x00000206u, /* cpuss.dw0_tr_out[13] */ 164 TRIG_IN_MUX_2_PDMA0_TR_OUT14 = 0x00000207u, /* cpuss.dw0_tr_out[14] */ 165 TRIG_IN_MUX_2_PDMA0_TR_OUT15 = 0x00000208u, /* cpuss.dw0_tr_out[15] */ 166 TRIG_IN_MUX_2_TCPWM0_TR_OUT00 = 0x00000209u, /* tcpwm[0].tr_out0[0] */ 167 TRIG_IN_MUX_2_TCPWM0_TR_OUT10 = 0x0000020Au, /* tcpwm[0].tr_out1[0] */ 168 TRIG_IN_MUX_2_TCPWM0_TR_OUT01 = 0x0000020Bu, /* tcpwm[0].tr_out0[1] */ 169 TRIG_IN_MUX_2_TCPWM0_TR_OUT11 = 0x0000020Cu, /* tcpwm[0].tr_out1[1] */ 170 TRIG_IN_MUX_2_TCPWM0_TR_OUT0256 = 0x0000020Du, /* tcpwm[0].tr_out0[256] */ 171 TRIG_IN_MUX_2_TCPWM0_TR_OUT1256 = 0x0000020Eu, /* tcpwm[0].tr_out1[256] */ 172 TRIG_IN_MUX_2_TCPWM0_TR_OUT0257 = 0x0000020Fu, /* tcpwm[0].tr_out0[257] */ 173 TRIG_IN_MUX_2_TCPWM0_TR_OUT1257 = 0x00000210u, /* tcpwm[0].tr_out1[257] */ 174 TRIG_IN_MUX_2_TCPWM0_TR_OUT0258 = 0x00000211u, /* tcpwm[0].tr_out0[258] */ 175 TRIG_IN_MUX_2_TCPWM0_TR_OUT1258 = 0x00000212u, /* tcpwm[0].tr_out1[258] */ 176 TRIG_IN_MUX_2_TCPWM0_TR_OUT0259 = 0x00000213u, /* tcpwm[0].tr_out0[259] */ 177 TRIG_IN_MUX_2_TCPWM0_TR_OUT1259 = 0x00000214u, /* tcpwm[0].tr_out1[259] */ 178 TRIG_IN_MUX_2_TCPWM0_TR_OUT0260 = 0x00000215u, /* tcpwm[0].tr_out0[260] */ 179 TRIG_IN_MUX_2_TCPWM0_TR_OUT1260 = 0x00000216u, /* tcpwm[0].tr_out1[260] */ 180 TRIG_IN_MUX_2_TCPWM0_TR_OUT0261 = 0x00000217u, /* tcpwm[0].tr_out0[261] */ 181 TRIG_IN_MUX_2_TCPWM0_TR_OUT1261 = 0x00000218u, /* tcpwm[0].tr_out1[261] */ 182 TRIG_IN_MUX_2_TCPWM0_TR_OUT0262 = 0x00000219u, /* tcpwm[0].tr_out0[262] */ 183 TRIG_IN_MUX_2_TCPWM0_TR_OUT1262 = 0x0000021Au, /* tcpwm[0].tr_out1[262] */ 184 TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000021Bu, /* scb[0].tr_i2c_scl_filtered */ 185 TRIG_IN_MUX_2_SCB_TX0 = 0x0000021Cu, /* scb[0].tr_tx_req */ 186 TRIG_IN_MUX_2_SCB_RX0 = 0x0000021Du, /* scb[0].tr_rx_req */ 187 TRIG_IN_MUX_2_TIE_LOW = 0x0000021Eu, /* cpuss.zero */ 188 TRIG_IN_MUX_2_SCB_TX1 = 0x0000021Fu, /* scb[1].tr_tx_req */ 189 TRIG_IN_MUX_2_SCB_RX1 = 0x00000220u, /* scb[1].tr_rx_req */ 190 TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000221u, /* scb[2].tr_i2c_scl_filtered */ 191 TRIG_IN_MUX_2_SCB_TX2 = 0x00000222u, /* scb[2].tr_tx_req */ 192 TRIG_IN_MUX_2_SCB_RX2 = 0x00000223u, /* scb[2].tr_rx_req */ 193 TRIG_IN_MUX_2_SMIF_TX = 0x00000224u, /* smif.tr_tx_req */ 194 TRIG_IN_MUX_2_SMIF_RX = 0x00000225u, /* smif.tr_rx_req */ 195 TRIG_IN_MUX_2_I2S_TDM_TX0 = 0x00000226u, /* tdm.tr_tx_req[0] */ 196 TRIG_IN_MUX_2_I2S_TDM_RX0 = 0x00000227u, /* tdm.tr_rx_req[0] */ 197 TRIG_IN_MUX_2_PDM_RX0 = 0x00000228u, /* pdm.tr_rx_req[0] */ 198 TRIG_IN_MUX_2_PDM_RX1 = 0x00000229u, /* pdm.tr_rx_req[1] */ 199 TRIG_IN_MUX_2_PDM_RX_REQ_ALL = 0x0000022Au, /* pdm.tr_rx_req_all */ 200 TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x0000022Bu, /* ioss.peri_tr_io_input_in[4] */ 201 TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000022Cu, /* ioss.peri_tr_io_input_in[5] */ 202 TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000022Du, /* ioss.peri_tr_io_input_in[6] */ 203 TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000022Eu, /* ioss.peri_tr_io_input_in[7] */ 204 TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x0000022Fu, /* cpuss.cti_tr_out[0] */ 205 TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000230u, /* cpuss.cti_tr_out[1] */ 206 TRIG_IN_MUX_2_ADCMIC_DC_DONE = 0x00000231u, /* adcmic.tr_adcmic_dc */ 207 TRIG_IN_MUX_2_ADCMIC_DATA_AVAIL = 0x00000232u, /* adcmic.tr_adcmic_data */ 208 TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000233u, /* canfd[0].tr_tmp_rtp_out[0] */ 209 TRIG_IN_MUX_2_BTSS_TR_TX = 0x00000234u, /* btss.tr_tx_start */ 210 TRIG_IN_MUX_2_BTSS_TR_RX = 0x00000235u /* btss.tr_rx_packet_sync */ 211 } en_trig_input_tcpwm1_t; 212 213 /* Trigger Input Group 3 - HSIOM trigger multiplexer */ 214 typedef enum 215 { 216 TRIG_IN_MUX_3_PDMA0_TR_OUT0 = 0x00000301u, /* cpuss.dw0_tr_out[0] */ 217 TRIG_IN_MUX_3_PDMA0_TR_OUT1 = 0x00000302u, /* cpuss.dw0_tr_out[1] */ 218 TRIG_IN_MUX_3_PDMA0_TR_OUT2 = 0x00000303u, /* cpuss.dw0_tr_out[2] */ 219 TRIG_IN_MUX_3_PDMA0_TR_OUT3 = 0x00000304u, /* cpuss.dw0_tr_out[3] */ 220 TRIG_IN_MUX_3_PDMA0_TR_OUT4 = 0x00000305u, /* cpuss.dw0_tr_out[4] */ 221 TRIG_IN_MUX_3_PDMA0_TR_OUT5 = 0x00000306u, /* cpuss.dw0_tr_out[5] */ 222 TRIG_IN_MUX_3_PDMA0_TR_OUT6 = 0x00000307u, /* cpuss.dw0_tr_out[6] */ 223 TRIG_IN_MUX_3_PDMA0_TR_OUT7 = 0x00000308u, /* cpuss.dw0_tr_out[7] */ 224 TRIG_IN_MUX_3_TCPWM0_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[0] */ 225 TRIG_IN_MUX_3_TCPWM0_TR_OUT10 = 0x0000030Au, /* tcpwm[0].tr_out1[0] */ 226 TRIG_IN_MUX_3_TCPWM0_TR_OUT01 = 0x0000030Bu, /* tcpwm[0].tr_out0[1] */ 227 TRIG_IN_MUX_3_TCPWM0_TR_OUT11 = 0x0000030Cu, /* tcpwm[0].tr_out1[1] */ 228 TRIG_IN_MUX_3_TCPWM0_TR_OUT0256 = 0x0000030Du, /* tcpwm[0].tr_out0[256] */ 229 TRIG_IN_MUX_3_TCPWM0_TR_OUT1256 = 0x0000030Eu, /* tcpwm[0].tr_out1[256] */ 230 TRIG_IN_MUX_3_TCPWM0_TR_OUT0257 = 0x0000030Fu, /* tcpwm[0].tr_out0[257] */ 231 TRIG_IN_MUX_3_TCPWM0_TR_OUT1257 = 0x00000310u, /* tcpwm[0].tr_out1[257] */ 232 TRIG_IN_MUX_3_TCPWM0_TR_OUT0258 = 0x00000311u, /* tcpwm[0].tr_out0[258] */ 233 TRIG_IN_MUX_3_TCPWM0_TR_OUT1258 = 0x00000312u, /* tcpwm[0].tr_out1[258] */ 234 TRIG_IN_MUX_3_TCPWM0_TR_OUT0259 = 0x00000313u, /* tcpwm[0].tr_out0[259] */ 235 TRIG_IN_MUX_3_TCPWM0_TR_OUT1259 = 0x00000314u, /* tcpwm[0].tr_out1[259] */ 236 TRIG_IN_MUX_3_TCPWM0_TR_OUT0260 = 0x00000315u, /* tcpwm[0].tr_out0[260] */ 237 TRIG_IN_MUX_3_TCPWM0_TR_OUT1260 = 0x00000316u, /* tcpwm[0].tr_out1[260] */ 238 TRIG_IN_MUX_3_TCPWM0_TR_OUT0261 = 0x00000317u, /* tcpwm[0].tr_out0[261] */ 239 TRIG_IN_MUX_3_TCPWM0_TR_OUT1261 = 0x00000318u, /* tcpwm[0].tr_out1[261] */ 240 TRIG_IN_MUX_3_TCPWM0_TR_OUT0262 = 0x00000319u, /* tcpwm[0].tr_out0[262] */ 241 TRIG_IN_MUX_3_TCPWM0_TR_OUT1262 = 0x0000031Au, /* tcpwm[0].tr_out1[262] */ 242 TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000031Bu, /* scb[0].tr_i2c_scl_filtered */ 243 TRIG_IN_MUX_3_SCB_TX0 = 0x0000031Cu, /* scb[0].tr_tx_req */ 244 TRIG_IN_MUX_3_SCB_RX0 = 0x0000031Du, /* scb[0].tr_rx_req */ 245 TRIG_IN_MUX_3_TIE_LOW = 0x0000031Eu, /* cpuss.zero */ 246 TRIG_IN_MUX_3_SCB_TX1 = 0x0000031Fu, /* scb[1].tr_tx_req */ 247 TRIG_IN_MUX_3_SCB_RX1 = 0x00000320u, /* scb[1].tr_rx_req */ 248 TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000321u, /* scb[2].tr_i2c_scl_filtered */ 249 TRIG_IN_MUX_3_SCB_TX2 = 0x00000322u, /* scb[2].tr_tx_req */ 250 TRIG_IN_MUX_3_SCB_RX2 = 0x00000323u, /* scb[2].tr_rx_req */ 251 TRIG_IN_MUX_3_I2S_TDM_TX0 = 0x00000324u, /* tdm.tr_tx_req[0] */ 252 TRIG_IN_MUX_3_I2S_TDM_RX0 = 0x00000325u, /* tdm.tr_rx_req[0] */ 253 TRIG_IN_MUX_3_PDM_RX0 = 0x00000326u, /* pdm.tr_rx_req[0] */ 254 TRIG_IN_MUX_3_PDM_RX1 = 0x00000327u, /* pdm.tr_rx_req[1] */ 255 TRIG_IN_MUX_3_PDM_RX_REQ_ALL = 0x00000328u, /* pdm.tr_rx_req_all */ 256 TRIG_IN_MUX_3_CTI_TR_OUT0 = 0x00000329u, /* cpuss.cti_tr_out[0] */ 257 TRIG_IN_MUX_3_CTI_TR_OUT1 = 0x0000032Au, /* cpuss.cti_tr_out[1] */ 258 TRIG_IN_MUX_3_ADCMIC_DC_DONE = 0x0000032Bu, /* adcmic.tr_adcmic_dc */ 259 TRIG_IN_MUX_3_ADCMIC_DATA_AVAIL = 0x0000032Cu, /* adcmic.tr_adcmic_data */ 260 TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x0000032Du /* canfd[0].tr_tmp_rtp_out[0] */ 261 } en_trig_input_hsiom_t; 262 263 /* Trigger Input Group 4 - CPUSS Debug multiplexer */ 264 typedef enum 265 { 266 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 267 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 268 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 269 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 270 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 271 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 272 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 273 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 274 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 275 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 276 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 277 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 278 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 279 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 280 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 281 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 282 TRIG_IN_MUX_4_TCPWM0_TR_OUT00 = 0x00000411u, /* tcpwm[0].tr_out0[0] */ 283 TRIG_IN_MUX_4_TCPWM0_TR_OUT10 = 0x00000412u, /* tcpwm[0].tr_out1[0] */ 284 TRIG_IN_MUX_4_TCPWM0_TR_OUT01 = 0x00000413u, /* tcpwm[0].tr_out0[1] */ 285 TRIG_IN_MUX_4_TCPWM0_TR_OUT11 = 0x00000414u, /* tcpwm[0].tr_out1[1] */ 286 TRIG_IN_MUX_4_TCPWM0_TR_OUT0256 = 0x00000415u, /* tcpwm[0].tr_out0[256] */ 287 TRIG_IN_MUX_4_TCPWM0_TR_OUT1256 = 0x00000416u, /* tcpwm[0].tr_out1[256] */ 288 TRIG_IN_MUX_4_TCPWM0_TR_OUT0257 = 0x00000417u, /* tcpwm[0].tr_out0[257] */ 289 TRIG_IN_MUX_4_TCPWM0_TR_OUT1257 = 0x00000418u, /* tcpwm[0].tr_out1[257] */ 290 TRIG_IN_MUX_4_TCPWM0_TR_OUT0258 = 0x00000419u, /* tcpwm[0].tr_out0[258] */ 291 TRIG_IN_MUX_4_TCPWM0_TR_OUT1258 = 0x0000041Au, /* tcpwm[0].tr_out1[258] */ 292 TRIG_IN_MUX_4_TCPWM0_TR_OUT0259 = 0x0000041Bu, /* tcpwm[0].tr_out0[259] */ 293 TRIG_IN_MUX_4_TCPWM0_TR_OUT1259 = 0x0000041Cu, /* tcpwm[0].tr_out1[259] */ 294 TRIG_IN_MUX_4_TCPWM0_TR_OUT0260 = 0x0000041Du, /* tcpwm[0].tr_out0[260] */ 295 TRIG_IN_MUX_4_TCPWM0_TR_OUT1260 = 0x0000041Eu, /* tcpwm[0].tr_out1[260] */ 296 TRIG_IN_MUX_4_TCPWM0_TR_OUT0261 = 0x0000041Fu, /* tcpwm[0].tr_out0[261] */ 297 TRIG_IN_MUX_4_TCPWM0_TR_OUT1261 = 0x00000420u, /* tcpwm[0].tr_out1[261] */ 298 TRIG_IN_MUX_4_TCPWM0_TR_OUT0262 = 0x00000421u, /* tcpwm[0].tr_out0[262] */ 299 TRIG_IN_MUX_4_TCPWM0_TR_OUT1262 = 0x00000422u, /* tcpwm[0].tr_out1[262] */ 300 TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x00000423u, /* scb[0].tr_i2c_scl_filtered */ 301 TRIG_IN_MUX_4_SCB_TX0 = 0x00000424u, /* scb[0].tr_tx_req */ 302 TRIG_IN_MUX_4_SCB_RX0 = 0x00000425u, /* scb[0].tr_rx_req */ 303 TRIG_IN_MUX_4_TIE_LOW = 0x00000426u, /* cpuss.zero */ 304 TRIG_IN_MUX_4_SCB_TX1 = 0x00000427u, /* scb[1].tr_tx_req */ 305 TRIG_IN_MUX_4_SCB_RX1 = 0x00000428u, /* scb[1].tr_rx_req */ 306 TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x00000429u, /* scb[2].tr_i2c_scl_filtered */ 307 TRIG_IN_MUX_4_SCB_TX2 = 0x0000042Au, /* scb[2].tr_tx_req */ 308 TRIG_IN_MUX_4_SCB_RX2 = 0x0000042Bu, /* scb[2].tr_rx_req */ 309 TRIG_IN_MUX_4_SMIF_TX = 0x0000042Cu, /* smif.tr_tx_req */ 310 TRIG_IN_MUX_4_SMIF_RX = 0x0000042Du, /* smif.tr_rx_req */ 311 TRIG_IN_MUX_4_I2S_TDM_TX0 = 0x0000042Eu, /* tdm.tr_tx_req[0] */ 312 TRIG_IN_MUX_4_I2S_TDM_RX0 = 0x0000042Fu, /* tdm.tr_rx_req[0] */ 313 TRIG_IN_MUX_4_PDM_RX0 = 0x00000430u, /* pdm.tr_rx_req[0] */ 314 TRIG_IN_MUX_4_PDM_RX1 = 0x00000431u, /* pdm.tr_rx_req[1] */ 315 TRIG_IN_MUX_4_PDM_RX_REQ_ALL = 0x00000432u, /* pdm.tr_rx_req_all */ 316 TRIG_IN_MUX_4_HSIOM_TR_OUT0 = 0x00000433u, /* ioss.peri_tr_io_input_in[0] */ 317 TRIG_IN_MUX_4_HSIOM_TR_OUT1 = 0x00000434u, /* ioss.peri_tr_io_input_in[1] */ 318 TRIG_IN_MUX_4_HSIOM_TR_OUT2 = 0x00000435u, /* ioss.peri_tr_io_input_in[2] */ 319 TRIG_IN_MUX_4_HSIOM_TR_OUT3 = 0x00000436u, /* ioss.peri_tr_io_input_in[3] */ 320 TRIG_IN_MUX_4_HSIOM_TR_OUT4 = 0x00000437u, /* ioss.peri_tr_io_input_in[4] */ 321 TRIG_IN_MUX_4_HSIOM_TR_OUT5 = 0x00000438u, /* ioss.peri_tr_io_input_in[5] */ 322 TRIG_IN_MUX_4_HSIOM_TR_OUT6 = 0x00000439u, /* ioss.peri_tr_io_input_in[6] */ 323 TRIG_IN_MUX_4_HSIOM_TR_OUT7 = 0x0000043Au, /* ioss.peri_tr_io_input_in[7] */ 324 TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x0000043Bu, /* cpuss.cti_tr_out[0] */ 325 TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x0000043Cu, /* cpuss.cti_tr_out[1] */ 326 TRIG_IN_MUX_4_ADCMIC_DC_DONE = 0x0000043Du, /* adcmic.tr_adcmic_dc */ 327 TRIG_IN_MUX_4_ADCMIC_DATA_AVAIL = 0x0000043Eu, /* adcmic.tr_adcmic_data */ 328 TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x0000043Fu /* canfd[0].tr_tmp_rtp_out[0] */ 329 } en_trig_input_cpuss_cti_t; 330 331 /* Trigger Input Group 5 - PERI Freeze trigger multiplexer */ 332 typedef enum 333 { 334 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x00000501u, /* cpuss.cti_tr_out[0] */ 335 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x00000502u /* cpuss.cti_tr_out[1] */ 336 } en_trig_input_peri_freeze_t; 337 338 /* Trigger Input Group 6 - TCPWM and PDM trigger multiplexer */ 339 typedef enum 340 { 341 TRIG_IN_MUX_6_TCPWM0_TR_OUT00 = 0x00000601u, /* tcpwm[0].tr_out0[0] */ 342 TRIG_IN_MUX_6_TCPWM0_TR_OUT10 = 0x00000602u, /* tcpwm[0].tr_out1[0] */ 343 TRIG_IN_MUX_6_TCPWM0_TR_OUT01 = 0x00000603u, /* tcpwm[0].tr_out0[1] */ 344 TRIG_IN_MUX_6_TCPWM0_TR_OUT11 = 0x00000604u, /* tcpwm[0].tr_out1[1] */ 345 TRIG_IN_MUX_6_TCPWM0_TR_OUT0256 = 0x00000605u, /* tcpwm[0].tr_out0[256] */ 346 TRIG_IN_MUX_6_TCPWM0_TR_OUT1256 = 0x00000606u, /* tcpwm[0].tr_out1[256] */ 347 TRIG_IN_MUX_6_TCPWM0_TR_OUT0257 = 0x00000607u, /* tcpwm[0].tr_out0[257] */ 348 TRIG_IN_MUX_6_TCPWM0_TR_OUT1257 = 0x00000608u, /* tcpwm[0].tr_out1[257] */ 349 TRIG_IN_MUX_6_TCPWM0_TR_OUT0258 = 0x00000609u, /* tcpwm[0].tr_out0[258] */ 350 TRIG_IN_MUX_6_TCPWM0_TR_OUT1258 = 0x0000060Au, /* tcpwm[0].tr_out1[258] */ 351 TRIG_IN_MUX_6_TCPWM0_TR_OUT0259 = 0x0000060Bu, /* tcpwm[0].tr_out0[259] */ 352 TRIG_IN_MUX_6_TCPWM0_TR_OUT1259 = 0x0000060Cu, /* tcpwm[0].tr_out1[259] */ 353 TRIG_IN_MUX_6_TCPWM0_TR_OUT0260 = 0x0000060Du, /* tcpwm[0].tr_out0[260] */ 354 TRIG_IN_MUX_6_TCPWM0_TR_OUT1260 = 0x0000060Eu, /* tcpwm[0].tr_out1[260] */ 355 TRIG_IN_MUX_6_TCPWM0_TR_OUT0261 = 0x0000060Fu, /* tcpwm[0].tr_out0[261] */ 356 TRIG_IN_MUX_6_TCPWM0_TR_OUT1261 = 0x00000610u, /* tcpwm[0].tr_out1[261] */ 357 TRIG_IN_MUX_6_TCPWM0_TR_OUT0262 = 0x00000611u, /* tcpwm[0].tr_out0[262] */ 358 TRIG_IN_MUX_6_TCPWM0_TR_OUT1262 = 0x00000612u /* tcpwm[0].tr_out1[262] */ 359 } en_trig_input_tcpwm_pdm_t; 360 361 /* Trigger Input Group 7 - CAN TT Synchronization triggers */ 362 typedef enum 363 { 364 TRIG_IN_MUX_7_CAN_TT_TR_OUT0 = 0x00000701u /* canfd[0].tr_tmp_rtp_out[0] */ 365 } en_trig_input_cantt_t; 366 367 /* Trigger Input Group 8 - CAN TT Synchronization triggers */ 368 typedef enum 369 { 370 TRIG_IN_MUX_8_SCB_TX0 = 0x00000801u, /* scb[0].tr_tx_req */ 371 TRIG_IN_MUX_8_CAN_DBG0 = 0x00000802u /* canfd[0].tr_dbg_dma_req[0] */ 372 } en_trig_input_scb_can0_t; 373 374 /* Trigger Input Group 9 - CAN TT Synchronization triggers */ 375 typedef enum 376 { 377 TRIG_IN_MUX_9_SCB_RX0 = 0x00000901u, /* scb[0].tr_rx_req */ 378 TRIG_IN_MUX_9_CAN_FIFO0 = 0x00000902u /* canfd[0].tr_fifo0[0] */ 379 } en_trig_input_scb_can1_t; 380 381 /* Trigger Group Outputs */ 382 /* Trigger Output Group 0 - P-DMA0 Request Assignments */ 383 typedef enum 384 { 385 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 386 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 387 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 388 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u /* cpuss.dw0_tr_in[3] */ 389 } en_trig_output_pdma0_tr_t; 390 391 /* Trigger Output Group 1 - TCPWM0 trigger multiplexer */ 392 typedef enum 393 { 394 TRIG_OUT_MUX_1_TCPWM0_TR_IN0 = 0x40000100u, /* tcpwm[0].tr_all_cnt_in[0] */ 395 TRIG_OUT_MUX_1_TCPWM0_TR_IN1 = 0x40000101u, /* tcpwm[0].tr_all_cnt_in[1] */ 396 TRIG_OUT_MUX_1_TCPWM0_TR_IN2 = 0x40000102u, /* tcpwm[0].tr_all_cnt_in[2] */ 397 TRIG_OUT_MUX_1_TCPWM0_TR_IN3 = 0x40000103u, /* tcpwm[0].tr_all_cnt_in[3] */ 398 TRIG_OUT_MUX_1_TCPWM0_TR_IN4 = 0x40000104u, /* tcpwm[0].tr_all_cnt_in[4] */ 399 TRIG_OUT_MUX_1_TCPWM0_TR_IN5 = 0x40000105u, /* tcpwm[0].tr_all_cnt_in[5] */ 400 TRIG_OUT_MUX_1_TCPWM0_TR_IN6 = 0x40000106u, /* tcpwm[0].tr_all_cnt_in[6] */ 401 TRIG_OUT_MUX_1_TCPWM0_TR_IN7 = 0x40000107u, /* tcpwm[0].tr_all_cnt_in[7] */ 402 TRIG_OUT_MUX_1_TCPWM0_TR_IN8 = 0x40000108u, /* tcpwm[0].tr_all_cnt_in[8] */ 403 TRIG_OUT_MUX_1_TCPWM0_TR_IN9 = 0x40000109u, /* tcpwm[0].tr_all_cnt_in[9] */ 404 TRIG_OUT_MUX_1_TCPWM0_TR_IN10 = 0x4000010Au, /* tcpwm[0].tr_all_cnt_in[10] */ 405 TRIG_OUT_MUX_1_TCPWM0_TR_IN11 = 0x4000010Bu, /* tcpwm[0].tr_all_cnt_in[11] */ 406 TRIG_OUT_MUX_1_TCPWM0_TR_IN12 = 0x4000010Cu, /* tcpwm[0].tr_all_cnt_in[12] */ 407 TRIG_OUT_MUX_1_TCPWM0_TR_IN13 = 0x4000010Du /* tcpwm[0].tr_all_cnt_in[13] */ 408 } en_trig_output_tcpwm0_t; 409 410 /* Trigger Output Group 2 - TCPWM1 trigger multiplexer */ 411 typedef enum 412 { 413 TRIG_OUT_MUX_2_TCPWM0_TR_IN14 = 0x40000200u, /* tcpwm[0].tr_all_cnt_in[14] */ 414 TRIG_OUT_MUX_2_TCPWM0_TR_IN15 = 0x40000201u, /* tcpwm[0].tr_all_cnt_in[15] */ 415 TRIG_OUT_MUX_2_TCPWM0_TR_IN16 = 0x40000202u, /* tcpwm[0].tr_all_cnt_in[16] */ 416 TRIG_OUT_MUX_2_TCPWM0_TR_IN17 = 0x40000203u, /* tcpwm[0].tr_all_cnt_in[17] */ 417 TRIG_OUT_MUX_2_TCPWM0_TR_IN18 = 0x40000204u, /* tcpwm[0].tr_all_cnt_in[18] */ 418 TRIG_OUT_MUX_2_TCPWM0_TR_IN19 = 0x40000205u, /* tcpwm[0].tr_all_cnt_in[19] */ 419 TRIG_OUT_MUX_2_TCPWM0_TR_IN20 = 0x40000206u, /* tcpwm[0].tr_all_cnt_in[20] */ 420 TRIG_OUT_MUX_2_TCPWM0_TR_IN21 = 0x40000207u, /* tcpwm[0].tr_all_cnt_in[21] */ 421 TRIG_OUT_MUX_2_TCPWM0_TR_IN22 = 0x40000208u, /* tcpwm[0].tr_all_cnt_in[22] */ 422 TRIG_OUT_MUX_2_TCPWM0_TR_IN23 = 0x40000209u, /* tcpwm[0].tr_all_cnt_in[23] */ 423 TRIG_OUT_MUX_2_TCPWM0_TR_IN24 = 0x4000020Au, /* tcpwm[0].tr_all_cnt_in[24] */ 424 TRIG_OUT_MUX_2_TCPWM0_TR_IN25 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[25] */ 425 TRIG_OUT_MUX_2_TCPWM0_TR_IN26 = 0x4000020Cu, /* tcpwm[0].tr_all_cnt_in[26] */ 426 TRIG_OUT_MUX_2_TCPWM0_TR_IN27 = 0x4000020Du /* tcpwm[0].tr_all_cnt_in[27] */ 427 } en_trig_output_tcpwm1_t; 428 429 /* Trigger Output Group 3 - HSIOM trigger multiplexer */ 430 typedef enum 431 { 432 TRIG_OUT_MUX_3_HSIOM_TR_IO_OUTPUT0 = 0x40000300u, /* ioss.peri_tr_io_output_out[0] */ 433 TRIG_OUT_MUX_3_HSIOM_TR_IO_OUTPUT1 = 0x40000301u /* ioss.peri_tr_io_output_out[1] */ 434 } en_trig_output_hsiom_t; 435 436 /* Trigger Output Group 4 - CPUSS Debug multiplexer */ 437 typedef enum 438 { 439 TRIG_OUT_MUX_4_CPUSS_CTI_TR_IN0 = 0x40000400u, /* cpuss.cti_tr_in[0] */ 440 TRIG_OUT_MUX_4_CPUSS_CTI_TR_IN1 = 0x40000401u, /* cpuss.cti_tr_in[1] */ 441 TRIG_OUT_MUX_4_SRSS_MCWDT_DEBUG_FREEZE_TR_IN0 = 0x40000403u /* srss.tr_debug_freeze_mcwdt[0] */ 442 } en_trig_output_cpuss_cti_t; 443 444 /* Trigger Output Group 5 - PERI Freeze trigger multiplexer */ 445 typedef enum 446 { 447 TRIG_OUT_MUX_5_PERI_DEBUG_FREEZE_TR_IN = 0x40000500u, /* peri.tr_dbg_freeze */ 448 TRIG_OUT_MUX_5_PDM_DEBUG_FREEZE_TR_IN = 0x40000501u, /* pdm.tr_dbg_freeze */ 449 TRIG_OUT_MUX_5_TDM_DEBUG_FREEZE_TR_IN = 0x40000502u, /* tdm.tr_dbg_freeze */ 450 TRIG_OUT_MUX_5_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000503u /* tcpwm[0].tr_debug_freeze */ 451 } en_trig_output_peri_freeze_t; 452 453 /* Trigger Output Group 6 - TCPWM and PDM trigger multiplexer */ 454 typedef enum 455 { 456 TRIG_OUT_MUX_6_PDM_TR_ACTIVATE0 = 0x40000600u, /* pdm.tr_activate[0] */ 457 TRIG_OUT_MUX_6_PDM_TR_ACTIVATE1 = 0x40000601u /* pdm.tr_activate[1] */ 458 } en_trig_output_tcpwm_pdm_t; 459 460 /* Trigger Output Group 7 - CAN TT Synchronization triggers */ 461 typedef enum 462 { 463 TRIG_OUT_MUX_7_CAN_TT_TR_IN0 = 0x40000700u /* canfd[0].tr_evt_swt_in[0] */ 464 } en_trig_output_cantt_t; 465 466 /* Trigger Output Group 8 - CAN TT Synchronization triggers */ 467 typedef enum 468 { 469 TRIG_OUT_MUX_8_PDMA0_TR_IN4 = 0x40000800u /* cpuss.dw0_tr_in[4] */ 470 } en_trig_output_scb_can0_t; 471 472 /* Trigger Output Group 9 - CAN TT Synchronization triggers */ 473 typedef enum 474 { 475 TRIG_OUT_MUX_9_PDMA0_TR_IN5 = 0x40000900u /* cpuss.dw0_tr_in[5] */ 476 } en_trig_output_scb_can1_t; 477 478 /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ 479 typedef enum 480 { 481 TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN6 = 0x40001000u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[6] */ 482 TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN7 = 0x40001001u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[7] */ 483 TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA1_TR_IN8 = 0x40001002u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[8] */ 484 TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA1_TR_IN9 = 0x40001003u /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[9] */ 485 } en_trig_output_1to1_scb_pdma0_tr_t; 486 487 /* Trigger Output Group 1 - I2S and PDM PDMA triggers (OneToOne) */ 488 typedef enum 489 { 490 TRIG_OUT_1TO1_1_I2S0_TX_TO_PDMA0_TR_IN10 = 0x40001100u, /* From tdm.tr_tx_req[0] to cpuss.dw0_tr_in[10] */ 491 TRIG_OUT_1TO1_1_I2S0_RX_TO_PDMA0_TR_IN11 = 0x40001101u, /* From tdm.tr_rx_req[0] to cpuss.dw0_tr_in[11] */ 492 TRIG_OUT_1TO1_1_PDM0_RX_TO_PDMA0_TR_IN12 = 0x40001102u, /* From pdm.tr_rx_req[0] to cpuss.dw0_tr_in[12] */ 493 TRIG_OUT_1TO1_1_PDM0_RX_TO_PDMA0_TR_IN13 = 0x40001103u, /* From pdm.tr_rx_req[1] to cpuss.dw0_tr_in[13] */ 494 TRIG_OUT_1TO1_1_PDM0_RX_ALL_TO_PDMA0_TR_IN14 = 0x40001104u /* From pdm.tr_rx_req_all to cpuss.dw0_tr_in[14] */ 495 } en_trig_output_1to1_audioss_pdma1_tr_t; 496 497 /* Trigger Output Group 2 - CAN to PDMA0 direct connect (OneToOne) */ 498 typedef enum 499 { 500 TRIG_OUT_1TO1_2_CAN_FIFO1_TO_PDMA0_TR_IN15 = 0x40001200u /* From canfd[0].tr_fifo1[0] to cpuss.dw0_tr_in[15] */ 501 } en_trig_output_1to1_can_to_pdma0_t; 502 503 /* Trigger Output Group 3 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ 504 typedef enum 505 { 506 TRIG_OUT_1TO1_3_PDMA0_TR_OUT0_ACK_TO_CAN_0 = 0x40001300u /* From cpuss.dw0_tr_out[8] to canfd[0].tr_dbg_dma_ack[0] */ 507 } en_trig_output_1to1_can0_dw_ack_t; 508 509 /* Trigger Output Group 4 - Dedicated triggers to LIN[0] (OneToOne) */ 510 typedef enum 511 { 512 TRIG_OUT_1TO1_4_PDMA0_TR_OUT0_ACK_TO_LIN = 0x40001400u, /* From cpuss.dw0_tr_out[9] to lin[0].tr_cmd_tx_header[0] */ 513 TRIG_OUT_1TO1_4_PDMA0_TR_OUT1_ACK_TO_LIN = 0x40001401u /* From cpuss.dw0_tr_out[10] to lin[0].tr_cmd_tx_header[1] */ 514 } en_trig_output_1to1_to_lin0_t; 515 516 /* Level or edge detection setting for a trigger mux */ 517 typedef enum 518 { 519 /* The trigger is a simple level output */ 520 TRIGGER_TYPE_LEVEL = 0u, 521 /* The trigger is synchronized to the consumer blocks clock 522 and a two cycle pulse is generated on this clock */ 523 TRIGGER_TYPE_EDGE = 1u 524 } en_trig_type_t; 525 526 /* Trigger Type Defines */ 527 /* ADCMIC Trigger Types */ 528 #define TRIGGER_TYPE_ADCMIC_TR_ADCMIC_DATA TRIGGER_TYPE_LEVEL 529 #define TRIGGER_TYPE_ADCMIC_TR_ADCMIC_DC TRIGGER_TYPE_LEVEL 530 /* BTSS Trigger Types */ 531 #define TRIGGER_TYPE_BTSS_TR_RX_PACKET_SYNC TRIGGER_TYPE_EDGE 532 #define TRIGGER_TYPE_BTSS_TR_TX_START TRIGGER_TYPE_EDGE 533 /* CANFD Trigger Types */ 534 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE 535 #define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL 536 #define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE 537 #define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL 538 #define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL 539 #define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE 540 /* CPUSS Trigger Types */ 541 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 542 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 543 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 544 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 545 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 546 /* LIN Trigger Types */ 547 #define TRIGGER_TYPE_LIN_TR_CMD_TX_HEADER TRIGGER_TYPE_EDGE 548 /* PDM Trigger Types */ 549 #define TRIGGER_TYPE_PDM_TR_ACTIVATE TRIGGER_TYPE_LEVEL 550 #define TRIGGER_TYPE_PDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 551 #define TRIGGER_TYPE_PDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 552 #define TRIGGER_TYPE_PDM_TR_RX_REQ_ALL TRIGGER_TYPE_LEVEL 553 /* PERI Trigger Types */ 554 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 555 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 556 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 557 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 558 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 559 /* SCB Trigger Types */ 560 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 561 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 562 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 563 /* SMIF Trigger Types */ 564 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 565 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 566 /* SRSS Trigger Types */ 567 #define TRIGGER_TYPE_SRSS_TR_DEBUG_FREEZE_MCWDT TRIGGER_TYPE_LEVEL 568 /* TCPWM Trigger Types */ 569 #define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL 570 /* TDM Trigger Types */ 571 #define TRIGGER_TYPE_TDM_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 572 #define TRIGGER_TYPE_TDM_TR_RX_REQ TRIGGER_TYPE_LEVEL 573 #define TRIGGER_TYPE_TDM_TR_TX_REQ TRIGGER_TYPE_LEVEL 574 575 /* Include IP definitions */ 576 #include "ip/cyip_peri.h" 577 #include "ip/cyip_ppc.h" 578 #include "ip/cyip_peri_pclk.h" 579 #include "ip/cyip_ramc_ppu.h" 580 #include "ip/cyip_icache.h" 581 #include "ip/cyip_cpuss_ppu.h" 582 #include "ip/cyip_ramc.h" 583 #include "ip/cyip_promc.h" 584 #include "ip/cyip_mxcm33.h" 585 #include "ip/cyip_dw.h" 586 #include "ip/cyip_cpuss.h" 587 #include "ip/cyip_ms_ctl_1_2.h" 588 #include "ip/cyip_cpuss_sl_ctl.h" 589 #include "ip/cyip_ipc.h" 590 #include "ip/cyip_srss.h" 591 #include "ip/cyip_pwrmode.h" 592 #include "ip/cyip_backup.h" 593 #include "ip/cyip_cryptolite.h" 594 #include "ip/cyip_hsiom.h" 595 #include "ip/cyip_gpio.h" 596 #include "ip/cyip_smartio.h" 597 #include "ip/cyip_lin.h" 598 #include "ip/cyip_canfd_v3.h" 599 #include "ip/cyip_tcpwm_v2.h" 600 #include "ip/cyip_mxs40adcmic.h" 601 #include "ip/cyip_scb_v4.h" 602 #include "ip/cyip_efuse_v3.h" 603 #include "ip/cyip_efuse_data_v3_cyw20829.h" 604 #include "ip/cyip_smif_v3.h" 605 #include "ip/cyip_tdm.h" 606 #include "ip/cyip_pdm.h" 607 #include "ip/cyip_mxkeyscan.h" 608 #include "ip/cyip_btss.h" 609 610 /* Parameter Defines */ 611 /* Number of TTCAN instances */ 612 #define CANFD_CAN_NR 1u 613 /* ECC logic present or not */ 614 #define CANFD_ECC_PRESENT 0u 615 /* address included in ECC logic or not */ 616 #define CANFD_ECC_ADDR_PRESENT 0u 617 /* Time Stamp counter present or not (required for instance 0, otherwise not 618 allowed) */ 619 #define CANFD_TS_PRESENT 1u 620 /* Message RAM size in KB */ 621 #define CANFD_MRAM_SIZE 4u 622 /* Message RAM address width */ 623 #define CANFD_MRAM_ADDR_WIDTH 10u 624 /* System RAM 0 MPC protection block size in Bytes: 1<< (RAMC0_BLOCK_SIZE+5). 625 Example: 7 = 4KB protection block size. */ 626 #define CPUSS_RAMC0_BLOCK_SIZE 7u 627 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System 628 SRAM0 is implemented with 8 32KB macros. */ 629 #define CPUSS_RAMC0_MACRO_NR 2u 630 /* Number of power partitions in system RAM 0. Each power partition can be 631 independently power controlled using a switch. Example: RAMC0_MACRO_NR = 16 632 and RAMC0_PWR_GROUP_NR = 4 will create 4 power partitions with 4 macros in 633 each power partition. */ 634 #define CPUSS_RAMC0_PWR_GROUP_NR 2u 635 /* System RAM 1 present or not (0=No, 1=Yes) */ 636 #define CPUSS_RAMC1_PRESENT 0u 637 /* System RAM 1 MPC protection block size in Bytes: 1<< (RAMC1_BLOCK_SIZE+5). 638 Example: 7 = 4KB protection block size. */ 639 #define CPUSS_RAMC1_BLOCK_SIZE 7u 640 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 641 RAM 1 is implemented with 8 32KB macros. */ 642 #define CPUSS_RAMC1_MACRO_NR 1u 643 /* Number of power partitions in system RAM 1. Each power partition can be 644 independently power controlled using a switch. Example: RAMC1_MACRO_NR = 16 645 and RAMC1_PWR_GROUP_NR = 4 will create 4 power partitions with 4 macros in 646 each power partition. */ 647 #define CPUSS_RAMC1_PWR_GROUP_NR 1u 648 /* System RAM 2 present or not (0=No, 1=Yes) */ 649 #define CPUSS_RAMC2_PRESENT 0u 650 /* System RAM 2 MPC protection block size in Bytes: 1<< (RAMC2_BLOCK_SIZE+5). 651 Example: 7 = 4KB protection block size. */ 652 #define CPUSS_RAMC2_BLOCK_SIZE 7u 653 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 654 RAM 2 is implemented with 8 32KB macros. */ 655 #define CPUSS_RAMC2_MACRO_NR 1u 656 /* Number of power partitions in system RAM 2. Each power partition can be 657 independently power controlled using a switch. Example: RAMC2_MACRO_NR = 16 658 and RAMC2_PWR_GROUP_NR = 4 will create 4 power partitions with 4 macros in 659 each power partition. */ 660 #define CPUSS_RAMC2_PWR_GROUP_NR 1u 661 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 662 #define CPUSS_RAMC_ECC_PRESENT 0u 663 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 664 #define CPUSS_RAMC_ECC_ADDR_PRESENT 0u 665 /* System Patchable ROM Controller Present or not ('0' : no, '1': yes) */ 666 #define CPUSS_PROMC_PRESENT 1u 667 /* Number of macros used to implement system patchable ROM. Example: 4 if 512 KB 668 system patchable ROM is implemented with 4 128KB macros. */ 669 #define CPUSS_PROMC_MACRO_NR 1u 670 /* PROMC memory block size for protection scheme : 1<< (PROMC_BLOCK_SIZE+5). 671 Example: 7 = 4KB protection block size. */ 672 #define CPUSS_PROMC_BLOCK_SIZE 6u 673 /* Presence of the patch functionality. 0: ROM cannot be patched. 1: ROM can be 674 patched. */ 675 #define CPUSS_PROMC_PATCH_PRESENT 0u 676 /* Number of patchable locations (patch entries). Possible range [32,512] in 677 powers of 2. (BRCM: 512 is only supported) These are implemented using SRAM. 678 (SNPS: 32x128, 64x128, 128x128, 256x128, 512x128 are supported; BRCM: 4 679 instances of 512x32 only supported) */ 680 #define CPUSS_PROMC_PATCH_NR 64u 681 /* Patch size selection of a single structure. 0: 8 Bytes. 1: 16 Bytes. **) 2: 32 682 Bytes. 3: 64 Bytes. **) The patch size should fit to the word size of the 683 ROM. Thus only PATCH_SIZE=1 is supported for this ROM controller. */ 684 #define CPUSS_PROMC_PATCH_SIZE 1u 685 /* Width of compared address bits. The LSB is determined by the PATCH_SIZE, for 16 686 bytes this equals to bit [4]. The MSB is chosen to address the full size of 687 the ROM in bytes. */ 688 #define CPUSS_PROMC_MATCH_ADDR_SIZE 12u 689 /* Initial value of the first patchable address in the ROM. This address and the 690 following higher addresses are patchable if the function is enabled. */ 691 #define CPUSS_PROMC_SROM_BOUNDARY 4096u 692 /* Flash Controller Present or not ('0' : no, '1': yes) */ 693 #define CPUSS_FLASHC_PRESENT 0u 694 /* Flash data output word size (in Bytes) */ 695 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u 696 /* Number of Flash BIST_DATA registers */ 697 #define CPUSS_FLASHC_BIST_DATA_NR 4u 698 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 699 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 700 Flash, and no Work Flash present. */ 701 #define CPUSS_FLASHC_SONOS_RWW 1u 702 /* SONOS Flash, number of main sectors. */ 703 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u 704 /* SONOS Flash, number of rows per main sector. */ 705 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u 706 /* SONOS Flash, number of words per row of main sector. */ 707 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u 708 /* SONOS Flash, number of special sectors. */ 709 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u 710 /* SONOS Flash, number of rows per special sector. */ 711 #define CPUSS_FLASHC_SONOS_SPL_ROWS 64u 712 /* DataWire 0 present or not ('0': no, '1': yes) */ 713 #define CPUSS_DW0_PRESENT 1u 714 /* Number of DataWire 0 channels (8, 16 or 32) */ 715 #define CPUSS_DW0_CH_NR 16u 716 /* DataWire 1 present or not ('0': no, '1': yes) */ 717 #define CPUSS_DW1_PRESENT 0u 718 /* Number of DataWire 1 channels (8, 16 or 32) */ 719 #define CPUSS_DW1_CH_NR 1u 720 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 721 #define CPUSS_DW_ECC_PRESENT 0u 722 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 723 #define CPUSS_DW_ECC_ADDR_PRESENT 0u 724 /* DMA controller-0 present or not ('0': no, '1': yes) */ 725 #define CPUSS_DMAC0_PRESENT 0u 726 /* Number of DMA controller-0 channels ([1, 8]) */ 727 #define CPUSS_DMAC0_CH_NR 1u 728 /* DMA controller-1 present or not ('0': no, '1': yes) */ 729 #define CPUSS_DMAC1_PRESENT 0u 730 /* Number of DMA controller-1 channels ([1, 8]) */ 731 #define CPUSS_DMAC1_CH_NR 1u 732 /* Number of IPC structures. Legal range [1, 16] */ 733 #define CPUSS_IPC_NR 4u 734 /* Number of IPC interrupt structures. Legal range [1, 16] */ 735 #define CPUSS_IPC_IRQ_NR 2u 736 /* Number of protection contexts supported. Legal range [3, 4, 6, 8] (CDT-336698) */ 737 #define CPUSS_PC_NR 4u 738 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 739 CM0+ PCU, which always uses system interrupt functionality. */ 740 #define CPUSS_SYSTEM_IRQ_PRESENT 0u 741 /* Number of total interrupt request inputs to CPUSS */ 742 #define CPUSS_SYSTEM_INT_NR 69u 743 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */ 744 #define CPUSS_SYSTEM_DPSLP_INT_NR 17u 745 /* Number of CPU interrupts used when SYSTEM_IRQ_PRESENT is '1'. Legal values 8, 746 16. */ 747 #define CPUSS_CM33_INT_NR 8u 748 /* Individual CPU interrupts to be disabled when SYSTEM_IRQ_PRESENT is '0'. 0: To 749 enable respective interrupt-bit functionality; 1: To disable respective 750 interrupt-bit functionality; Default value {480{1'b0}} to enable all 480 751 interrupts of CM33; Example: {479{1'b0},1'b1} disables the interrupt IRQ[0] 752 of CM33 and enables all other interrupts. This parameter is NOT applicable 753 when SYSTEM_IRQ_PRESENT is '1'. */ 754 #define CPUSS_CM33_IRQ_DISABLE 0u 755 /* CM33_0 Floating point unit present or not ('0': no, '1': yes) */ 756 #define CPUSS_CM33_0_FPU_PRESENT 0u 757 /* CM33_0 DSP extension present or not ('0': no, '1': yes) */ 758 #define CPUSS_CM33_0_DSP_PRESENT 0u 759 /* CM33_0 Security extension present or not ('0': no, '1': yes) */ 760 #define CPUSS_CM33_0_SECEXT_PRESENT 0u 761 /* CM33_0 non-secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 762 #define CPUSS_CM33_0_MPU_NS_REGION_NR 8u 763 /* CM33_0 secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 764 #define CPUSS_CM33_0_MPU_S_REGION_NR 0u 765 /* CM33_0 SAU regions. Legal values [0, 4, 8] */ 766 #define CPUSS_CM33_0_SAU_REGION_NR 0u 767 /* CM33_1 present or not. */ 768 #define CPUSS_CM33_1_PRESENT 0u 769 /* CM33_1 Floating point unit present or not ('0': no, '1': yes) */ 770 #define CPUSS_CM33_1_FPU_PRESENT 1u 771 /* CM33_1 DSP extension present or not ('0': no, '1': yes) */ 772 #define CPUSS_CM33_1_DSP_PRESENT 1u 773 /* CM33_1 Security extension present or not ('0': no, '1': yes) */ 774 #define CPUSS_CM33_1_SECEXT_PRESENT 1u 775 /* CM33_1 non-secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 776 #define CPUSS_CM33_1_MPU_NS_REGION_NR 16u 777 /* CM33_1 secure MPU regions. Legal values [0, 4, 8, 12, 16] */ 778 #define CPUSS_CM33_1_MPU_S_REGION_NR 16u 779 /* CM33_1 SAU regions. Legal values [0, 4, 8] */ 780 #define CPUSS_CM33_1_SAU_REGION_NR 8u 781 /* Cache RAM size in Kilo Bytes; Supported values are [8, 16, 32]. */ 782 #define CPUSS_CACHE_SIZE 8u 783 /* Cache RAM ECC present or not ('0': no, '1': yes) */ 784 #define CPUSS_CACHE_RAM_ECC_PRESENT 0u 785 /* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 786 breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 787 watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ 788 #define CPUSS_DEBUG_LVL 2u 789 /* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + 790 ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace 791 level is not supported in CPUSS. */ 792 #define CPUSS_TRACE_LVL 1u 793 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */ 794 #define CPUSS_ETB_PRESENT 0u 795 /* PTM interface present (0=No, 1=Yes) */ 796 #define CPUSS_PTM_PRESENT 0u 797 /* Width of the PTM interface in bits ([2,32]) */ 798 #define CPUSS_PTM_WIDTH 1u 799 /* Width of the TPIU interface in bits ([1,4]) */ 800 #define CPUSS_TPIU_WIDTH 4u 801 /* CPUSS external CODE master interface 0 present or not on CODE infrastructure. 802 ('0': no, '1': yes). */ 803 #define CPUSS_CODE_MS_0_PRESENT 0u 804 /* CPUSS external SYS master interface 0 present or not on SYS infrastructure. 805 ('0': no, '1': yes). */ 806 #define CPUSS_SYS_MS_0_PRESENT 1u 807 /* CPUSS external SYS master interface 1 present or not on SYS infrastructure. 808 ('0': no, '1': yes). */ 809 #define CPUSS_SYS_MS_1_PRESENT 0u 810 /* CPUSS external SYS master NVM interface 0 present or not on SYS infrastructure. 811 ('0': no, '1': yes). */ 812 #define CPUSS_SYS_MS_0_NVM_PRESENT 0u 813 /* CPUSS external SYS master NVM interface 1 present or not on SYS infrastructure. 814 ('0': no, '1': yes). */ 815 #define CPUSS_SYS_MS_1_NVM_PRESENT 0u 816 /* Number of external AHB5 slave interfaces connected to SYSTEM infrastructure. 817 Maximum number of slaves supported is 4. Width of this parameter is 4-bits. 818 1-bit mask for each slave indicating present or not. Example: 4'b0001 - slave 819 0 is present. */ 820 #define CPUSS_SYS_SL_PRESENT 1u 821 /* Number of external EXPANSION masters driving the EXP AHB5 infrastructure. 822 Maximum number of masters supported is 8. Width of this parameter is 8-bits. 823 1-bit mask for each master indicating present or not. Example: 8'b0000_0101 - 824 master 0 & master 2 are present. */ 825 #define CPUSS_EXP_MS_PRESENT 1u 826 /* The timing de-coupled AHB brdige is present or not on the output of EXP 827 infrastructure. ('0': no, '1':yes) */ 828 #define CPUSS_EXP_BRIDGE_PRESENT 1u 829 /* Specifies the CODE interconnect is present or not; 0: Not present; 1: Present; */ 830 #define CPUSS_CODE_INFRA_PRESENT 1u 831 /* Specifies the CODE interconnect arbitration type used for generating the RTL. 832 0: ROUND; round insert an extra cycle each time the downstream port selects a 833 new upstream port to service and must be used to avoid timing issues when 834 target frequency is >=100MHz; 1: ROUND_NOLAT; round_nolat have no such 835 latency and can be used when target frequency is <100MHz; Improves the 836 performance by reducing latency; */ 837 #define CPUSS_CODE_INFRA_ARB_TYPE 1u 838 /* Specifies the SYSTEM interconnect arbitration type used for generating the RTL. 839 0: ROUND; round insert an extra cycle each time the downstream port selects a 840 new upstream port to service and must be used to avoid timing issues when 841 target frequency is >=100MHz; 1: ROUND_NOLAT; round_nolat have no such 842 latency and can be used when target frequency is <100MHz; Improves the 843 performance by reducing latency; */ 844 #define CPUSS_SYSTEM_INFRA_ARB_TYPE 1u 845 /* Specifies the EXPANSION interconnect arbitration type used for generating the 846 RTL. 0: ROUND; round insert an extra cycle each time the downstream port 847 selects a new upstream port to service and must be used to avoid timing 848 issues when target frequency is >=100MHz; 1: ROUND_NOLAT; round_nolat have no 849 such latency and can be used when target frequency is <100MHz; Improves the 850 performance by reducing latency; */ 851 #define CPUSS_EXP_INFRA_ARB_TYPE 1u 852 /* CoreSight Part Identification Number */ 853 #define CPUSS_JEPID 52u 854 /* CoreSight Part Identification Number */ 855 #define CPUSS_JEPCONTINUATION 0u 856 /* CoreSight Part Identification Number */ 857 #define CPUSS_FAMILYID 272u 858 /* ROM trim register width (for ARM 3, for Synopsys 5, for BRCM 6) */ 859 #define CPUSS_ROM_TRIM_WIDTH 5u 860 /* ROM trim register default (for both ARM and Synopsys 0x0000_0002; for BRCM 861 0x0000_0000) */ 862 #define CPUSS_ROM_TRIM_DEFAULT 18u 863 /* RAM trim register width (for ARM 8, for SNPS 15, for BRCM 16) For SNPS: SRAM 864 will get its trim value from trim[15:0] and RF from trim [31:16] */ 865 #define CPUSS_RAM_TRIM_WIDTH 32u 866 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012, 867 for BRCM 0x0000_0000) */ 868 #define CPUSS_RAM_TRIM_DEFAULT 16403u 869 /* RAM Trim control-2 register present or not; 1-present; 0-not present; Place 870 holder for S22 SRAM memories. */ 871 #define CPUSS_TRIM_RAM_CTL2_PRESENT 0u 872 /* RAM trim register width Place holder for S22 SRAM memories. */ 873 #define CPUSS_RAM_TRIM_WIDTH2 32u 874 /* RAM trim register default. Place holder for S22 SRAM memories. */ 875 #define CPUSS_RAM_TRIM_DEFAULT2 24594u 876 /* RAM Trim control-3 register present or not; 1-present; 0-not present; Place 877 holder for S22 SRAM memories. */ 878 #define CPUSS_TRIM_RAM_CTL3_PRESENT 0u 879 /* RAM trim register width Place holder for S22 SRAM memories. */ 880 #define CPUSS_RAM_TRIM_WIDTH3 32u 881 /* RAM trim register default. Place holder for S22 SRAM memories. */ 882 #define CPUSS_RAM_TRIM_DEFAULT3 24594u 883 /* RAM Trim control-4 register present or not; 1-present; 0-not present; Place 884 holder for S22 SRAM memories. */ 885 #define CPUSS_TRIM_RAM_CTL4_PRESENT 0u 886 /* RAM trim register width Place holder for S22 SRAM memories. */ 887 #define CPUSS_RAM_TRIM_WIDTH4 32u 888 /* RAM trim register default. Place holder for S22 SRAM memories. */ 889 #define CPUSS_RAM_TRIM_DEFAULT4 24594u 890 /* Specifies the CM33-0 CACHE SRAM POWER SWITCH is present or not; 0: Not present; 891 1: Present; */ 892 #define CPUSS_CM33_0_CACHE_SWITCH_PRESENT 1u 893 /* Specifies the CM33-1 CACHE SRAM POWER SWITCH is present or not; 0: Not present; 894 1: Present; */ 895 #define CPUSS_CM33_1_CACHE_SWITCH_PRESENT 0u 896 /* Specifies the DW-0 SRAM POWER SWITCH is present or not; 0: Not present; 1: 897 Present; */ 898 #define CPUSS_DW0_SWITCH_PRESENT 0u 899 /* Specifies the DW-1 SRAM POWER SWITCH is present or not; 0: Not present; 1: 900 Present; */ 901 #define CPUSS_DW1_SWITCH_PRESENT 0u 902 /* Specifies the MPC SRAM POWER SWITCH is present or not; 0: Not present; 1: 903 Present; */ 904 #define CPUSS_MPC_SWITCH_PRESENT 0u 905 /* Specifies the PROMC Patch-SRAM POWER SWITCH is present or not; 0: Not present; 906 1: Present; */ 907 #define CPUSS_PROMC_SWITCH_PRESENT 0u 908 /* External Crystal Oscillator is present (high frequency) */ 909 #define CPUSS_ECO_PRESENT 0u 910 /* System RAM 0 size in KB */ 911 #define CPUSS_CHIP_TOP_RAMC0_SIZE 128u 912 /* System RAM 1 size in kilobytes */ 913 #define CPUSS_CHIP_TOP_RAMC1_SIZE 1u 914 /* System RAM 2 size in kilobytes */ 915 #define CPUSS_CHIP_TOP_RAMC2_SIZE 1u 916 /* System Patchable ROM size in KB */ 917 #define CPUSS_CHIP_TOP_PROMC_SIZE 64u 918 /* Flash main region size in KB */ 919 #define CPUSS_CHIP_TOP_FLASH_SIZE 2048u 920 /* Flash work region size in KB (EEPROM emulation, data) */ 921 #define CPUSS_CHIP_TOP_WFLASH_SIZE 32u 922 /* Flash supervisory region size in KB */ 923 #define CPUSS_CHIP_TOP_SFLASH_SIZE 32u 924 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 925 #define CPUSS_CHIP_TOP_ETB_SRAM_SIZE 2u 926 /* See MMIO2 instantiation or not */ 927 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u 928 /* ETAS Calibration support pin out present (automotive only) */ 929 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u 930 /* TRACE_LVL>0 */ 931 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 932 /* Number of protection contexts supported. Legal range [3, 4, 6, 8] (CDT-336698) */ 933 #define CPUSS_MS_CTL_STRUCT_PC_NR 4u 934 /* IP MMIO registers base address in the system address space (32-bit Byte address 935 at a 64 kB multiple). The IP MMIO registers occupy a 64 kB memory region in 936 the system address space. */ 937 #define CRYPTOLITE_ADDR_BASE 1076035584u 938 /* ECC present or not ('0': no, '1': yes). */ 939 #define CRYPTOLITE_ECC_PRESENT 0u 940 /* True random number generation component support ('0': no, '1': yes). */ 941 #define CRYPTOLITE_TRNG_PRESENT 0u 942 /* Vector unit component support ('0': no, '1': yes). */ 943 #define CRYPTOLITE_VU_PRESENT 0u 944 /* SHA-256 hash component support ('0': no, '1': yes). */ 945 #define CRYPTOLITE_SHA_PRESENT 1u 946 /* AES-128 block cipher component support ('0': no, '1': yes). */ 947 #define CRYPTOLITE_AES_PRESENT 0u 948 /* Number of HFCLK roots present. Must be > 0. Must be same as set for SRSS */ 949 #define DFT_NUM_HFROOT 4u 950 /* Width of clk_occ_fast output bus (number of external OCCs) */ 951 #define DFT_EXT_OCC 0u 952 /* Number of PLLs usable as struct mode clock source (number of clk_occ_fast 953 clocks). Not expected to be more than 4 */ 954 #define DFT_NUM_FASTCLK 1u 955 /* Number of select signals to control each FASTCLK multiplexer. Not expected to 956 be more than 2 */ 957 #define DFT_NUM_FASTCLK_SEL 1u 958 /* Number of MBIST controllers with corresponding mbist(pg)_done and mbist(pg)_go 959 signals. Value defined by CIC during Pass 1. */ 960 #define DFT_MBIST_C_NUM 7u 961 /* Number of LBIST controllers. One LBIST controller on top level and one LBIST 962 controller in each optional HDFT block */ 963 #define DFT_LBIST_C_NUM 1u 964 /* Number of MBISR chains. Separate chains are required for power domains that can 965 be enabled independently */ 966 #define DFT_MBISR_CH_NUM 1u 967 /* Defines if (Burn-In) Monitor function is present */ 968 #define DFT_MONITOR_PRESENT 1u 969 /* Defines if Mentor BISR controller is present (controls generation of control 970 and status register) */ 971 #define DFT_MENTOR_BISR_PRESENT 1u 972 /* Defines if Direct MBIST Access function is present (controls generation of 973 control and status registers) */ 974 #define DFT_DIRECT_MBIST_ACCESS_PRESENT 0u 975 /* Defines if DIRECT_MBIST*SEL and DIRECT_MBIST*_RESULT registers are generated 976 (only used for DIRECT_MBIST_ACCESS_PRESENT=1) */ 977 #define DFT_DIRECT_MBIST_CTRL_ACCESS_PRESENT 0u 978 /* Controls generation of BIST_STEP_SEL_EN and BIST_STEP_SEL register fields 979 within DIRECT_MBIST_CTL reg (only used for DIRECT_MBIST_ACCESS_PRESENT=1) */ 980 #define DFT_DIRECT_MBIST_STEP_ACCESS_PRESENT 0u 981 /* Controls generation of BIST_MEM_SEL_EN and BIST_MEM_SEL register fields within 982 DIRECT_MBIST_CTL reg (only used for DIRECT_MBIST_ACCESS_PRESENT=1) */ 983 #define DFT_DIRECT_MBIST_MEM_ACCESS_PRESENT 0u 984 /* Number of HLBs with Direct MBIST Access function (only used for 985 DIRECT_MBIST_ACCESS_PRESENT=1) */ 986 #define DFT_DIRECT_MBIST_BAP_NUM 1u 987 /* Maximum value of MBIST controllers connected to single BAP (only used for 988 DIRECT_MBIST_ACCESS_PRESENT=1) */ 989 #define DFT_DIRECT_MBIST_CTRL_NUM 1u 990 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST0_COMPLETED 991 register */ 992 #define DFT_MBIST0_C_NUM 7u 993 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST1_COMPLETED 994 register */ 995 #define DFT_MBIST1_C_NUM 1u 996 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST2_COMPLETED 997 register */ 998 #define DFT_MBIST2_C_NUM 1u 999 /* local parameter: Number of MBIST controllers mapped to BISTMON_MBIST3_COMPLETED 1000 register */ 1001 #define DFT_MBIST3_C_NUM 1u 1002 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST0_SEL and 1003 DIRECT_MBIST0_RESULT registers */ 1004 #define DFT_DIRECT_MBIST0_CTRL_NUM 1u 1005 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST1_SEL and 1006 DIRECT_MBIST1_RESULT registers */ 1007 #define DFT_DIRECT_MBIST1_CTRL_NUM 1u 1008 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST2_SEL and 1009 DIRECT_MBIST2_RESULT registers */ 1010 #define DFT_DIRECT_MBIST2_CTRL_NUM 1u 1011 /* local parameter: Number of MBIST controllers mapped to DIRECT_MBIST3_SEL and 1012 DIRECT_MBIST3_RESULT registers */ 1013 #define DFT_DIRECT_MBIST3_CTRL_NUM 1u 1014 /* Must be set to 1 when using this mxdft version in MXS40Sv2 devices */ 1015 #define DFT_PLATFORM_MXS40SV2 1u 1016 /* Defines if VCCRET supply is generated in UPF. Must be set to 1 in MXS40S* 1017 technologies and to 0 in MXS40E */ 1018 #define DFT_VCCRET_PRESENT 1u 1019 /* Defines if UPF is generated for S28 technology (1) or S40 technolgy (0) */ 1020 #define DFT_TECH_S28 0u 1021 /* Controls the polulation of the "accessed" monitor bits <IOBSC,0,MBIST,LBIST>. 1022 Default = 4'b1011 */ 1023 #define DFT_POP_ACC 10u 1024 /* Controls the polulation of the "started" monitor bits 1025 <0,FLASH_DBI,MBIST,LBIST>. Default = 4'b0111 */ 1026 #define DFT_POP_START 2u 1027 /* Controls the polulation of the "done" (completed) monitor bits 1028 <0,FLASH_DBI,MBIST,LBIST>. Default = 4'b0111 */ 1029 #define DFT_POP_DONE 2u 1030 /* Controls the polulation of the "failed" monitor bits <0,0,MBIST,LBIST>. Default 1031 = 4'b0011 */ 1032 #define DFT_POP_FAIL 2u 1033 /* Used for mxdft_tap: controls generation of logic for "TDR capture&update via 1034 MMIO" (default value is 1) */ 1035 #define DFT_CAP_UP_PRESENT 0u 1036 /* Number of DataWire channels ([1, 512]) */ 1037 #define DW_CH_NR 16u 1038 /* DataWire SRAM ECC present or not ('0': no, '1': yes) */ 1039 #define DW_ECC_PRESENT 0u 1040 /* DataWire SRAM address ECC present or not ('0': no, '1': yes) */ 1041 #define DW_ECC_ADDR_PRESENT 0u 1042 #define DW_CH_NR_WIDTH 1u 1043 #define DW_CH_STRUCT_ECC_PRESENT 0u 1044 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [4,8,12,16] */ 1045 #define EFUSE_EFUSE_NR 4u 1046 /* Enables limiting access to region defined by PROT_MASTER_START/END by 1047 PROT_MASTER */ 1048 #define EFUSE_BLOCK_NVM_CRYPTO 0u 1049 /* Begining of region of EFUSE only accessible by master defined by PROT_MASTER. */ 1050 #define EFUSE_PROT_MASTER_START 4092u 1051 /* End of region of EFUSE (last address) only accessible by master defined by 1052 PROT_MASTER. */ 1053 #define EFUSE_PROT_MASTER_END 4092u 1054 /* The Master with permission to access the region defined by 1055 PROT_MASTER_START/PROT_MASTER_END */ 1056 #define EFUSE_PROT_MASTER 255u 1057 /* Cache SRAM ECC present or not ('0': no, '1': yes) */ 1058 #define ICACHE_ECC_PRESENT 0u 1059 /* Number of GPIO ports in range 0..31 */ 1060 #define IOSS_GPIO_GPIO_PORT_NR_0_31 6u 1061 /* Number of GPIO ports in range 32..63 */ 1062 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 1063 /* Number of GPIO ports in range 64..95 */ 1064 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 1065 /* Number of GPIO ports in range 96..127 */ 1066 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 1067 /* Number of ports in device */ 1068 #define IOSS_GPIO_GPIO_PORT_NR 6u 1069 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1070 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 1071 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1072 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 1073 /* Indicates port is an HSIO port */ 1074 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_HSIO 0u 1075 /* Indicates port is a GPIO_SMC */ 1076 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO_SMC 0u 1077 /* Indicates port is a HSIO_ENH */ 1078 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_HSIO_ENH 0u 1079 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1080 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u 1081 /* Indicates port supports drive select trims */ 1082 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DS_CTRL 0u 1083 /* Indicates port supports slew extension bits */ 1084 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_EXT 1u 1085 /* Indicates port supports drive select extension trims */ 1086 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_EXT 1u 1087 /* Indicates slew bit width */ 1088 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLEW_WIDTH 1u 1089 /* Indicates drive bit width */ 1090 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_DRIVE_WIDTH 3u 1091 /* Indicates that pin #0 exists for this port with slew control feature */ 1092 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 0u 1093 /* Indicates that pin #1 exists for this port with slew control feature */ 1094 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 0u 1095 /* Indicates that pin #2 exists for this port with slew control feature */ 1096 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 0u 1097 /* Indicates that pin #3 exists for this port with slew control feature */ 1098 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 0u 1099 /* Indicates that pin #4 exists for this port with slew control feature */ 1100 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 0u 1101 /* Indicates that pin #5 exists for this port with slew control feature */ 1102 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 0u 1103 /* Indicates that pin #6 exists for this port with slew control feature */ 1104 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 1105 /* Indicates that pin #7 exists for this port with slew control feature */ 1106 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 1107 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1108 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 1109 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1110 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 1111 /* Indicates port is an HSIO port */ 1112 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_HSIO 0u 1113 /* Indicates port is a GPIO_SMC */ 1114 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO_SMC 0u 1115 /* Indicates port is a HSIO_ENH */ 1116 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_HSIO_ENH 0u 1117 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1118 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u 1119 /* Indicates port supports drive select trims */ 1120 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DS_CTRL 0u 1121 /* Indicates port supports slew extension bits */ 1122 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_EXT 1u 1123 /* Indicates port supports drive select extension trims */ 1124 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_EXT 1u 1125 /* Indicates slew bit width */ 1126 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLEW_WIDTH 1u 1127 /* Indicates drive bit width */ 1128 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_DRIVE_WIDTH 3u 1129 /* Indicates that pin #0 exists for this port with slew control feature */ 1130 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 0u 1131 /* Indicates that pin #1 exists for this port with slew control feature */ 1132 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 0u 1133 /* Indicates that pin #2 exists for this port with slew control feature */ 1134 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 0u 1135 /* Indicates that pin #3 exists for this port with slew control feature */ 1136 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u 1137 /* Indicates that pin #4 exists for this port with slew control feature */ 1138 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u 1139 /* Indicates that pin #5 exists for this port with slew control feature */ 1140 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u 1141 /* Indicates that pin #6 exists for this port with slew control feature */ 1142 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 1143 /* Indicates that pin #7 exists for this port with slew control feature */ 1144 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 1145 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1146 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 1147 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1148 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 1149 /* Indicates port is an HSIO port */ 1150 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_HSIO 1u 1151 /* Indicates port is a GPIO_SMC */ 1152 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO_SMC 0u 1153 /* Indicates port is a HSIO_ENH */ 1154 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_HSIO_ENH 0u 1155 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1156 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u 1157 /* Indicates port supports drive select trims */ 1158 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DS_CTRL 0u 1159 /* Indicates port supports slew extension bits */ 1160 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_EXT 1u 1161 /* Indicates port supports drive select extension trims */ 1162 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_EXT 1u 1163 /* Indicates slew bit width */ 1164 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLEW_WIDTH 1u 1165 /* Indicates drive bit width */ 1166 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_DRIVE_WIDTH 3u 1167 /* Indicates that pin #0 exists for this port with slew control feature */ 1168 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 0u 1169 /* Indicates that pin #1 exists for this port with slew control feature */ 1170 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 0u 1171 /* Indicates that pin #2 exists for this port with slew control feature */ 1172 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 0u 1173 /* Indicates that pin #3 exists for this port with slew control feature */ 1174 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 0u 1175 /* Indicates that pin #4 exists for this port with slew control feature */ 1176 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 0u 1177 /* Indicates that pin #5 exists for this port with slew control feature */ 1178 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 0u 1179 /* Indicates that pin #6 exists for this port with slew control feature */ 1180 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 0u 1181 /* Indicates that pin #7 exists for this port with slew control feature */ 1182 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 0u 1183 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1184 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 1185 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1186 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 1187 /* Indicates port is an HSIO port */ 1188 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_HSIO 0u 1189 /* Indicates port is a GPIO_SMC */ 1190 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO_SMC 0u 1191 /* Indicates port is a HSIO_ENH */ 1192 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_HSIO_ENH 0u 1193 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1194 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u 1195 /* Indicates port supports drive select trims */ 1196 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DS_CTRL 0u 1197 /* Indicates port supports slew extension bits */ 1198 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_EXT 1u 1199 /* Indicates port supports drive select extension trims */ 1200 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_EXT 1u 1201 /* Indicates slew bit width */ 1202 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLEW_WIDTH 1u 1203 /* Indicates drive bit width */ 1204 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_DRIVE_WIDTH 3u 1205 /* Indicates that pin #0 exists for this port with slew control feature */ 1206 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 0u 1207 /* Indicates that pin #1 exists for this port with slew control feature */ 1208 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 0u 1209 /* Indicates that pin #2 exists for this port with slew control feature */ 1210 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u 1211 /* Indicates that pin #3 exists for this port with slew control feature */ 1212 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u 1213 /* Indicates that pin #4 exists for this port with slew control feature */ 1214 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u 1215 /* Indicates that pin #5 exists for this port with slew control feature */ 1216 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u 1217 /* Indicates that pin #6 exists for this port with slew control feature */ 1218 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 1219 /* Indicates that pin #7 exists for this port with slew control feature */ 1220 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 1221 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1222 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 1223 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1224 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 1225 /* Indicates port is an HSIO port */ 1226 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_HSIO 0u 1227 /* Indicates port is a GPIO_SMC */ 1228 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO_SMC 0u 1229 /* Indicates port is a HSIO_ENH */ 1230 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_HSIO_ENH 0u 1231 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1232 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u 1233 /* Indicates port supports drive select trims */ 1234 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DS_CTRL 0u 1235 /* Indicates port supports slew extension bits */ 1236 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_EXT 1u 1237 /* Indicates port supports drive select extension trims */ 1238 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_EXT 1u 1239 /* Indicates slew bit width */ 1240 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLEW_WIDTH 1u 1241 /* Indicates drive bit width */ 1242 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_DRIVE_WIDTH 3u 1243 /* Indicates that pin #0 exists for this port with slew control feature */ 1244 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 1u 1245 /* Indicates that pin #1 exists for this port with slew control feature */ 1246 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 1u 1247 /* Indicates that pin #2 exists for this port with slew control feature */ 1248 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u 1249 /* Indicates that pin #3 exists for this port with slew control feature */ 1250 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u 1251 /* Indicates that pin #4 exists for this port with slew control feature */ 1252 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 1253 /* Indicates that pin #5 exists for this port with slew control feature */ 1254 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 1255 /* Indicates that pin #6 exists for this port with slew control feature */ 1256 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 1257 /* Indicates that pin #7 exists for this port with slew control feature */ 1258 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 1259 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 1260 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 1261 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 1262 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 1263 /* Indicates port is an HSIO port */ 1264 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_HSIO 0u 1265 /* Indicates port is a GPIO_SMC */ 1266 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO_SMC 0u 1267 /* Indicates port is a HSIO_ENH */ 1268 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_HSIO_ENH 0u 1269 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 1270 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u 1271 /* Indicates port supports drive select trims */ 1272 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DS_CTRL 0u 1273 /* Indicates port supports slew extension bits */ 1274 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_EXT 1u 1275 /* Indicates port supports drive select extension trims */ 1276 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_EXT 1u 1277 /* Indicates slew bit width */ 1278 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLEW_WIDTH 1u 1279 /* Indicates drive bit width */ 1280 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_DRIVE_WIDTH 3u 1281 /* Indicates that pin #0 exists for this port with slew control feature */ 1282 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 0u 1283 /* Indicates that pin #1 exists for this port with slew control feature */ 1284 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 0u 1285 /* Indicates that pin #2 exists for this port with slew control feature */ 1286 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 0u 1287 /* Indicates that pin #3 exists for this port with slew control feature */ 1288 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u 1289 /* Indicates that pin #4 exists for this port with slew control feature */ 1290 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u 1291 /* Indicates that pin #5 exists for this port with slew control feature */ 1292 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u 1293 /* Indicates that pin #6 exists for this port with slew control feature */ 1294 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 0u 1295 /* Indicates that pin #7 exists for this port with slew control feature */ 1296 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 0u 1297 /* Power Switch exists */ 1298 #define IOSS_GPIO_PWRSW 0u 1299 /* Number of AMUX splitter cells */ 1300 #define IOSS_HSIOM_AMUX_SPLIT_NR 1u 1301 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 1302 #define IOSS_HSIOM_HSIOM_PORT_NR 6u 1303 /* Number of PWR/GND MONITOR CELLs in the device */ 1304 #define IOSS_HSIOM_MONITOR_NR 0u 1305 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 1306 #define IOSS_HSIOM_MONITOR_NR_0_31 0u 1307 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 1308 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 1309 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 1310 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 1311 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 1312 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 1313 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 1314 #define IOSS_HSIOM_HSIOM_SEC_PORT_NR 0u 1315 /* Mask of SMARTIO instances presence */ 1316 #define IOSS_SMARTIO_SMARTIO_MASK 8u 1317 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 1318 #define IPC_PA_SIZE 32u 1319 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 1320 #define IPC_MASTER_WIDTH 6u 1321 #define IPC_IPC_NR 4u 1322 #define IPC_IPC_IRQ_NR 2u 1323 /* Number of LIN channels ([2, 32]). For test functionality (two channels are 1324 connected), the minimal number of LIN channels is 2. */ 1325 #define LIN_CH_NR 2u 1326 /* Number of AHB5 "hmaster[]" bits ([1, 8]). */ 1327 #define LIN_MASTER_WIDTH 6u 1328 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 1329 8=T28HPL, 9=T28HPC */ 1330 #define LIN_CHIP_TOP_PLATFORM_VARIANT 6u 1331 /* CM33[0] should be 0, CM33[1] should have 1 */ 1332 #define MXCM33_CPU_WAIT_DEFAULT 0u 1333 /* Number of CPU interrupts used when SYSTEM_IRQ_PRESENT is '1'. Legal values 8, 1334 16. */ 1335 #define MXCM33_CM33_INT_NR 8u 1336 /* IRQ expander present ('0': no, '1': yes) */ 1337 #define MXCM33_SYSTEM_IRQ_PRESENT 0u 1338 /* CM33[0] should be 1, CM33[1] should have 0 */ 1339 #define MXCM33_PC_MON_PRESENT 1u 1340 /* Number of system interrupt inputs to CPUSS */ 1341 #define MXCM33_SYSTEM_INT_NR 69u 1342 /* TrustZone security extention present or not */ 1343 #define MXCM33_SECEXT 0u 1344 /* FPU extention present or not */ 1345 #define MXCM33_FPU_PRESENT 0u 1346 /* DSP extention present or not */ 1347 #define MXCM33_DSP_PRESENT 0u 1348 /* AHB5 master bus width */ 1349 #define MXKEYSCAN_AHB_MASTER_WIDTH 6u 1350 /* AHB5 address bus width */ 1351 #define MXKEYSCAN_AHB_ADDR_WIDTH 12u 1352 /* AHB5 user bus width */ 1353 #define MXKEYSCAN_AHB_USER_WIDTH 4u 1354 /* AHB5 prot bus width */ 1355 #define MXKEYSCAN_AHB_PROT_WIDTH 7u 1356 /* Number of keyboard rows as input */ 1357 #define MXKEYSCAN_NUM_ROWS_IN 8u 1358 /* Number of keyboard columns as output */ 1359 #define MXKEYSCAN_NUM_COLS_OUT 18u 1360 /* CELL VT selection for ACTIVE Domain */ 1361 #define MXKEYSCAN_CELL_VT_TYPE_ACTIVE 1u 1362 /* CELL VT selection DEEEPSLEEP Domain */ 1363 #define MXKEYSCAN_CELL_VT_TYPE_DPSLP 0u 1364 /* Number of PDM structures ({2, 4, 6, 8}]). */ 1365 #define PDM_NR 2u 1366 /* Master interface presence mask (4 bits) */ 1367 #define PERI_MS_PRESENT 3u 1368 /* Clock control functionality present ('0': no, '1': yes) */ 1369 #define PERI_GROUP_PRESENT0_PERI_GROUP_CLOCK_PRESENT 0u 1370 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1371 Group-1 to Group-15 it is 32'h000_0000 */ 1372 #define PERI_GROUP_PRESENT0_PERI_GROUP_SL_CTL_DEFAULT 4294967295u 1373 /* Clock control functionality present ('0': no, '1': yes) */ 1374 #define PERI_GROUP_PRESENT1_PERI_GROUP_CLOCK_PRESENT 1u 1375 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1376 Group-1 to Group-15 it is 32'h000_0000 */ 1377 #define PERI_GROUP_PRESENT1_PERI_GROUP_SL_CTL_DEFAULT 0u 1378 /* Clock control functionality present ('0': no, '1': yes) */ 1379 #define PERI_GROUP_PRESENT2_PERI_GROUP_CLOCK_PRESENT 1u 1380 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1381 Group-1 to Group-15 it is 32'h000_0000 */ 1382 #define PERI_GROUP_PRESENT2_PERI_GROUP_SL_CTL_DEFAULT 0u 1383 /* Clock control functionality present ('0': no, '1': yes) */ 1384 #define PERI_GROUP_PRESENT3_PERI_GROUP_CLOCK_PRESENT 0u 1385 /* Default value for SL_CTL register value on POR. Group-0 it is 32'hFFFF_FFFF 1386 Group-1 to Group-15 it is 32'h000_0000 */ 1387 #define PERI_GROUP_PRESENT3_PERI_GROUP_SL_CTL_DEFAULT 0u 1388 /* Number of asynchronous PCLK groups */ 1389 #define PERI_PCLK_GROUP_NR 7u 1390 /* Defines the width of INTR_AHB_ERROR.AHB_ERROR_VIO register width based on 1391 number of peripheral groups enabled and AHB error reporting is enabled 1392 (AHB_ERROR_PRESENT==1) */ 1393 #define PERI_GROUP_AHB_ERROR_WIDTH 4u 1394 /* Defines the width of INTR_AHB_ERROR.TIMEOUT_VIO register width based on number 1395 of peripheral groups present and timeout error reporting logic is present 1396 (TIMEOUT_PRESENT==1). Note that group-0 is excluded from timeout reporting, 1397 so max width is 15 (group-1 to group-15). */ 1398 #define PERI_GROUP_TIMEOUT_WIDTH 3u 1399 /* Timeout functionality present ('0': no, '1': yes) */ 1400 #define PERI_TIMEOUT_PRESENT 1u 1401 /* AHB ERROR response reporting present ('0': no, '1':yes) */ 1402 #define PERI_AHB_ERROR_PRESENT 1u 1403 /* Trigger module present ('0': no, '1': yes) */ 1404 #define PERI_TR 1u 1405 /* Number of trigger groups */ 1406 #define PERI_TR_GROUP_NR 10u 1407 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1408 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1409 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1410 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1411 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1412 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1413 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1414 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1415 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1416 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1417 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1418 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1419 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1420 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1421 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1422 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1423 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1424 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1425 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 1426 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 1427 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1428 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1429 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1430 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1431 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1432 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1433 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1434 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1435 /* 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 1436 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 1437 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 1438 #define PERI_GR_DIV_ADDR_WIDTH 4u 1439 /* Number of asynchronous PCLK groups */ 1440 #define PERI_PERI_PCLK_PCLK_GROUP_NR 7u 1441 /* Number of 8.0 dividers */ 1442 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 0u 1443 /* Number of 16.0 dividers */ 1444 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 0u 1445 /* Number of 16.5 (fractional) dividers */ 1446 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0u 1447 /* Number of 24.5 (fractional) dividers */ 1448 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 1u 1449 /* Number of programmable clocks [1, 256] */ 1450 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT 1u 1451 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1452 #define PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_PCLK_DIV_PRESENT 1u 1453 /* Number of 8.0 dividers */ 1454 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 5u 1455 /* Number of 16.0 dividers */ 1456 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 4u 1457 /* Number of 16.5 (fractional) dividers */ 1458 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 2u 1459 /* Number of 24.5 (fractional) dividers */ 1460 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 1u 1461 /* Number of programmable clocks [1, 256] */ 1462 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT 16u 1463 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1464 #define PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_PCLK_DIV_PRESENT 1u 1465 /* Number of 8.0 dividers */ 1466 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0u 1467 /* Number of 16.0 dividers */ 1468 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0u 1469 /* Number of 16.5 (fractional) dividers */ 1470 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0u 1471 /* Number of 24.5 (fractional) dividers */ 1472 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0u 1473 /* Number of programmable clocks [1, 256] */ 1474 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_CLOCK_VECT 0u 1475 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1476 #define PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_PCLK_DIV_PRESENT 0u 1477 /* Number of 8.0 dividers */ 1478 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0u 1479 /* Number of 16.0 dividers */ 1480 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0u 1481 /* Number of 16.5 (fractional) dividers */ 1482 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 2u 1483 /* Number of 24.5 (fractional) dividers */ 1484 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0u 1485 /* Number of programmable clocks [1, 256] */ 1486 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_CLOCK_VECT 2u 1487 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1488 #define PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_PCLK_DIV_PRESENT 1u 1489 /* Number of 8.0 dividers */ 1490 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0u 1491 /* Number of 16.0 dividers */ 1492 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0u 1493 /* Number of 16.5 (fractional) dividers */ 1494 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0u 1495 /* Number of 24.5 (fractional) dividers */ 1496 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0u 1497 /* Number of programmable clocks [1, 256] */ 1498 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_CLOCK_VECT 0u 1499 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1500 #define PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_PCLK_DIV_PRESENT 0u 1501 /* Number of 8.0 dividers */ 1502 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0u 1503 /* Number of 16.0 dividers */ 1504 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0u 1505 /* Number of 16.5 (fractional) dividers */ 1506 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0u 1507 /* Number of 24.5 (fractional) dividers */ 1508 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0u 1509 /* Number of programmable clocks [1, 256] */ 1510 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_CLOCK_VECT 0u 1511 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1512 #define PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_PCLK_DIV_PRESENT 0u 1513 /* Number of 8.0 dividers */ 1514 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0u 1515 /* Number of 16.0 dividers */ 1516 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0u 1517 /* Number of 16.5 (fractional) dividers */ 1518 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0u 1519 /* Number of 24.5 (fractional) dividers */ 1520 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0u 1521 /* Number of programmable clocks [1, 256] */ 1522 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_CLOCK_VECT 0u 1523 /* If Direct Clocks PCLK DIVIDER would be zero, other wise 1 */ 1524 #define PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_PCLK_DIV_PRESENT 0u 1525 /* Number of protection contexts supported. Legal range [3, 4, 6, 8] (CDT-336698) */ 1526 #define PERI_PPC_PC_NR 4u 1527 /* Security extension present ('0': no, '1': yes) */ 1528 #define PERI_PPC_SECEXT 0u 1529 /* Security Aware */ 1530 #define PERI_PPC_PPC_NR0_SECURITY_AWARE 0u 1531 /* Security Aware */ 1532 #define PERI_PPC_PPC_NR1_SECURITY_AWARE 0u 1533 /* Security Aware */ 1534 #define PERI_PPC_PPC_NR2_SECURITY_AWARE 0u 1535 /* Security Aware */ 1536 #define PERI_PPC_PPC_NR3_SECURITY_AWARE 0u 1537 /* Security Aware */ 1538 #define PERI_PPC_PPC_NR4_SECURITY_AWARE 0u 1539 /* Security Aware */ 1540 #define PERI_PPC_PPC_NR5_SECURITY_AWARE 0u 1541 /* Security Aware */ 1542 #define PERI_PPC_PPC_NR6_SECURITY_AWARE 0u 1543 /* Security Aware */ 1544 #define PERI_PPC_PPC_NR7_SECURITY_AWARE 0u 1545 /* Security Aware */ 1546 #define PERI_PPC_PPC_NR8_SECURITY_AWARE 0u 1547 /* Security Aware */ 1548 #define PERI_PPC_PPC_NR9_SECURITY_AWARE 0u 1549 /* Security Aware */ 1550 #define PERI_PPC_PPC_NR10_SECURITY_AWARE 0u 1551 /* Security Aware */ 1552 #define PERI_PPC_PPC_NR11_SECURITY_AWARE 0u 1553 /* Security Aware */ 1554 #define PERI_PPC_PPC_NR12_SECURITY_AWARE 0u 1555 /* Security Aware */ 1556 #define PERI_PPC_PPC_NR13_SECURITY_AWARE 0u 1557 /* Security Aware */ 1558 #define PERI_PPC_PPC_NR14_SECURITY_AWARE 0u 1559 /* Security Aware */ 1560 #define PERI_PPC_PPC_NR15_SECURITY_AWARE 0u 1561 /* Security Aware */ 1562 #define PERI_PPC_PPC_NR16_SECURITY_AWARE 0u 1563 /* Security Aware */ 1564 #define PERI_PPC_PPC_NR17_SECURITY_AWARE 0u 1565 /* Security Aware */ 1566 #define PERI_PPC_PPC_NR18_SECURITY_AWARE 0u 1567 /* Security Aware */ 1568 #define PERI_PPC_PPC_NR19_SECURITY_AWARE 0u 1569 /* Security Aware */ 1570 #define PERI_PPC_PPC_NR20_SECURITY_AWARE 0u 1571 /* Security Aware */ 1572 #define PERI_PPC_PPC_NR21_SECURITY_AWARE 0u 1573 /* Security Aware */ 1574 #define PERI_PPC_PPC_NR22_SECURITY_AWARE 0u 1575 /* Security Aware */ 1576 #define PERI_PPC_PPC_NR23_SECURITY_AWARE 0u 1577 /* Security Aware */ 1578 #define PERI_PPC_PPC_NR24_SECURITY_AWARE 0u 1579 /* Security Aware */ 1580 #define PERI_PPC_PPC_NR25_SECURITY_AWARE 0u 1581 /* Security Aware */ 1582 #define PERI_PPC_PPC_NR26_SECURITY_AWARE 0u 1583 /* Security Aware */ 1584 #define PERI_PPC_PPC_NR27_SECURITY_AWARE 0u 1585 /* Security Aware */ 1586 #define PERI_PPC_PPC_NR28_SECURITY_AWARE 0u 1587 /* Security Aware */ 1588 #define PERI_PPC_PPC_NR29_SECURITY_AWARE 0u 1589 /* Security Aware */ 1590 #define PERI_PPC_PPC_NR30_SECURITY_AWARE 0u 1591 /* Security Aware */ 1592 #define PERI_PPC_PPC_NR31_SECURITY_AWARE 0u 1593 /* Security Aware */ 1594 #define PERI_PPC_PPC_NR32_SECURITY_AWARE 0u 1595 /* Security Aware */ 1596 #define PERI_PPC_PPC_NR33_SECURITY_AWARE 0u 1597 /* Security Aware */ 1598 #define PERI_PPC_PPC_NR34_SECURITY_AWARE 0u 1599 /* Security Aware */ 1600 #define PERI_PPC_PPC_NR35_SECURITY_AWARE 0u 1601 /* Security Aware */ 1602 #define PERI_PPC_PPC_NR36_SECURITY_AWARE 0u 1603 /* Security Aware */ 1604 #define PERI_PPC_PPC_NR37_SECURITY_AWARE 0u 1605 /* Security Aware */ 1606 #define PERI_PPC_PPC_NR38_SECURITY_AWARE 0u 1607 /* Security Aware */ 1608 #define PERI_PPC_PPC_NR39_SECURITY_AWARE 0u 1609 /* Security Aware */ 1610 #define PERI_PPC_PPC_NR40_SECURITY_AWARE 0u 1611 /* Security Aware */ 1612 #define PERI_PPC_PPC_NR41_SECURITY_AWARE 0u 1613 /* Security Aware */ 1614 #define PERI_PPC_PPC_NR42_SECURITY_AWARE 0u 1615 /* Security Aware */ 1616 #define PERI_PPC_PPC_NR43_SECURITY_AWARE 0u 1617 /* Security Aware */ 1618 #define PERI_PPC_PPC_NR44_SECURITY_AWARE 0u 1619 /* Security Aware */ 1620 #define PERI_PPC_PPC_NR45_SECURITY_AWARE 0u 1621 /* Security Aware */ 1622 #define PERI_PPC_PPC_NR46_SECURITY_AWARE 0u 1623 /* Security Aware */ 1624 #define PERI_PPC_PPC_NR47_SECURITY_AWARE 0u 1625 /* Security Aware */ 1626 #define PERI_PPC_PPC_NR48_SECURITY_AWARE 0u 1627 /* Security Aware */ 1628 #define PERI_PPC_PPC_NR49_SECURITY_AWARE 0u 1629 /* Security Aware */ 1630 #define PERI_PPC_PPC_NR50_SECURITY_AWARE 0u 1631 /* Security Aware */ 1632 #define PERI_PPC_PPC_NR51_SECURITY_AWARE 0u 1633 /* Security Aware */ 1634 #define PERI_PPC_PPC_NR52_SECURITY_AWARE 0u 1635 /* Security Aware */ 1636 #define PERI_PPC_PPC_NR53_SECURITY_AWARE 0u 1637 /* Security Aware */ 1638 #define PERI_PPC_PPC_NR54_SECURITY_AWARE 0u 1639 /* Security Aware */ 1640 #define PERI_PPC_PPC_NR55_SECURITY_AWARE 0u 1641 /* Security Aware */ 1642 #define PERI_PPC_PPC_NR56_SECURITY_AWARE 0u 1643 /* Security Aware */ 1644 #define PERI_PPC_PPC_NR57_SECURITY_AWARE 0u 1645 /* Security Aware */ 1646 #define PERI_PPC_PPC_NR58_SECURITY_AWARE 0u 1647 /* Security Aware */ 1648 #define PERI_PPC_PPC_NR59_SECURITY_AWARE 0u 1649 /* Security Aware */ 1650 #define PERI_PPC_PPC_NR60_SECURITY_AWARE 0u 1651 /* Security Aware */ 1652 #define PERI_PPC_PPC_NR61_SECURITY_AWARE 0u 1653 /* Security Aware */ 1654 #define PERI_PPC_PPC_NR62_SECURITY_AWARE 0u 1655 /* Security Aware */ 1656 #define PERI_PPC_PPC_NR63_SECURITY_AWARE 0u 1657 /* Security Aware */ 1658 #define PERI_PPC_PPC_NR64_SECURITY_AWARE 0u 1659 /* Security Aware */ 1660 #define PERI_PPC_PPC_NR65_SECURITY_AWARE 1u 1661 /* Security Aware */ 1662 #define PERI_PPC_PPC_NR66_SECURITY_AWARE 1u 1663 /* Security Aware */ 1664 #define PERI_PPC_PPC_NR67_SECURITY_AWARE 1u 1665 /* Security Aware */ 1666 #define PERI_PPC_PPC_NR68_SECURITY_AWARE 1u 1667 /* Security Aware */ 1668 #define PERI_PPC_PPC_NR69_SECURITY_AWARE 1u 1669 /* Security Aware */ 1670 #define PERI_PPC_PPC_NR70_SECURITY_AWARE 1u 1671 /* Security Aware */ 1672 #define PERI_PPC_PPC_NR71_SECURITY_AWARE 0u 1673 /* Security Aware */ 1674 #define PERI_PPC_PPC_NR72_SECURITY_AWARE 0u 1675 /* Security Aware */ 1676 #define PERI_PPC_PPC_NR73_SECURITY_AWARE 0u 1677 /* Security Aware */ 1678 #define PERI_PPC_PPC_NR74_SECURITY_AWARE 0u 1679 /* Security Aware */ 1680 #define PERI_PPC_PPC_NR75_SECURITY_AWARE 0u 1681 /* Security Aware */ 1682 #define PERI_PPC_PPC_NR76_SECURITY_AWARE 0u 1683 /* Security Aware */ 1684 #define PERI_PPC_PPC_NR77_SECURITY_AWARE 0u 1685 /* Security Aware */ 1686 #define PERI_PPC_PPC_NR78_SECURITY_AWARE 0u 1687 /* Security Aware */ 1688 #define PERI_PPC_PPC_NR79_SECURITY_AWARE 0u 1689 /* Security Aware */ 1690 #define PERI_PPC_PPC_NR80_SECURITY_AWARE 0u 1691 /* Security Aware */ 1692 #define PERI_PPC_PPC_NR81_SECURITY_AWARE 0u 1693 /* Security Aware */ 1694 #define PERI_PPC_PPC_NR82_SECURITY_AWARE 0u 1695 /* Security Aware */ 1696 #define PERI_PPC_PPC_NR83_SECURITY_AWARE 0u 1697 /* Security Aware */ 1698 #define PERI_PPC_PPC_NR84_SECURITY_AWARE 0u 1699 /* Security Aware */ 1700 #define PERI_PPC_PPC_NR85_SECURITY_AWARE 1u 1701 /* Security Aware */ 1702 #define PERI_PPC_PPC_NR86_SECURITY_AWARE 1u 1703 /* Security Aware */ 1704 #define PERI_PPC_PPC_NR87_SECURITY_AWARE 1u 1705 /* Security Aware */ 1706 #define PERI_PPC_PPC_NR88_SECURITY_AWARE 1u 1707 /* Security Aware */ 1708 #define PERI_PPC_PPC_NR89_SECURITY_AWARE 1u 1709 /* Security Aware */ 1710 #define PERI_PPC_PPC_NR90_SECURITY_AWARE 1u 1711 /* Security Aware */ 1712 #define PERI_PPC_PPC_NR91_SECURITY_AWARE 1u 1713 /* Security Aware */ 1714 #define PERI_PPC_PPC_NR92_SECURITY_AWARE 1u 1715 /* Security Aware */ 1716 #define PERI_PPC_PPC_NR93_SECURITY_AWARE 1u 1717 /* Security Aware */ 1718 #define PERI_PPC_PPC_NR94_SECURITY_AWARE 1u 1719 /* Security Aware */ 1720 #define PERI_PPC_PPC_NR95_SECURITY_AWARE 1u 1721 /* Security Aware */ 1722 #define PERI_PPC_PPC_NR96_SECURITY_AWARE 1u 1723 /* Security Aware */ 1724 #define PERI_PPC_PPC_NR97_SECURITY_AWARE 1u 1725 /* Security Aware */ 1726 #define PERI_PPC_PPC_NR98_SECURITY_AWARE 1u 1727 /* Security Aware */ 1728 #define PERI_PPC_PPC_NR99_SECURITY_AWARE 1u 1729 /* Security Aware */ 1730 #define PERI_PPC_PPC_NR100_SECURITY_AWARE 1u 1731 /* Security Aware */ 1732 #define PERI_PPC_PPC_NR101_SECURITY_AWARE 1u 1733 /* Security Aware */ 1734 #define PERI_PPC_PPC_NR102_SECURITY_AWARE 1u 1735 /* Security Aware */ 1736 #define PERI_PPC_PPC_NR103_SECURITY_AWARE 1u 1737 /* Security Aware */ 1738 #define PERI_PPC_PPC_NR104_SECURITY_AWARE 1u 1739 /* Security Aware */ 1740 #define PERI_PPC_PPC_NR105_SECURITY_AWARE 1u 1741 /* Security Aware */ 1742 #define PERI_PPC_PPC_NR106_SECURITY_AWARE 1u 1743 /* Security Aware */ 1744 #define PERI_PPC_PPC_NR107_SECURITY_AWARE 0u 1745 /* Security Aware */ 1746 #define PERI_PPC_PPC_NR108_SECURITY_AWARE 0u 1747 /* Security Aware */ 1748 #define PERI_PPC_PPC_NR109_SECURITY_AWARE 0u 1749 /* Security Aware */ 1750 #define PERI_PPC_PPC_NR110_SECURITY_AWARE 0u 1751 /* Security Aware */ 1752 #define PERI_PPC_PPC_NR111_SECURITY_AWARE 0u 1753 /* Security Aware */ 1754 #define PERI_PPC_PPC_NR112_SECURITY_AWARE 0u 1755 /* Security Aware */ 1756 #define PERI_PPC_PPC_NR113_SECURITY_AWARE 0u 1757 /* Security Aware */ 1758 #define PERI_PPC_PPC_NR114_SECURITY_AWARE 0u 1759 /* Security Aware */ 1760 #define PERI_PPC_PPC_NR115_SECURITY_AWARE 0u 1761 /* Security Aware */ 1762 #define PERI_PPC_PPC_NR116_SECURITY_AWARE 0u 1763 /* Security Aware */ 1764 #define PERI_PPC_PPC_NR117_SECURITY_AWARE 0u 1765 /* Security Aware */ 1766 #define PERI_PPC_PPC_NR118_SECURITY_AWARE 0u 1767 /* Security Aware */ 1768 #define PERI_PPC_PPC_NR119_SECURITY_AWARE 0u 1769 /* Security Aware */ 1770 #define PERI_PPC_PPC_NR120_SECURITY_AWARE 0u 1771 /* Security Aware */ 1772 #define PERI_PPC_PPC_NR121_SECURITY_AWARE 0u 1773 /* Security Aware */ 1774 #define PERI_PPC_PPC_NR122_SECURITY_AWARE 0u 1775 /* Security Aware */ 1776 #define PERI_PPC_PPC_NR123_SECURITY_AWARE 0u 1777 /* Security Aware */ 1778 #define PERI_PPC_PPC_NR124_SECURITY_AWARE 0u 1779 /* Security Aware */ 1780 #define PERI_PPC_PPC_NR125_SECURITY_AWARE 0u 1781 /* Security Aware */ 1782 #define PERI_PPC_PPC_NR126_SECURITY_AWARE 0u 1783 /* Security Aware */ 1784 #define PERI_PPC_PPC_NR127_SECURITY_AWARE 0u 1785 /* Security Aware */ 1786 #define PERI_PPC_PPC_NR128_SECURITY_AWARE 0u 1787 /* Security Aware */ 1788 #define PERI_PPC_PPC_NR129_SECURITY_AWARE 0u 1789 /* Security Aware */ 1790 #define PERI_PPC_PPC_NR130_SECURITY_AWARE 0u 1791 /* Security Aware */ 1792 #define PERI_PPC_PPC_NR131_SECURITY_AWARE 0u 1793 /* Security Aware */ 1794 #define PERI_PPC_PPC_NR132_SECURITY_AWARE 0u 1795 /* Security Aware */ 1796 #define PERI_PPC_PPC_NR133_SECURITY_AWARE 0u 1797 /* Security Aware */ 1798 #define PERI_PPC_PPC_NR134_SECURITY_AWARE 0u 1799 /* Security Aware */ 1800 #define PERI_PPC_PPC_NR135_SECURITY_AWARE 0u 1801 /* Security Aware */ 1802 #define PERI_PPC_PPC_NR136_SECURITY_AWARE 0u 1803 /* Security Aware */ 1804 #define PERI_PPC_PPC_NR137_SECURITY_AWARE 0u 1805 /* Security Aware */ 1806 #define PERI_PPC_PPC_NR138_SECURITY_AWARE 0u 1807 /* Security Aware */ 1808 #define PERI_PPC_PPC_NR139_SECURITY_AWARE 0u 1809 /* Security Aware */ 1810 #define PERI_PPC_PPC_NR140_SECURITY_AWARE 0u 1811 /* Security Aware */ 1812 #define PERI_PPC_PPC_NR141_SECURITY_AWARE 0u 1813 /* Security Aware */ 1814 #define PERI_PPC_PPC_NR142_SECURITY_AWARE 0u 1815 /* Security Aware */ 1816 #define PERI_PPC_PPC_NR143_SECURITY_AWARE 0u 1817 /* Security Aware */ 1818 #define PERI_PPC_PPC_NR144_SECURITY_AWARE 0u 1819 /* Security Aware */ 1820 #define PERI_PPC_PPC_NR145_SECURITY_AWARE 0u 1821 /* Security Aware */ 1822 #define PERI_PPC_PPC_NR146_SECURITY_AWARE 0u 1823 /* Security Aware */ 1824 #define PERI_PPC_PPC_NR147_SECURITY_AWARE 0u 1825 /* Security Aware */ 1826 #define PERI_PPC_PPC_NR148_SECURITY_AWARE 0u 1827 /* Security Aware */ 1828 #define PERI_PPC_PPC_NR149_SECURITY_AWARE 0u 1829 /* Security Aware */ 1830 #define PERI_PPC_PPC_NR150_SECURITY_AWARE 0u 1831 /* Security Aware */ 1832 #define PERI_PPC_PPC_NR151_SECURITY_AWARE 0u 1833 /* Security Aware */ 1834 #define PERI_PPC_PPC_NR152_SECURITY_AWARE 0u 1835 /* Security Aware */ 1836 #define PERI_PPC_PPC_NR153_SECURITY_AWARE 0u 1837 /* Security Aware */ 1838 #define PERI_PPC_PPC_NR154_SECURITY_AWARE 0u 1839 /* Security Aware */ 1840 #define PERI_PPC_PPC_NR155_SECURITY_AWARE 0u 1841 /* Security Aware */ 1842 #define PERI_PPC_PPC_NR156_SECURITY_AWARE 0u 1843 /* Presence of the patch functionality. 0: ROM cannot be patched. 1: ROM can be 1844 patched. */ 1845 #define PROMC_PATCH_PRESENT 0u 1846 /* Number of patchable locations (patch entries). Possible range [0,512]. */ 1847 #define PROMC_PATCH_NR 64u 1848 /* Number of patchable locations, qualified by PATCH_PRESENT. Local param to mimic 1849 by product XLS. */ 1850 #define PROMC_PATCH_NR_QUAL 0u 1851 /* Patch size selection of a single structure. 0: 8 Bytes. 1: 16 Bytes. **) 2: 32 1852 Bytes. 3: 64 Bytes. **) The patch size should fit to the word size of the 1853 ROM. Thus only PATCH_SIZE=1 is supported for this ROM controller. */ 1854 #define PROMC_PATCH_SIZE 1u 1855 /* Width of compared address bits. The LSB is determined by the PATCH_SIZE, for 16 1856 bytes this equals to bit [4]. The MSB is chosen to address the full size of 1857 the ROM in bytes. */ 1858 #define PROMC_MATCH_ADDR_SIZE 12u 1859 /* Initial value of the first patchable address in the ROM. This address and the 1860 following higher addresses are patchable if the function is enabled. */ 1861 #define PROMC_SROM_BOUNDARY 303u 1862 /* Width of the byte address (2^ROMC_ADDR_WIDTH byte of total SROM region). */ 1863 #define PROMC_ROMC_ADDR_WIDTH 16u 1864 /* Number of physical SROM macros used. */ 1865 #define PROMC_ROMC_MACRO_NR 1u 1866 /* Width of the byte address per each physical macro. */ 1867 #define PROMC_ROMC_MACRO_ADDR_WIDTH 16u 1868 /* Bit width of hrdata and hwdata (AHB5 slave for ROM access). */ 1869 #define PROMC_DATA_PATH_WIDTH 128u 1870 /* Number of RAM words for patch data. Local param to mimic by product XLS. */ 1871 #define PROMC_PATCH_RAM_WORDS 0u 1872 /* VT type of instantiated tech cells through mxtk. */ 1873 #define PROMC_CELL_VT_TYPE 1u 1874 /* Bit width of mmio_trim_ram_ctl_trim. */ 1875 #define PROMC_TRIM_WIDTH 32u 1876 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 1877 8=T28HPL, 9=T28HPC */ 1878 #define PROMC_PLATFORM_VARIANT 6u 1879 /* RAM vendor (0=Cypress, 1=Synopsys, 2=ARM, 3=Broadcom,4=TSMC) */ 1880 #define PROMC_RAM_VEND 1u 1881 /* Security based access checks are valid (1: NS bit is checked, 0: NS bit is 1882 ignored). */ 1883 #define PROMC_MPC_SECEXT 0u 1884 /* Bit width of hmaster signal. */ 1885 #define PROMC_MPC_MASTER_WIDTH 6u 1886 #define PROMC_MPC_PC_WIDTH 3u 1887 /* Number of supported protection contexts. */ 1888 #define PROMC_MPC_PC_NR 4u 1889 #define PROMC_MPC_BLK_IDX_MAX 0u 1890 #define PROMC_MPC_BLK_IDX_WIDTH 0u 1891 #define PROMC_MPC_EXT_PRESENT 0u 1892 #define PROMC_MPC_BLK_IDX_MAX_TIMES_FOUR_PLUS_THREE 3u 1893 #define PROMC_MPC_BLK_IDX_WIDTH_PLUS_TWO 2u 1894 /* Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1MB) */ 1895 #define PROMC_MPC_BLOCK_SIZE 6u 1896 /* Number of AHB5 "huser[]" bits ([1, 8]). */ 1897 #define PROMC_MPC_USER_WIDTH 4u 1898 /* Number of System SRAM power partions */ 1899 #define RAMC_PWR_GROUP_NR 2u 1900 /* SRAM ECC present or not ('0': no, '1': yes) */ 1901 #define RAMC_ECC_PRESENT 0u 1902 #define RAMC_MPC_MASTER_WIDTH 6u 1903 #define RAMC_MPC_PC_WIDTH 3u 1904 #define RAMC_MPC_PC_NR 4u 1905 #define RAMC_MPC_BLK_IDX_MAX 0u 1906 #define RAMC_MPC_BLK_IDX_WIDTH 0u 1907 #define RAMC_MPC_EXT_PRESENT 0u 1908 #define RAMC_MPC_BLK_IDX_MAX_TIMES_FOUR_PLUS_THREE 3u 1909 #define RAMC_MPC_BLK_IDX_WIDTH_PLUS_TWO 2u 1910 #define RAMC_MPC_BLOCK_SIZE 7u 1911 /* DeepSleep support ('0':no, '1': yes) */ 1912 #define SCB0_DEEPSLEEP 1u 1913 /* Externally clocked support? ('0': no, '1': yes) */ 1914 #define SCB0_EC 1u 1915 /* I2C master support? ('0': no, '1': yes) */ 1916 #define SCB0_I2C_M 1u 1917 /* I2C slave support? ('0': no, '1': yes) */ 1918 #define SCB0_I2C_S 1u 1919 /* I2C support? (I2C_M | I2C_S) */ 1920 #define SCB0_I2C 1u 1921 /* I2C glitch filters present? ('0': no, '1': yes) */ 1922 #define SCB0_I2C_GLITCH 1u 1923 /* Support I2C Hs-mode (3.4Mbps) ('0': no, '1': yes) */ 1924 #define SCB0_I2C_HS 0u 1925 /* I2C externally clocked support? ('0': no, '1': yes) */ 1926 #define SCB0_I2C_EC 1u 1927 /* I2C master and slave support? (I2C_M & I2C_S) */ 1928 #define SCB0_I2C_M_S 1u 1929 /* I2C master and slave support? (I2C_M & I2C_HS) */ 1930 #define SCB0_I2C_M_HS 0u 1931 /* I2C master and slave support? (I2C_S & I2C_HS) */ 1932 #define SCB0_I2C_S_HS 0u 1933 /* I2C slave with EC? (I2C_S & I2C_EC) */ 1934 #define SCB0_I2C_S_EC 1u 1935 /* SPI master support? ('0': no, '1': yes) */ 1936 #define SCB0_SPI_M 1u 1937 /* SPI slave support? ('0': no, '1': yes) */ 1938 #define SCB0_SPI_S 1u 1939 /* SPI support? (SPI_M | SPI_S) */ 1940 #define SCB0_SPI 1u 1941 /* SPI externally clocked support? ('0': no, '1': yes) */ 1942 #define SCB0_SPI_EC 1u 1943 /* SPI slave with EC? (SPI_S & SPI_EC) */ 1944 #define SCB0_SPI_S_EC 1u 1945 /* UART support? ('0': no, '1': yes) */ 1946 #define SCB0_UART 0u 1947 /* SPI or UART (SPI | UART) */ 1948 #define SCB0_SPI_UART 1u 1949 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 1950 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 1951 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 1952 #define SCB0_EZ_DATA_NR 256u 1953 /* Command/response mode support? ('0': no, '1': yes) */ 1954 #define SCB0_CMD_RESP 1u 1955 /* EZ mode support? ('0': no, '1': yes) */ 1956 #define SCB0_EZ 1u 1957 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 1958 #define SCB0_EZ_CMD_RESP 1u 1959 /* I2C slave with EZ mode (I2C_S & EZ) */ 1960 #define SCB0_I2C_S_EZ 1u 1961 /* SPI slave with EZ mode (SPI_S & EZ) */ 1962 #define SCB0_SPI_S_EZ 1u 1963 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 1964 #define SCB0_MASTER_WIDTH 8u 1965 /* Number of used spi_select signals (max 4) */ 1966 #define SCB0_CHIP_TOP_SPI_SEL_NR 3u 1967 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 1968 #define SCB0_CHIP_TOP_I2C_FAST_PLUS 1u 1969 /* ddft_in[1:0] and ddft_out[1:0] are used (not used on M0S8 platform) */ 1970 #define SCB0_CHIP_TOP_DDFT_USED 4u 1971 /* DeepSleep support ('0':no, '1': yes) */ 1972 #define SCB1_DEEPSLEEP 0u 1973 /* Externally clocked support? ('0': no, '1': yes) */ 1974 #define SCB1_EC 0u 1975 /* I2C master support? ('0': no, '1': yes) */ 1976 #define SCB1_I2C_M 0u 1977 /* I2C slave support? ('0': no, '1': yes) */ 1978 #define SCB1_I2C_S 0u 1979 /* I2C support? (I2C_M | I2C_S) */ 1980 #define SCB1_I2C 0u 1981 /* I2C glitch filters present? ('0': no, '1': yes) */ 1982 #define SCB1_I2C_GLITCH 0u 1983 /* Support I2C Hs-mode (3.4Mbps) ('0': no, '1': yes) */ 1984 #define SCB1_I2C_HS 0u 1985 /* I2C externally clocked support? ('0': no, '1': yes) */ 1986 #define SCB1_I2C_EC 0u 1987 /* I2C master and slave support? (I2C_M & I2C_S) */ 1988 #define SCB1_I2C_M_S 0u 1989 /* I2C master and slave support? (I2C_M & I2C_HS) */ 1990 #define SCB1_I2C_M_HS 0u 1991 /* I2C master and slave support? (I2C_S & I2C_HS) */ 1992 #define SCB1_I2C_S_HS 0u 1993 /* I2C slave with EC? (I2C_S & I2C_EC) */ 1994 #define SCB1_I2C_S_EC 0u 1995 /* SPI master support? ('0': no, '1': yes) */ 1996 #define SCB1_SPI_M 1u 1997 /* SPI slave support? ('0': no, '1': yes) */ 1998 #define SCB1_SPI_S 1u 1999 /* SPI support? (SPI_M | SPI_S) */ 2000 #define SCB1_SPI 1u 2001 /* SPI externally clocked support? ('0': no, '1': yes) */ 2002 #define SCB1_SPI_EC 0u 2003 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2004 #define SCB1_SPI_S_EC 0u 2005 /* UART support? ('0': no, '1': yes) */ 2006 #define SCB1_UART 1u 2007 /* SPI or UART (SPI | UART) */ 2008 #define SCB1_SPI_UART 1u 2009 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2010 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2011 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2012 #define SCB1_EZ_DATA_NR 256u 2013 /* Command/response mode support? ('0': no, '1': yes) */ 2014 #define SCB1_CMD_RESP 0u 2015 /* EZ mode support? ('0': no, '1': yes) */ 2016 #define SCB1_EZ 0u 2017 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2018 #define SCB1_EZ_CMD_RESP 0u 2019 /* I2C slave with EZ mode (I2C_S & EZ) */ 2020 #define SCB1_I2C_S_EZ 0u 2021 /* SPI slave with EZ mode (SPI_S & EZ) */ 2022 #define SCB1_SPI_S_EZ 0u 2023 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2024 #define SCB1_MASTER_WIDTH 8u 2025 /* Number of used spi_select signals (max 4) */ 2026 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 2027 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2028 #define SCB1_CHIP_TOP_I2C_FAST_PLUS 1u 2029 /* ddft_in[1:0] and ddft_out[1:0] are used (not used on M0S8 platform) */ 2030 #define SCB1_CHIP_TOP_DDFT_USED 4u 2031 /* DeepSleep support ('0':no, '1': yes) */ 2032 #define SCB2_DEEPSLEEP 0u 2033 /* Externally clocked support? ('0': no, '1': yes) */ 2034 #define SCB2_EC 0u 2035 /* I2C master support? ('0': no, '1': yes) */ 2036 #define SCB2_I2C_M 1u 2037 /* I2C slave support? ('0': no, '1': yes) */ 2038 #define SCB2_I2C_S 1u 2039 /* I2C support? (I2C_M | I2C_S) */ 2040 #define SCB2_I2C 1u 2041 /* I2C glitch filters present? ('0': no, '1': yes) */ 2042 #define SCB2_I2C_GLITCH 1u 2043 /* Support I2C Hs-mode (3.4Mbps) ('0': no, '1': yes) */ 2044 #define SCB2_I2C_HS 0u 2045 /* I2C externally clocked support? ('0': no, '1': yes) */ 2046 #define SCB2_I2C_EC 0u 2047 /* I2C master and slave support? (I2C_M & I2C_S) */ 2048 #define SCB2_I2C_M_S 1u 2049 /* I2C master and slave support? (I2C_M & I2C_HS) */ 2050 #define SCB2_I2C_M_HS 0u 2051 /* I2C master and slave support? (I2C_S & I2C_HS) */ 2052 #define SCB2_I2C_S_HS 0u 2053 /* I2C slave with EC? (I2C_S & I2C_EC) */ 2054 #define SCB2_I2C_S_EC 0u 2055 /* SPI master support? ('0': no, '1': yes) */ 2056 #define SCB2_SPI_M 0u 2057 /* SPI slave support? ('0': no, '1': yes) */ 2058 #define SCB2_SPI_S 0u 2059 /* SPI support? (SPI_M | SPI_S) */ 2060 #define SCB2_SPI 0u 2061 /* SPI externally clocked support? ('0': no, '1': yes) */ 2062 #define SCB2_SPI_EC 0u 2063 /* SPI slave with EC? (SPI_S & SPI_EC) */ 2064 #define SCB2_SPI_S_EC 0u 2065 /* UART support? ('0': no, '1': yes) */ 2066 #define SCB2_UART 1u 2067 /* SPI or UART (SPI | UART) */ 2068 #define SCB2_SPI_UART 1u 2069 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 2070 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 2071 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 2072 #define SCB2_EZ_DATA_NR 256u 2073 /* Command/response mode support? ('0': no, '1': yes) */ 2074 #define SCB2_CMD_RESP 0u 2075 /* EZ mode support? ('0': no, '1': yes) */ 2076 #define SCB2_EZ 0u 2077 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 2078 #define SCB2_EZ_CMD_RESP 0u 2079 /* I2C slave with EZ mode (I2C_S & EZ) */ 2080 #define SCB2_I2C_S_EZ 0u 2081 /* SPI slave with EZ mode (SPI_S & EZ) */ 2082 #define SCB2_SPI_S_EZ 0u 2083 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2084 #define SCB2_MASTER_WIDTH 8u 2085 /* Number of used spi_select signals (max 4) */ 2086 #define SCB2_CHIP_TOP_SPI_SEL_NR 0u 2087 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 2088 #define SCB2_CHIP_TOP_I2C_FAST_PLUS 1u 2089 /* ddft_in[1:0] and ddft_out[1:0] are used (not used on M0S8 platform) */ 2090 #define SCB2_CHIP_TOP_DDFT_USED 4u 2091 /* Slow AHB XIP cache is present ([0,1]). If SLOW_AHB_XIP_IF_PRESENT=0 then set 2092 this to 0 as well. */ 2093 #define SMIF_SLOW_CACHE_PRESENT 0u 2094 /* Fast AHB XIP cache is present ([0,1]). If FAST_AHB_XIP_IF_PRESENT=0 then set 2095 this to 0 as well. */ 2096 #define SMIF_FAST_CACHE_PRESENT 0u 2097 /* Number of Protection Contexts [1..8] for MPC; only valid when SLOW or 2098 FAST_AHB_XIP_IF_IS_AHB5 */ 2099 #define SMIF_PC_NR 4u 2100 /* Granularity of the MPC block size; 0: 32B, 1: 64B, ... 15: 1MB; only valid when 2101 SLOW or FAST_AHB_XIP_IF_IS_AHB5 */ 2102 #define SMIF_BLOCK_SIZE 12u 2103 /* Base address of the SMIF XIP memory region. This address must be a multiple of 2104 the SMIF XIP memory capacity. This address must be a multiple of the SMIF XIP 2105 memory region capacity (see SMIP_XIP_MASK below). The SMIF XIP memory region 2106 should NOT overlap with other memory regions. This adress must be in the 2107 [0x0000:0000, 0xffff:0000] memory region. However, for MXS40 CM4 based 2108 platform variant, this address must be in the [0x0000:0000, 0x1fff:0000] 2109 memory region (to ensure a connection to the ARM CM4 CPU ICode/DCode memory 2110 region [0x0000:0000, 0x1fff:ffff]). The external memory devices are located 2111 within the SMIF XIP memory region. */ 2112 #define SMIF_SMIF_XIP_ADDR 1610612736u 2113 /* Capacity of the SMIF XIP memory region. The capacity must be a power of 2 and 2114 greater or equal than 64 KB). The more significant bits of this parameter are 2115 '1' and the lesser significant bits of this parameter are '0'. E.g., 2116 0xfff0:0000 specifies a 1 MB memory region. Legal values are {0xffff:0000, 2117 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 0xffe0:0000, ..., 2118 0x8000:0000, 0x0000:0000}. */ 2119 #define SMIF_SMIF_XIP_MASK 4160749568u 2120 /* Cryptography (AES) support. This is a 1-bit parameter: '0' = no support, '1' = 2121 support. */ 2122 #define SMIF_CRYPTO 1u 2123 /* Number of cryptography keys [0,1,2,4,8]; set to 0 if CRYPTO=0 */ 2124 #define SMIF_CRYPTO_KEY_NR 1u 2125 /* Hardcoded 8-bit parameter (do NOT override) that allows crypto key 0 to take on 2126 additional registers to support MMIO encryption */ 2127 #define SMIF_CRYPTO_KEY_MMIO_CAPABLE 1u 2128 /* Bus CRC support is present ([0,1]) Note: In MXS40 SMIF version 2 this option is 2129 currently not available (BUS_CRC_PRESENT=0). Based on project schedules this 2130 feature may be added already to MXS40 SMIF version 2 or to a later SMIF 2131 version. */ 2132 #define SMIF_BUS_CRC_PRESENT 0u 2133 /* Number of external memory devices supported. This parameter is in the range 2134 [1,4]. */ 2135 #define SMIF_DEVICE_NR 2u 2136 /* External memory devices write support. This is a 4-bit field. Each external 2137 memory device has a dedicated bit. E.g., if bit 2 is '1', external device 2 2138 has write support. */ 2139 #define SMIF_DEVICE_WR_EN 3u 2140 /* Number of delay lines ([1..8]). */ 2141 #define SMIF_DELAY_LINES_NR 4u 2142 /* Number of delay taps in clock delay line. */ 2143 #define SMIF_DELAY_TAPS_NR 32u 2144 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2145 #define SMIF_MASTER_WIDTH 6u 2146 /* AXI ID width. Legal range [11,16] */ 2147 #define SMIF_AXIS_ID_WIDTH 16u 2148 /* MPC SECEXT Present */ 2149 #define SMIF_MPC_SECEXT 0u 2150 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 2151 pins) */ 2152 #define SMIF_CHIP_TOP_DATA8_PRESENT 0u 2153 /* Number of used spi_select signals (max 4) */ 2154 #define SMIF_CHIP_TOP_SPI_SEL_NR 2u 2155 /* S40S variant. Must be 1 when targeting S40S and 0 otherwise. */ 2156 #define SRSS_S40S_VARIANT 1u 2157 /* S40E variant. Must be 1 when targeting S40E and 0 otherwise. */ 2158 #define SRSS_S40E_VARIANT 0u 2159 /* Number of regulator modules instantiated within SRSS. Must be > 0. */ 2160 #define SRSS_NUM_ACTREG_PWRMOD 0u 2161 /* Number of shorting switches between vccd and vccact. Must be > 0. */ 2162 #define SRSS_NUM_ACTIVE_SWITCH 2u 2163 /* S40S variant. Number of shorting switches between vccd and vccdplsp for S40S 2164 REGSETB. Must be > 0. Has no affect when S40S_REGSETB_PRESENT=0 */ 2165 #define SRSS_NUM_DPSLP_SWITCH 6u 2166 /* S40S Regulator Set A system is present */ 2167 #define SRSS_S40S_REGSETA_PRESENT 0u 2168 /* S40E Regulator Set A system is present */ 2169 #define SRSS_S40E_REGSETA_PRESENT 0u 2170 /* SIMO buck core regulator is present. Only compatible with S40S linear regulator 2171 system (S40S_LINREG_PRESENT==1). */ 2172 #define SRSS_S40S_SIMOBUCK_PRESENT 0u 2173 /* Precision ILO (PILO) is present */ 2174 #define SRSS_S40S_PILO_PRESENT 1u 2175 /* External Crystal Oscillator is present (high frequency) */ 2176 #define SRSS_ECO_PRESENT 0u 2177 /* Number of clock paths. Must be > 0 */ 2178 #define SRSS_NUM_CLKPATH 4u 2179 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 2180 #define SRSS_NUM_PLL200M 0u 2181 /* Number of HFCLK roots present. Must be > 0 */ 2182 #define SRSS_NUM_HFROOT 4u 2183 /* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ 2184 #define SRSS_NUM_HIBDATA 1u 2185 /* Backup domain is present (includes RTC and WCO) */ 2186 #define SRSS_BACKUP_PRESENT 1u 2187 /* CSV present. User must add one NUM_CLKPATH and one NUM_HFROOT to monitor ILO0 2188 with CSV_HF_REF clock. */ 2189 #define SRSS_CSV_PRESENT 0u 2190 /* Number of software watchdog timers. */ 2191 #define SRSS_NUM_MCWDT 1u 2192 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 2193 #define SRSS_NUM_DSI 0u 2194 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 2195 #define SRSS_ALTHF_PRESENT 1u 2196 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 2197 #define SRSS_ALTLF_PRESENT 0u 2198 /* Use the hardened clkactfllmux block */ 2199 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 2200 /* Number of clock paths, including direct paths in hardened clkactfllmux block 2201 (Must be >= NUM_CLKPATH) */ 2202 #define SRSS_HARD_CLKPATH 8u 2203 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= 2204 NUM_PLL+1) */ 2205 #define SRSS_HARD_CLKPATHMUX 8u 2206 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ 2207 #define SRSS_HARD_HFROOT 8u 2208 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ 2209 #define SRSS_HARD_ECOMUX_PRESENT 1u 2210 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ 2211 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 2212 /* POR present. */ 2213 #define SRSS_POR_PRESENT 0u 2214 /* Low-current buck regulator present. Can be derived from 2215 S40S_SISOBUCKLC_PRESENT, S40S_SISOBUCKMC_PRESENT or S40S_SIMOBUCK_PRESENT. */ 2216 #define SRSS_BUCKCTL_PRESENT 0u 2217 /* Low-current SISO buck core regulator is present. Only compatible with S40S 2218 linear regulator system (S40S_LINREG_PRESENT==1). */ 2219 #define SRSS_S40S_SISOBUCKLC_PRESENT 0u 2220 /* S40E linear regulator system is present */ 2221 #define SRSS_S40E_REGHC_PRESENT 0u 2222 /* LPECO mux is present in hardened clkactfllmux block */ 2223 #define SRSS_HARD_LPECOMUX_PRESENT 1u 2224 /* Number of 400MHz PLLs present. */ 2225 #define SRSS_NUM_PLL400M 0u 2226 /* Mask of DIRECT_MUX defaults. For each clock root i, if bit[i] is low the 2227 DIRECT_MUX defaults to IMO. If bit[0] is high, the DIRECT_MUX selects the 2228 output of ROOT_MUX. For backward compatibility, M33-only systems can have all 2229 mask bits high. In all cases, must have bit[0]==1 to start the chip. */ 2230 #define SRSS_MASK_DIRECTMUX_DEF 65535u 2231 /* Mask of which HFCLK roots are enabled when the debugger requests power up 2232 (CDBGPWRUPREQ). For each clock root i, SRSS enables the clock in response to 2233 CDBGPWRUPREQ, if bit[i] of mask is high. SRSS automatically enables clk_hf0, 2234 regardless of setting of mask bit0. */ 2235 #define SRSS_MASK_DEBUG_CLK 1u 2236 /* Total number of PLLs present. */ 2237 #define SRSS_NUM_TOTAL_PLL 0u 2238 /* PMIC control of vccd is present (without REGHC). */ 2239 #define SRSS_S40E_PMIC_PRESENT 0u 2240 /* Number of multi-counter watchdog timers (type B). Software incompatibility with 2241 type A. */ 2242 #define SRSS_NUM_MCWDT_B 0u 2243 /* WDT type A is present (backward compatible version) */ 2244 #define SRSS_WDT_A_PRESENT 1u 2245 /* WDT type B is present. Software incompatibility with type A. */ 2246 #define SRSS_WDT_B_PRESENT 0u 2247 /* Medium-current SISO buck core regulator is present. Only compatible with S40S 2248 linear regulator system (S40S_LINREG_PRESENT==1). */ 2249 #define SRSS_S40S_SISOBUCKMC_PRESENT 0u 2250 /* Mask for whether a PD is present in the PDCM. The zeroth bit is the PD 2251 controlled by the main PPU and must always be set. */ 2252 #define SRSS_PDCM_PD_PRESENT 15u 2253 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2254 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2255 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2256 on. For configurable sense bits, this indicates the reset value of the 2257 configuration register. */ 2258 #define SRSS_PDCM_PD_PRESENT0_PDCM_PD_DEFAULT_ON 6u 2259 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2260 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2261 PD<k/16> can be configured on when PD<k%16> is on. */ 2262 #define SRSS_PDCM_PD_PRESENT0_PDCM_PD_CONFIG_ON 9u 2263 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2264 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2265 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2266 on. For configurable sense bits, this indicates the reset value of the 2267 configuration register. */ 2268 #define SRSS_PDCM_PD_PRESENT1_PDCM_PD_DEFAULT_ON 0u 2269 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2270 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2271 PD<k/16> can be configured on when PD<k%16> is on. */ 2272 #define SRSS_PDCM_PD_PRESENT1_PDCM_PD_CONFIG_ON 10u 2273 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2274 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2275 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2276 on. For configurable sense bits, this indicates the reset value of the 2277 configuration register. */ 2278 #define SRSS_PDCM_PD_PRESENT2_PDCM_PD_DEFAULT_ON 2u 2279 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2280 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2281 PD<k/16> can be configured on when PD<k%16> is on. */ 2282 #define SRSS_PDCM_PD_PRESENT2_PDCM_PD_CONFIG_ON 14u 2283 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2284 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2285 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2286 on. For configurable sense bits, this indicates the reset value of the 2287 configuration register. */ 2288 #define SRSS_PDCM_PD_PRESENT3_PDCM_PD_DEFAULT_ON 0u 2289 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2290 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2291 PD<k/16> can be configured on when PD<k%16> is on. */ 2292 #define SRSS_PDCM_PD_PRESENT3_PDCM_PD_CONFIG_ON 10u 2293 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2294 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2295 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2296 on. For configurable sense bits, this indicates the reset value of the 2297 configuration register. */ 2298 #define SRSS_PDCM_PD_PRESENT4_PDCM_PD_DEFAULT_ON 0u 2299 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2300 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2301 PD<k/16> can be configured on when PD<k%16> is on. */ 2302 #define SRSS_PDCM_PD_PRESENT4_PDCM_PD_CONFIG_ON 0u 2303 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2304 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2305 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2306 on. For configurable sense bits, this indicates the reset value of the 2307 configuration register. */ 2308 #define SRSS_PDCM_PD_PRESENT5_PDCM_PD_DEFAULT_ON 0u 2309 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2310 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2311 PD<k/16> can be configured on when PD<k%16> is on. */ 2312 #define SRSS_PDCM_PD_PRESENT5_PDCM_PD_CONFIG_ON 0u 2313 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2314 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2315 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2316 on. For configurable sense bits, this indicates the reset value of the 2317 configuration register. */ 2318 #define SRSS_PDCM_PD_PRESENT6_PDCM_PD_DEFAULT_ON 0u 2319 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2320 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2321 PD<k/16> can be configured on when PD<k%16> is on. */ 2322 #define SRSS_PDCM_PD_PRESENT6_PDCM_PD_CONFIG_ON 0u 2323 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2324 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2325 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2326 on. For configurable sense bits, this indicates the reset value of the 2327 configuration register. */ 2328 #define SRSS_PDCM_PD_PRESENT7_PDCM_PD_DEFAULT_ON 0u 2329 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2330 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2331 PD<k/16> can be configured on when PD<k%16> is on. */ 2332 #define SRSS_PDCM_PD_PRESENT7_PDCM_PD_CONFIG_ON 0u 2333 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2334 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2335 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2336 on. For configurable sense bits, this indicates the reset value of the 2337 configuration register. */ 2338 #define SRSS_PDCM_PD_PRESENT8_PDCM_PD_DEFAULT_ON 0u 2339 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2340 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2341 PD<k/16> can be configured on when PD<k%16> is on. */ 2342 #define SRSS_PDCM_PD_PRESENT8_PDCM_PD_CONFIG_ON 0u 2343 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2344 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2345 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2346 on. For configurable sense bits, this indicates the reset value of the 2347 configuration register. */ 2348 #define SRSS_PDCM_PD_PRESENT9_PDCM_PD_DEFAULT_ON 0u 2349 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2350 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2351 PD<k/16> can be configured on when PD<k%16> is on. */ 2352 #define SRSS_PDCM_PD_PRESENT9_PDCM_PD_CONFIG_ON 0u 2353 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2354 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2355 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2356 on. For configurable sense bits, this indicates the reset value of the 2357 configuration register. */ 2358 #define SRSS_PDCM_PD_PRESENT10_PDCM_PD_DEFAULT_ON 0u 2359 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2360 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2361 PD<k/16> can be configured on when PD<k%16> is on. */ 2362 #define SRSS_PDCM_PD_PRESENT10_PDCM_PD_CONFIG_ON 0u 2363 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2364 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2365 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2366 on. For configurable sense bits, this indicates the reset value of the 2367 configuration register. */ 2368 #define SRSS_PDCM_PD_PRESENT11_PDCM_PD_DEFAULT_ON 0u 2369 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2370 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2371 PD<k/16> can be configured on when PD<k%16> is on. */ 2372 #define SRSS_PDCM_PD_PRESENT11_PDCM_PD_CONFIG_ON 0u 2373 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2374 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2375 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2376 on. For configurable sense bits, this indicates the reset value of the 2377 configuration register. */ 2378 #define SRSS_PDCM_PD_PRESENT12_PDCM_PD_DEFAULT_ON 0u 2379 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2380 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2381 PD<k/16> can be configured on when PD<k%16> is on. */ 2382 #define SRSS_PDCM_PD_PRESENT12_PDCM_PD_CONFIG_ON 0u 2383 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2384 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2385 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2386 on. For configurable sense bits, this indicates the reset value of the 2387 configuration register. */ 2388 #define SRSS_PDCM_PD_PRESENT13_PDCM_PD_DEFAULT_ON 0u 2389 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2390 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2391 PD<k/16> can be configured on when PD<k%16> is on. */ 2392 #define SRSS_PDCM_PD_PRESENT13_PDCM_PD_CONFIG_ON 0u 2393 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2394 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2395 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2396 on. For configurable sense bits, this indicates the reset value of the 2397 configuration register. */ 2398 #define SRSS_PDCM_PD_PRESENT14_PDCM_PD_DEFAULT_ON 0u 2399 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2400 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2401 PD<k/16> can be configured on when PD<k%16> is on. */ 2402 #define SRSS_PDCM_PD_PRESENT14_PDCM_PD_CONFIG_ON 0u 2403 /* Mask of PDCM PD_FORCE_ON bits. Each bit k maps to 2404 PD_SPT[k/16].PD_FORCE_ON[k%16]. For a non-configurable sense bit, a high 2405 value for bit k indicates whether PD<k/16> is always kept on when PD<k%16> is 2406 on. For configurable sense bits, this indicates the reset value of the 2407 configuration register. */ 2408 #define SRSS_PDCM_PD_PRESENT15_PDCM_PD_DEFAULT_ON 0u 2409 /* Mask of PDCM PD_CONFIG_ON bits. Each bit k maps to 2410 PD_SPT[k/16].PD_CONFIG_ON[k%16]. A high value for bit k indicates whether 2411 PD<k/16> can be configured on when PD<k%16> is on. */ 2412 #define SRSS_PDCM_PD_PRESENT15_PDCM_PD_CONFIG_ON 0u 2413 /* FLL present */ 2414 #define SRSS_FLL_PRESENT 1u 2415 /* S40S Regulator Set B system is present */ 2416 #define SRSS_S40S_REGSETB_PRESENT 1u 2417 /* S40S Regulator Set B Nwell regulator is present */ 2418 #define SRSS_S40S_REGSETB_NW_PRESENT 0u 2419 /* Number of additional HIBERNATE wakeup sources */ 2420 #define SRSS_NUM_HIB_WAKE 4u 2421 /* CSV_BAK is present. Monitors clk_bak_hv using clk_ilo0_hv. */ 2422 #define SRSS_CSV_BAK_PRESENT 0u 2423 /* HVLDO0 present */ 2424 #define SRSS_S40S_REGSETB_HVLDO0_PRESENT 1u 2425 /* Width of the WDT (Type A) counter. For backward compatibility, the minimum 2426 allowed is 16b. */ 2427 #define SRSS_NUM_WDT_A_BITS 22u 2428 /* Separate power supply Vbackup is present (only used when BACKUP_PRESENT==1) */ 2429 #define SRSS_BACKUP_VBCK_PRESENT 0u 2430 /* Alarm1 present in RTC */ 2431 #define SRSS_BACKUP_ALM1_PRESENT 1u 2432 /* Alarm2 present in RTC */ 2433 #define SRSS_BACKUP_ALM2_PRESENT 1u 2434 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 2435 #define SRSS_BACKUP_BMEM_PRESENT 0u 2436 /* Number of Backup registers to include (each is 32b). Only used when 2437 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2438 #define SRSS_BACKUP_NUM_BREG0 4u 2439 /* Number of Backup registers to include (each is 32b). Only used when 2440 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2441 #define SRSS_BACKUP_NUM_BREG1 4u 2442 /* Number of Backup registers to include (each is 32b). Only used when 2443 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2444 #define SRSS_BACKUP_NUM_BREG2 8u 2445 /* Number of Backup registers to include (each is 32b). Only used when 2446 BACKUP_PRESENT==1. Approximate size is 850squm per register. */ 2447 #define SRSS_BACKUP_NUM_BREG3 0u 2448 /* Low power external crystal oscillator (LPECO) is present. */ 2449 #define SRSS_BACKUP_S40E_LPECO_PRESENT 0u 2450 /* CSV_BAK is present. Monitors clk_bak_hv using clk_ilo0_hv. */ 2451 #define SRSS_BACKUP_CSV_BAK_PRESENT 0u 2452 /* S40S variant. Must be 1 when targeting S40S and 0 otherwise. */ 2453 #define SRSS_CLK_TRIM_PLL400M_S40S_VARIANT 1u 2454 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 2455 mask indicates presence of a CSV. */ 2456 #define SRSS_CSV_HF_MASK_HFCSV 0u 2457 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 2458 #define TCPWM_MASTER_WIDTH 8u 2459 /* Number of input triggers per counter only routed to one counter (0..8) */ 2460 #define TCPWM_TR_ONE_CNT_NR 1u 2461 /* Number of input triggers routed to all counters (0..254), 2462 NR_TR_ONE_CNT+NR_TR_ALL CNT <= 254 */ 2463 #define TCPWM_TR_ALL_CNT_NR 28u 2464 /* Number of TCPWM counter groups (1..4) */ 2465 #define TCPWM_GRP_NR 2u 2466 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 2467 #define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 32u 2468 /* Second Capture / Compare Unit is present (0, 1) */ 2469 #define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 0u 2470 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 2471 GRP_CC1_PRESENT = 1 */ 2472 #define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u 2473 /* Stepper Motor Control features are present (0, 1). */ 2474 #define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u 2475 /* Number of counters per TCPWM group (1..256) */ 2476 #define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 2u 2477 /* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ 2478 #define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u 2479 /* Second Capture / Compare Unit is present (0, 1) */ 2480 #define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u 2481 /* Advanced Motor Control features are present (0, 1). Should only be 1 when 2482 GRP_CC1_PRESENT = 1 */ 2483 #define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u 2484 /* Stepper Motor Control features are present (0, 1). */ 2485 #define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 0u 2486 /* Number of counters per TCPWM group (1..256) */ 2487 #define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 7u 2488 /* Number of AHB-Lite "hmaster[]" bits ([4, 8]). */ 2489 #define TDM_MASTER_WIDTH 8u 2490 /* Number of TDM structures ({1, 2, 3, 4}]). */ 2491 #define TDM_NR 1u 2492 /* Number of channels per TDM structure. */ 2493 #define TDM_NR_CH_NR 2u 2494 /* Number of channels per TDM structure. */ 2495 #define TDM_NR_TDM_RX_STRUCT_CH_NR 2u 2496 /* Number of channels per TDM structure. */ 2497 #define TDM_NR_TDM_TX_STRUCT_CH_NR 2u 2498 /* Spare Enable 0=no spare, 1=max, 2=min */ 2499 #define TDM_SPARE_EN 1u 2500 /* 0=ULL65, 1=MXS40-ULP, 2=MXS40E, 3=M0S8, 4=MXS40-HD, 5=F45, 6=MXS40v2, 7=T28HPM, 2501 8=T28HPL, 9=T28HPC */ 2502 #define TDM_PLATFORM_VARIANT 6u 2503 /* SRAM vendor ({0=Cypress, 1=Synopsys, 2=ARM, 3=BRCM}) */ 2504 #define TDM_RAM_VEND 1u 2505 /* Use mxsramwrap IP */ 2506 #define TDM_MXSRAMWRAP_EN 1u 2507 /* Number of connected clocks at the IP's top level ([1, 4]). */ 2508 #define TDM_CHIP_TOP_CLK_NR 1u 2509 /* Replay functionality for transmitter. This functionality adds significant 2510 silicon area. */ 2511 #define TDM_TDM_TX_STRUCT_REPLAY_PRESENT 0u 2512 2513 /* MMIO Targets Defines */ 2514 #define CY_MMIO_SRSS_GROUP_NR 0u 2515 #define CY_MMIO_SRSS_SLAVE_NR 4u 2516 #define CY_MMIO_PWRMODE_GROUP_NR 0u 2517 #define CY_MMIO_PWRMODE_SLAVE_NR 5u 2518 #define CY_MMIO_BACKUP_GROUP_NR 0u 2519 #define CY_MMIO_BACKUP_SLAVE_NR 6u 2520 #define CY_MMIO_CRYPTO_GROUP_NR 0u 2521 #define CY_MMIO_CRYPTO_SLAVE_NR 7u 2522 #define CY_MMIO_HSIOM_GROUP_NR 1u 2523 #define CY_MMIO_HSIOM_SLAVE_NR 0u 2524 #define CY_MMIO_GPIO_GROUP_NR 1u 2525 #define CY_MMIO_GPIO_SLAVE_NR 1u 2526 #define CY_MMIO_SMARTIO_GROUP_NR 1u 2527 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 2528 #define CY_MMIO_LIN0_GROUP_NR 1u 2529 #define CY_MMIO_LIN0_SLAVE_NR 3u 2530 #define CY_MMIO_CANFD0_GROUP_NR 1u 2531 #define CY_MMIO_CANFD0_SLAVE_NR 4u 2532 #define CY_MMIO_TCPWM0_GROUP_NR 1u 2533 #define CY_MMIO_TCPWM0_SLAVE_NR 5u 2534 #define CY_MMIO_MXS40ADCMIC0_GROUP_NR 1u 2535 #define CY_MMIO_MXS40ADCMIC0_SLAVE_NR 6u 2536 #define CY_MMIO_SCB0_GROUP_NR 1u 2537 #define CY_MMIO_SCB0_SLAVE_NR 7u 2538 #define CY_MMIO_SCB01_GROUP_NR 1u 2539 #define CY_MMIO_SCB01_SLAVE_NR 8u 2540 #define CY_MMIO_SCB02_GROUP_NR 1u 2541 #define CY_MMIO_SCB02_SLAVE_NR 9u 2542 #define CY_MMIO_DFT_GROUP_NR 2u 2543 #define CY_MMIO_DFT_SLAVE_NR 0u 2544 #define CY_MMIO_EFUSE_GROUP_NR 2u 2545 #define CY_MMIO_EFUSE_SLAVE_NR 1u 2546 #define CY_MMIO_SMIF0_GROUP_NR 2u 2547 #define CY_MMIO_SMIF0_SLAVE_NR 2u 2548 #define CY_MMIO_TDM0_GROUP_NR 2u 2549 #define CY_MMIO_TDM0_SLAVE_NR 3u 2550 #define CY_MMIO_PDM0_GROUP_NR 2u 2551 #define CY_MMIO_PDM0_SLAVE_NR 4u 2552 #define CY_MMIO_KEYSCAN_GROUP_NR 2u 2553 #define CY_MMIO_KEYSCAN_SLAVE_NR 5u 2554 #define CY_MMIO_BTSS_GROUP_NR 3u 2555 #define CY_MMIO_BTSS_SLAVE_NR 0u 2556 2557 /* Protection regions */ 2558 typedef enum 2559 { 2560 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00004000 */ 2561 PROT_PERI_GR0_GROUP = 1, /* Address 0x40004010, size 0x00000008 */ 2562 PROT_PERI_GR1_GROUP = 2, /* Address 0x40004040, size 0x00000020 */ 2563 PROT_PERI_GR2_GROUP = 3, /* Address 0x40004080, size 0x00000020 */ 2564 PROT_PERI_GR3_GROUP = 4, /* Address 0x400040d0, size 0x00000010 */ 2565 PROT_PERI_GR0_BOOT = 5, /* Address 0x40004020, size 0x00000004 */ 2566 PROT_PERI_GR1_BOOT = 6, /* Address 0x40004060, size 0x00000004 */ 2567 PROT_PERI_GR2_BOOT = 7, /* Address 0x400040a0, size 0x00000004 */ 2568 PROT_PERI_GR3_BOOT = 8, /* Address 0x400040e0, size 0x00000004 */ 2569 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 2570 PROT_PPC_PPC_SECURE = 10, /* Address 0x40020000, size 0x00004000 */ 2571 PROT_PPC_PPC_NONSECURE = 11, /* Address 0x40024000, size 0x00004000 */ 2572 PROT_PERI_PCLK_MAIN = 12, /* Address 0x40040000, size 0x00010000 */ 2573 PROT_CPUSS = 13, /* Address 0x40100000, size 0x00010000 */ 2574 PROT_RAMC0_CM33 = 14, /* Address 0x40110000, size 0x00000010 */ 2575 PROT_RAMC0_BOOT = 15, /* Address 0x40110100, size 0x00000004 */ 2576 PROT_RAMC0_RAM_PWR = 16, /* Address 0x40110200, size 0x00000100 */ 2577 PROT_RAMC0_MPC0_PPC_MPC_MAIN = 17, /* Address 0x40114000, size 0x00000040 */ 2578 PROT_RAMC0_MPC0_PPC_MPC_PC = 18, /* Address 0x40114100, size 0x00000020 */ 2579 PROT_RAMC0_MPC0_PPC_MPC_ROT = 19, /* Address 0x40114200, size 0x00000020 */ 2580 PROT_PROMC_CM33 = 20, /* Address 0x40140000, size 0x00000004 */ 2581 PROT_PROMC_MPC0_PPC_MPC_MAIN = 21, /* Address 0x40141000, size 0x00000040 */ 2582 PROT_PROMC_MPC0_PPC_MPC_PC = 22, /* Address 0x40141100, size 0x00000020 */ 2583 PROT_PROMC_MPC0_PPC_MPC_ROT = 23, /* Address 0x40141200, size 0x00000020 */ 2584 PROT_MXCM33_CM33 = 24, /* Address 0x40160000, size 0x00000100 */ 2585 PROT_MXCM33_CM33_NS = 25, /* Address 0x40161004, size 0x00000004 */ 2586 PROT_MXCM33_BOOT = 26, /* Address 0x40162000, size 0x00000100 */ 2587 PROT_MXCM33_CM33_INT = 27, /* Address 0x40168000, size 0x00000200 */ 2588 PROT_DW0_DW = 28, /* Address 0x40180000, size 0x00000080 */ 2589 PROT_DW0_DW_CRC = 29, /* Address 0x40180100, size 0x00000080 */ 2590 PROT_DW0_CH_STRUCT0_CH = 30, /* Address 0x40188000, size 0x00000040 */ 2591 PROT_DW0_CH_STRUCT1_CH = 31, /* Address 0x40188040, size 0x00000040 */ 2592 PROT_DW0_CH_STRUCT2_CH = 32, /* Address 0x40188080, size 0x00000040 */ 2593 PROT_DW0_CH_STRUCT3_CH = 33, /* Address 0x401880c0, size 0x00000040 */ 2594 PROT_DW0_CH_STRUCT4_CH = 34, /* Address 0x40188100, size 0x00000040 */ 2595 PROT_DW0_CH_STRUCT5_CH = 35, /* Address 0x40188140, size 0x00000040 */ 2596 PROT_DW0_CH_STRUCT6_CH = 36, /* Address 0x40188180, size 0x00000040 */ 2597 PROT_DW0_CH_STRUCT7_CH = 37, /* Address 0x401881c0, size 0x00000040 */ 2598 PROT_DW0_CH_STRUCT8_CH = 38, /* Address 0x40188200, size 0x00000040 */ 2599 PROT_DW0_CH_STRUCT9_CH = 39, /* Address 0x40188240, size 0x00000040 */ 2600 PROT_DW0_CH_STRUCT10_CH = 40, /* Address 0x40188280, size 0x00000040 */ 2601 PROT_DW0_CH_STRUCT11_CH = 41, /* Address 0x401882c0, size 0x00000040 */ 2602 PROT_DW0_CH_STRUCT12_CH = 42, /* Address 0x40188300, size 0x00000040 */ 2603 PROT_DW0_CH_STRUCT13_CH = 43, /* Address 0x40188340, size 0x00000040 */ 2604 PROT_DW0_CH_STRUCT14_CH = 44, /* Address 0x40188380, size 0x00000040 */ 2605 PROT_DW0_CH_STRUCT15_CH = 45, /* Address 0x401883c0, size 0x00000040 */ 2606 PROT_CPUSS_ALL_PC = 46, /* Address 0x401c0000, size 0x00000080 */ 2607 PROT_CPUSS_DDFT = 47, /* Address 0x401c0080, size 0x00000004 */ 2608 PROT_CPUSS_CM33_NS = 48, /* Address 0x401c0120, size 0x00000004 */ 2609 PROT_CPUSS_AHB_ERR_INT = 49, /* Address 0x401c0200, size 0x00000040 */ 2610 PROT_CPUSS_AP = 50, /* Address 0x401c1000, size 0x00000004 */ 2611 PROT_CPUSS_BOOT = 51, /* Address 0x401c2000, size 0x00000200 */ 2612 PROT_MS0_MAIN = 52, /* Address 0x401c4000, size 0x00000004 */ 2613 PROT_MS4_MAIN = 53, /* Address 0x401c4040, size 0x00000004 */ 2614 PROT_MS7_MAIN = 54, /* Address 0x401c4070, size 0x00000004 */ 2615 PROT_MS9_MAIN = 55, /* Address 0x401c4090, size 0x00000004 */ 2616 PROT_MS31_MAIN = 56, /* Address 0x401c41f0, size 0x00000004 */ 2617 PROT_MS_PC0_PRIV = 57, /* Address 0x401c5000, size 0x00000004 */ 2618 PROT_MS_PC9_PRIV = 58, /* Address 0x401c5090, size 0x00000004 */ 2619 PROT_MS_PC31_PRIV = 59, /* Address 0x401c51f0, size 0x00000004 */ 2620 PROT_MS_PC0_PRIV_MIR = 60, /* Address 0x401c5004, size 0x00000004 */ 2621 PROT_MS_PC9_PRIV_MIR = 61, /* Address 0x401c5094, size 0x00000004 */ 2622 PROT_MS_PC31_PRIV_MIR = 62, /* Address 0x401c51f4, size 0x00000004 */ 2623 PROT_MSC_ACG = 63, /* Address 0x401c6000, size 0x00000040 */ 2624 PROT_CPUSS_SL_CTL_GROUP = 64, /* Address 0x401c8000, size 0x00000008 */ 2625 PROT_IPC_STRUCT0_IPC = 65, /* Address 0x401d0000, size 0x00000020 */ 2626 PROT_IPC_STRUCT1_IPC = 66, /* Address 0x401d0020, size 0x00000020 */ 2627 PROT_IPC_STRUCT2_IPC = 67, /* Address 0x401d0040, size 0x00000020 */ 2628 PROT_IPC_STRUCT3_IPC = 68, /* Address 0x401d0060, size 0x00000020 */ 2629 PROT_IPC_INTR_STRUCT0_INTR = 69, /* Address 0x401d1000, size 0x00000010 */ 2630 PROT_IPC_INTR_STRUCT1_INTR = 70, /* Address 0x401d1020, size 0x00000010 */ 2631 PROT_SRSS_GENERAL = 71, /* Address 0x40200000, size 0x00000400 */ 2632 PROT_SRSS_GENERAL2 = 72, /* Address 0x40200400, size 0x00000020 */ 2633 PROT_SRSS_HIB_DATA = 73, /* Address 0x40200800, size 0x00000100 */ 2634 PROT_SRSS_MAIN = 74, /* Address 0x40201000, size 0x00001000 */ 2635 PROT_SRSS_SECURE = 75, /* Address 0x40202000, size 0x00002000 */ 2636 PROT_SRSS_WDT = 76, /* Address 0x4020c000, size 0x00000010 */ 2637 PROT_MAIN = 77, /* Address 0x4020d000, size 0x00000040 */ 2638 PROT_PWRMODE_PWRMODE = 78, /* Address 0x40210000, size 0x00004000 */ 2639 PROT_BACKUP_BACKUP = 79, /* Address 0x40220000, size 0x00000100 */ 2640 PROT_BACKUP_B_BREG0 = 80, /* Address 0x40221000, size 0x00000010 */ 2641 PROT_BACKUP_B_BREG1 = 81, /* Address 0x40221010, size 0x00000010 */ 2642 PROT_BACKUP_B_BREG2 = 82, /* Address 0x40221020, size 0x00000020 */ 2643 PROT_BACKUP_BACKUP_SECURE = 83, /* Address 0x4022ff00, size 0x00000004 */ 2644 PROT_CRYPTO_MAIN = 84, /* Address 0x40230000, size 0x00000100 */ 2645 PROT_HSIOM_PRT0_PRT = 85, /* Address 0x40400000, size 0x00000008 */ 2646 PROT_HSIOM_PRT1_PRT = 86, /* Address 0x40400010, size 0x00000008 */ 2647 PROT_HSIOM_PRT2_PRT = 87, /* Address 0x40400020, size 0x00000008 */ 2648 PROT_HSIOM_PRT3_PRT = 88, /* Address 0x40400030, size 0x00000008 */ 2649 PROT_HSIOM_PRT4_PRT = 89, /* Address 0x40400040, size 0x00000008 */ 2650 PROT_HSIOM_PRT5_PRT = 90, /* Address 0x40400050, size 0x00000008 */ 2651 PROT_HSIOM_AMUX = 91, /* Address 0x40402000, size 0x00000004 */ 2652 PROT_HSIOM_MON = 92, /* Address 0x40402200, size 0x00000010 */ 2653 PROT_GPIO_PRT0_PRT = 93, /* Address 0x40410000, size 0x00000040 */ 2654 PROT_GPIO_PRT1_PRT = 94, /* Address 0x40410080, size 0x00000040 */ 2655 PROT_GPIO_PRT2_PRT = 95, /* Address 0x40410100, size 0x00000040 */ 2656 PROT_GPIO_PRT3_PRT = 96, /* Address 0x40410180, size 0x00000040 */ 2657 PROT_GPIO_PRT4_PRT = 97, /* Address 0x40410200, size 0x00000040 */ 2658 PROT_GPIO_PRT5_PRT = 98, /* Address 0x40410280, size 0x00000040 */ 2659 PROT_GPIO_PRT0_CFG = 99, /* Address 0x40410040, size 0x00000040 */ 2660 PROT_GPIO_PRT1_CFG = 100, /* Address 0x404100c0, size 0x00000040 */ 2661 PROT_GPIO_PRT2_CFG = 101, /* Address 0x40410140, size 0x00000040 */ 2662 PROT_GPIO_PRT3_CFG = 102, /* Address 0x404101c0, size 0x00000040 */ 2663 PROT_GPIO_PRT4_CFG = 103, /* Address 0x40410240, size 0x00000040 */ 2664 PROT_GPIO_PRT5_CFG = 104, /* Address 0x404102c0, size 0x00000040 */ 2665 PROT_GPIO_GPIO = 105, /* Address 0x40418000, size 0x00000040 */ 2666 PROT_GPIO_TEST = 106, /* Address 0x40419000, size 0x00000008 */ 2667 PROT_SMARTIO_PRT3_PRT = 107, /* Address 0x40420300, size 0x00000100 */ 2668 PROT_LIN0_MAIN = 108, /* Address 0x40430000, size 0x00000008 */ 2669 PROT_LIN0_CH0_CH = 109, /* Address 0x40438000, size 0x00000100 */ 2670 PROT_LIN0_CH1_CH = 110, /* Address 0x40438100, size 0x00000100 */ 2671 PROT_CANFD0_CH0_CH = 111, /* Address 0x40440000, size 0x00000200 */ 2672 PROT_CANFD0_MAIN = 112, /* Address 0x40441000, size 0x00000040 */ 2673 PROT_CANFD0_BUF = 113, /* Address 0x40450000, size 0x00010000 */ 2674 PROT_TCPWM0_GRP0_CNT0_CNT = 114, /* Address 0x404a0000, size 0x00000080 */ 2675 PROT_TCPWM0_GRP0_CNT1_CNT = 115, /* Address 0x404a0080, size 0x00000080 */ 2676 PROT_TCPWM0_GRP1_CNT0_CNT = 116, /* Address 0x404a8000, size 0x00000080 */ 2677 PROT_TCPWM0_GRP1_CNT1_CNT = 117, /* Address 0x404a8080, size 0x00000080 */ 2678 PROT_TCPWM0_GRP1_CNT2_CNT = 118, /* Address 0x404a8100, size 0x00000080 */ 2679 PROT_TCPWM0_GRP1_CNT3_CNT = 119, /* Address 0x404a8180, size 0x00000080 */ 2680 PROT_TCPWM0_GRP1_CNT4_CNT = 120, /* Address 0x404a8200, size 0x00000080 */ 2681 PROT_TCPWM0_GRP1_CNT5_CNT = 121, /* Address 0x404a8280, size 0x00000080 */ 2682 PROT_TCPWM0_GRP1_CNT6_CNT = 122, /* Address 0x404a8300, size 0x00000080 */ 2683 PROT_MXS40ADCMIC0_MAIN = 123, /* Address 0x40520000, size 0x00000400 */ 2684 PROT_SCB0 = 124, /* Address 0x40590000, size 0x00010000 */ 2685 PROT_SCB1 = 125, /* Address 0x405a0000, size 0x00010000 */ 2686 PROT_SCB2 = 126, /* Address 0x405b0000, size 0x00010000 */ 2687 PROT_DFT = 127, /* Address 0x40800000, size 0x00001000 */ 2688 PROT_EFUSE_CTL1 = 128, /* Address 0x40810000, size 0x00000004 */ 2689 PROT_EFUSE_CTL2 = 129, /* Address 0x40810100, size 0x00000080 */ 2690 PROT_EFUSE_CTL3 = 130, /* Address 0x40810180, size 0x00000004 */ 2691 PROT_EFUSE_DATA_BOOT1 = 131, /* Address 0x40810800, size 0x00000020 */ 2692 PROT_EFUSE_DATA_BOOT2 = 132, /* Address 0x40810820, size 0x00000010 */ 2693 PROT_EFUSE_DATA_BOOT3 = 133, /* Address 0x40810830, size 0x00000004 */ 2694 PROT_EFUSE_DATA_BLESS1 = 134, /* Address 0x40810834, size 0x00000004 */ 2695 PROT_EFUSE_DATA_BLESS2 = 135, /* Address 0x40810838, size 0x00000004 */ 2696 PROT_EFUSE_DATA_BLESS3 = 136, /* Address 0x4081083c, size 0x00000004 */ 2697 PROT_EFUSE_DATA_APP1 = 137, /* Address 0x40810840, size 0x00000010 */ 2698 PROT_EFUSE_DATA_APP2 = 138, /* Address 0x40810850, size 0x00000010 */ 2699 PROT_EFUSE_DATA_APP3 = 139, /* Address 0x40810860, size 0x00000010 */ 2700 PROT_EFUSE_DATA_ALL = 140, /* Address 0x40810870, size 0x00000010 */ 2701 PROT_SMIF0_MAIN = 141, /* Address 0x40890000, size 0x00001000 */ 2702 PROT_SMIF0_MPC0_PPC_MPC_MAIN = 142, /* Address 0x40891000, size 0x00000040 */ 2703 PROT_SMIF0_MPC0_PPC_MPC_PC = 143, /* Address 0x40891100, size 0x00000020 */ 2704 PROT_SMIF0_MPC0_PPC_MPC_ROT = 144, /* Address 0x40891200, size 0x00000020 */ 2705 PROT_TDM0_TDM_STRUCT0_TDM_TX_STRUCT_TX = 145, /* Address 0x408c8000, size 0x00000100 */ 2706 PROT_TDM0_TDM_STRUCT0_TDM_RX_STRUCT_RX = 146, /* Address 0x408c8100, size 0x00000100 */ 2707 PROT_PDM0_MAIN = 147, /* Address 0x408d0000, size 0x00000200 */ 2708 PROT_PDM0_CH0_RX = 148, /* Address 0x408d8000, size 0x00000100 */ 2709 PROT_PDM0_CH1_RX = 149, /* Address 0x408d8100, size 0x00000100 */ 2710 PROT_MXKEYSCAN_MAIN = 150, /* Address 0x40920000, size 0x00000040 */ 2711 PROT_BTSS_ROM = 151, /* Address 0x42000000, size 0x00400000 */ 2712 PROT_BTSS_SYSRAM = 152, /* Address 0x42400000, size 0x00004000 */ 2713 PROT_BTSS_DATA_RAM_IPC = 153, /* Address 0x42600000, size 0x00100000 */ 2714 PROT_BTSS_DRIVER = 154, /* Address 0x42a00000, size 0x00100000 */ 2715 PROT_BTSS_FWONLY = 155, /* Address 0x42b00000, size 0x00100000 */ 2716 PROT_BTSS_SECURE = 156 /* Address 0x42f00000, size 0x00100000 */ 2717 } cy_en_prot_region_t; 2718 2719 #endif /* _CYW20829A0_CONFIG_H_ */ 2720 2721 2722 /* [] END OF FILE */ 2723
