1 /***************************************************************************//** 2 * \file cyt2b73bae.h 3 * 4 * \brief 5 * CYT2B73BAE device header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYT2B73BAE_H_ 28 #define _CYT2B73BAE_H_ 29 30 /** 31 * \addtogroup group_device CYT2B73BAE 32 * \{ 33 */ 34 35 /** 36 * \addtogroup Configuration_of_CMSIS 37 * \{ 38 */ 39 40 /******************************************************************************* 41 * Interrupt Number Definition 42 *******************************************************************************/ 43 44 typedef enum { 45 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 46 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 47 (defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \ 48 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 49 /* ARM Cortex-M0+ Core Interrupt Numbers */ 50 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 51 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 52 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 53 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 54 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 55 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 56 #else 57 /* ARM Cortex-M4 Core Interrupt Numbers */ 58 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 59 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 60 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 61 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 62 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 63 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 64 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 65 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 66 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 67 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 68 #endif 69 /* CYT2B73BAE User Interrupt Numbers */ 70 NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ 71 NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ 72 NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ 73 NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ 74 NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ 75 NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ 76 NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ 77 NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ 78 /* CYT2B73BAE Internal SW Interrupt Numbers */ 79 Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ 80 Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ 81 Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ 82 Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ 83 Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ 84 Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ 85 Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ 86 Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ 87 unconnected_IRQn =1023 /*!< 1023 Unconnected */ 88 } IRQn_Type; 89 90 91 /* CYT2B73BAE peripheral interrupts */ 92 typedef enum { 93 cpuss_interrupts_ipc_0_IRQn = 0, /*!< 0 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ 94 cpuss_interrupts_ipc_1_IRQn = 1, /*!< 1 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ 95 cpuss_interrupts_ipc_2_IRQn = 2, /*!< 2 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ 96 cpuss_interrupts_ipc_3_IRQn = 3, /*!< 3 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ 97 cpuss_interrupts_ipc_4_IRQn = 4, /*!< 4 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ 98 cpuss_interrupts_ipc_5_IRQn = 5, /*!< 5 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ 99 cpuss_interrupts_ipc_6_IRQn = 6, /*!< 6 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ 100 cpuss_interrupts_ipc_7_IRQn = 7, /*!< 7 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ 101 cpuss_interrupts_fault_0_IRQn = 8, /*!< 8 [DeepSleep] CPUSS Fault Structure Interrupt #0 */ 102 cpuss_interrupts_fault_1_IRQn = 9, /*!< 9 [DeepSleep] CPUSS Fault Structure Interrupt #1 */ 103 cpuss_interrupts_fault_2_IRQn = 10, /*!< 10 [DeepSleep] CPUSS Fault Structure Interrupt #2 */ 104 cpuss_interrupts_fault_3_IRQn = 11, /*!< 11 [DeepSleep] CPUSS Fault Structure Interrupt #3 */ 105 srss_interrupt_backup_IRQn = 12, /*!< 12 [DeepSleep] Interrupt for BACKUP domain */ 106 srss_interrupt_mcwdt_0_IRQn = 13, /*!< 13 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 107 srss_interrupt_mcwdt_1_IRQn = 14, /*!< 14 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 108 srss_interrupt_wdt_IRQn = 15, /*!< 15 [DeepSleep] Hardware Watchdog Timer interrupt */ 109 srss_interrupt_IRQn = 16, /*!< 16 [DeepSleep] Other combined Interrupts for SRSS (LVD, CLKCAL) */ 110 scb_0_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Serial Communication Block #0 (DeepSleep capable) */ 111 evtgen_0_interrupt_dpslp_IRQn = 18, /*!< 18 [DeepSleep] Event gen Deep-sleep domain interrupt */ 112 ioss_interrupt_vdd_IRQn = 19, /*!< 19 [DeepSleep] GPIO Supply Detect Interrupt */ 113 ioss_interrupt_gpio_IRQn = 20, /*!< 20 [DeepSleep] Consolidated Interrupt for GPIO, All Ports */ 114 ioss_interrupts_gpio_0_IRQn = 21, /*!< 21 [DeepSleep] GPIO Port Interrupt #0 */ 115 ioss_interrupts_gpio_1_IRQn = 22, /*!< 22 [DeepSleep] GPIO Port Interrupt #1 */ 116 ioss_interrupts_gpio_2_IRQn = 23, /*!< 23 [DeepSleep] GPIO Port Interrupt #2 */ 117 ioss_interrupts_gpio_3_IRQn = 24, /*!< 24 [DeepSleep] GPIO Port Interrupt #3 */ 118 ioss_interrupts_gpio_4_IRQn = 25, /*!< 25 [DeepSleep] GPIO Port Interrupt #4 */ 119 ioss_interrupts_gpio_5_IRQn = 26, /*!< 26 [DeepSleep] GPIO Port Interrupt #5 */ 120 ioss_interrupts_gpio_6_IRQn = 27, /*!< 27 [DeepSleep] GPIO Port Interrupt #6 */ 121 ioss_interrupts_gpio_7_IRQn = 28, /*!< 28 [DeepSleep] GPIO Port Interrupt #7 */ 122 ioss_interrupts_gpio_8_IRQn = 29, /*!< 29 [DeepSleep] GPIO Port Interrupt #8 */ 123 ioss_interrupts_gpio_9_IRQn = 30, /*!< 30 [DeepSleep] GPIO Port Interrupt #9 */ 124 ioss_interrupts_gpio_10_IRQn = 31, /*!< 31 [DeepSleep] GPIO Port Interrupt #10 */ 125 ioss_interrupts_gpio_11_IRQn = 32, /*!< 32 [DeepSleep] GPIO Port Interrupt #11 */ 126 ioss_interrupts_gpio_12_IRQn = 33, /*!< 33 [DeepSleep] GPIO Port Interrupt #12 */ 127 ioss_interrupts_gpio_13_IRQn = 34, /*!< 34 [DeepSleep] GPIO Port Interrupt #13 */ 128 ioss_interrupts_gpio_14_IRQn = 35, /*!< 35 [DeepSleep] GPIO Port Interrupt #14 */ 129 ioss_interrupts_gpio_15_IRQn = 36, /*!< 36 [DeepSleep] GPIO Port Interrupt #15 */ 130 ioss_interrupts_gpio_16_IRQn = 37, /*!< 37 [DeepSleep] GPIO Port Interrupt #16 */ 131 ioss_interrupts_gpio_17_IRQn = 38, /*!< 38 [DeepSleep] GPIO Port Interrupt #17 */ 132 ioss_interrupts_gpio_18_IRQn = 39, /*!< 39 [DeepSleep] GPIO Port Interrupt #18 */ 133 ioss_interrupts_gpio_19_IRQn = 40, /*!< 40 [DeepSleep] GPIO Port Interrupt #19 */ 134 ioss_interrupts_gpio_20_IRQn = 41, /*!< 41 [DeepSleep] GPIO Port Interrupt #20 */ 135 ioss_interrupts_gpio_21_IRQn = 42, /*!< 42 [DeepSleep] GPIO Port Interrupt #21 */ 136 ioss_interrupts_gpio_22_IRQn = 43, /*!< 43 [DeepSleep] GPIO Port Interrupt #22 */ 137 ioss_interrupts_gpio_23_IRQn = 44, /*!< 44 [DeepSleep] GPIO Port Interrupt #23 */ 138 cpuss_interrupt_crypto_IRQn = 45, /*!< 45 [Active] CRYPTO Accelerator Interrupt */ 139 cpuss_interrupt_fm_IRQn = 46, /*!< 46 [Active] FLASH Macro Interrupt */ 140 cpuss_interrupts_cm4_fp_IRQn = 47, /*!< 47 [Active] Floating Point operation fault */ 141 cpuss_interrupts_cm0_cti_0_IRQn = 48, /*!< 48 [Active] CM0+ CTI #0 */ 142 cpuss_interrupts_cm0_cti_1_IRQn = 49, /*!< 49 [Active] CM0+ CTI #1 */ 143 cpuss_interrupts_cm4_cti_0_IRQn = 50, /*!< 50 [Active] CM4 CTI #0 */ 144 cpuss_interrupts_cm4_cti_1_IRQn = 51, /*!< 51 [Active] CM4 CTI #1 */ 145 evtgen_0_interrupt_IRQn = 52, /*!< 52 [Active] Event gen Active domain interrupt */ 146 canfd_0_interrupt0_IRQn = 53, /*!< 53 [Active] Can #0, Consolidated interrupt #0 for all three channels */ 147 canfd_0_interrupt1_IRQn = 54, /*!< 54 [Active] Can #0, Consolidated interrupt #1 for all three channels */ 148 canfd_1_interrupt0_IRQn = 55, /*!< 55 [Active] Can #1, Consolidated interrupt #0 for all three channels */ 149 canfd_1_interrupt1_IRQn = 56, /*!< 56 [Active] Can #1, Consolidated interrupt #1 for all three channels */ 150 canfd_0_interrupts0_0_IRQn = 57, /*!< 57 [Active] CAN #0, Interrupt #0, Channel #0 */ 151 canfd_0_interrupts0_1_IRQn = 58, /*!< 58 [Active] CAN #0, Interrupt #0, Channel #1 */ 152 canfd_0_interrupts0_2_IRQn = 59, /*!< 59 [Active] CAN #0, Interrupt #0, Channel #2 */ 153 canfd_0_interrupts1_0_IRQn = 60, /*!< 60 [Active] CAN #0, Interrupt #1, Channel #0 */ 154 canfd_0_interrupts1_1_IRQn = 61, /*!< 61 [Active] CAN #0, Interrupt #1, Channel #1 */ 155 canfd_0_interrupts1_2_IRQn = 62, /*!< 62 [Active] CAN #0, Interrupt #1, Channel #2 */ 156 canfd_1_interrupts0_0_IRQn = 63, /*!< 63 [Active] CAN #1, Interrupt #0, Channel #0 */ 157 canfd_1_interrupts0_1_IRQn = 64, /*!< 64 [Active] CAN #1, Interrupt #0, Channel #1 */ 158 canfd_1_interrupts0_2_IRQn = 65, /*!< 65 [Active] CAN #1, Interrupt #0, Channel #2 */ 159 canfd_1_interrupts1_0_IRQn = 66, /*!< 66 [Active] CAN #1, Interrupt #1, Channel #0 */ 160 canfd_1_interrupts1_1_IRQn = 67, /*!< 67 [Active] CAN #1, Interrupt #1, Channel #1 */ 161 canfd_1_interrupts1_2_IRQn = 68, /*!< 68 [Active] CAN #1, Interrupt #1, Channel #2 */ 162 lin_0_interrupts_0_IRQn = 69, /*!< 69 [Active] LIN Interrupt, Channel #0 */ 163 lin_0_interrupts_1_IRQn = 70, /*!< 70 [Active] LIN Interrupt, Channel #1 */ 164 lin_0_interrupts_2_IRQn = 71, /*!< 71 [Active] LIN Interrupt, Channel #2 */ 165 lin_0_interrupts_3_IRQn = 72, /*!< 72 [Active] LIN Interrupt, Channel #3 */ 166 lin_0_interrupts_4_IRQn = 73, /*!< 73 [Active] LIN Interrupt, Channel #4 */ 167 lin_0_interrupts_5_IRQn = 74, /*!< 74 [Active] LIN Interrupt, Channel #5 */ 168 lin_0_interrupts_6_IRQn = 75, /*!< 75 [Active] LIN Interrupt, Channel #6 */ 169 lin_0_interrupts_7_IRQn = 76, /*!< 76 [Active] LIN Interrupt, Channel #7 */ 170 scb_1_interrupt_IRQn = 77, /*!< 77 [Active] Serial Communication Block #1 */ 171 scb_2_interrupt_IRQn = 78, /*!< 78 [Active] Serial Communication Block #2 */ 172 scb_3_interrupt_IRQn = 79, /*!< 79 [Active] Serial Communication Block #3 */ 173 scb_4_interrupt_IRQn = 80, /*!< 80 [Active] Serial Communication Block #4 */ 174 scb_5_interrupt_IRQn = 81, /*!< 81 [Active] Serial Communication Block #5 */ 175 scb_6_interrupt_IRQn = 82, /*!< 82 [Active] Serial Communication Block #6 */ 176 scb_7_interrupt_IRQn = 83, /*!< 83 [Active] Serial Communication Block #7 */ 177 pass_0_interrupts_sar_0_IRQn = 84, /*!< 84 [Active] PASS interrupts, ADC #0, Channel #0 */ 178 pass_0_interrupts_sar_1_IRQn = 85, /*!< 85 [Active] PASS interrupts, ADC #0, Channel #1 */ 179 pass_0_interrupts_sar_2_IRQn = 86, /*!< 86 [Active] PASS interrupts, ADC #0, Channel #2 */ 180 pass_0_interrupts_sar_3_IRQn = 87, /*!< 87 [Active] PASS interrupts, ADC #0, Channel #3 */ 181 pass_0_interrupts_sar_4_IRQn = 88, /*!< 88 [Active] PASS interrupts, ADC #0, Channel #4 */ 182 pass_0_interrupts_sar_5_IRQn = 89, /*!< 89 [Active] PASS interrupts, ADC #0, Channel #5 */ 183 pass_0_interrupts_sar_6_IRQn = 90, /*!< 90 [Active] PASS interrupts, ADC #0, Channel #6 */ 184 pass_0_interrupts_sar_7_IRQn = 91, /*!< 91 [Active] PASS interrupts, ADC #0, Channel #7 */ 185 pass_0_interrupts_sar_8_IRQn = 92, /*!< 92 [Active] PASS interrupts, ADC #0, Channel #8 */ 186 pass_0_interrupts_sar_9_IRQn = 93, /*!< 93 [Active] PASS interrupts, ADC #0, Channel #9 */ 187 pass_0_interrupts_sar_10_IRQn = 94, /*!< 94 [Active] PASS interrupts, ADC #0, Channel #10 */ 188 pass_0_interrupts_sar_11_IRQn = 95, /*!< 95 [Active] PASS interrupts, ADC #0, Channel #11 */ 189 pass_0_interrupts_sar_12_IRQn = 96, /*!< 96 [Active] PASS interrupts, ADC #0, Channel #12 */ 190 pass_0_interrupts_sar_13_IRQn = 97, /*!< 97 [Active] PASS interrupts, ADC #0, Channel #13 */ 191 pass_0_interrupts_sar_14_IRQn = 98, /*!< 98 [Active] PASS interrupts, ADC #0, Channel #14 */ 192 pass_0_interrupts_sar_15_IRQn = 99, /*!< 99 [Active] PASS interrupts, ADC #0, Channel #15 */ 193 pass_0_interrupts_sar_16_IRQn = 100, /*!< 100 [Active] PASS interrupts, ADC #0, Channel #16 */ 194 pass_0_interrupts_sar_17_IRQn = 101, /*!< 101 [Active] PASS interrupts, ADC #0, Channel #17 */ 195 pass_0_interrupts_sar_18_IRQn = 102, /*!< 102 [Active] PASS interrupts, ADC #0, Channel #18 */ 196 pass_0_interrupts_sar_19_IRQn = 103, /*!< 103 [Active] PASS interrupts, ADC #0, Channel #19 */ 197 pass_0_interrupts_sar_20_IRQn = 104, /*!< 104 [Active] PASS interrupts, ADC #0, Channel #20 */ 198 pass_0_interrupts_sar_21_IRQn = 105, /*!< 105 [Active] PASS interrupts, ADC #0, Channel #21 */ 199 pass_0_interrupts_sar_22_IRQn = 106, /*!< 106 [Active] PASS interrupts, ADC #0, Channel #22 */ 200 pass_0_interrupts_sar_23_IRQn = 107, /*!< 107 [Active] PASS interrupts, ADC #0, Channel #23 */ 201 pass_0_interrupts_sar_32_IRQn = 108, /*!< 108 [Active] PASS interrupts, ADC #1, Channel #0 */ 202 pass_0_interrupts_sar_33_IRQn = 109, /*!< 109 [Active] PASS interrupts, ADC #1, Channel #1 */ 203 pass_0_interrupts_sar_34_IRQn = 110, /*!< 110 [Active] PASS interrupts, ADC #1, Channel #2 */ 204 pass_0_interrupts_sar_35_IRQn = 111, /*!< 111 [Active] PASS interrupts, ADC #1, Channel #3 */ 205 pass_0_interrupts_sar_36_IRQn = 112, /*!< 112 [Active] PASS interrupts, ADC #1, Channel #4 */ 206 pass_0_interrupts_sar_37_IRQn = 113, /*!< 113 [Active] PASS interrupts, ADC #1, Channel #5 */ 207 pass_0_interrupts_sar_38_IRQn = 114, /*!< 114 [Active] PASS interrupts, ADC #1, Channel #6 */ 208 pass_0_interrupts_sar_39_IRQn = 115, /*!< 115 [Active] PASS interrupts, ADC #1, Channel #7 */ 209 pass_0_interrupts_sar_40_IRQn = 116, /*!< 116 [Active] PASS interrupts, ADC #1, Channel #8 */ 210 pass_0_interrupts_sar_41_IRQn = 117, /*!< 117 [Active] PASS interrupts, ADC #1, Channel #9 */ 211 pass_0_interrupts_sar_42_IRQn = 118, /*!< 118 [Active] PASS interrupts, ADC #1, Channel #10 */ 212 pass_0_interrupts_sar_43_IRQn = 119, /*!< 119 [Active] PASS interrupts, ADC #1, Channel #11 */ 213 pass_0_interrupts_sar_44_IRQn = 120, /*!< 120 [Active] PASS interrupts, ADC #1, Channel #12 */ 214 pass_0_interrupts_sar_45_IRQn = 121, /*!< 121 [Active] PASS interrupts, ADC #1, Channel #13 */ 215 pass_0_interrupts_sar_46_IRQn = 122, /*!< 122 [Active] PASS interrupts, ADC #1, Channel #14 */ 216 pass_0_interrupts_sar_47_IRQn = 123, /*!< 123 [Active] PASS interrupts, ADC #1, Channel #15 */ 217 pass_0_interrupts_sar_48_IRQn = 124, /*!< 124 [Active] PASS interrupts, ADC #1, Channel #16 */ 218 pass_0_interrupts_sar_49_IRQn = 125, /*!< 125 [Active] PASS interrupts, ADC #1, Channel #17 */ 219 pass_0_interrupts_sar_50_IRQn = 126, /*!< 126 [Active] PASS interrupts, ADC #1, Channel #18 */ 220 pass_0_interrupts_sar_51_IRQn = 127, /*!< 127 [Active] PASS interrupts, ADC #1, Channel #19 */ 221 pass_0_interrupts_sar_52_IRQn = 128, /*!< 128 [Active] PASS interrupts, ADC #1, Channel #20 */ 222 pass_0_interrupts_sar_53_IRQn = 129, /*!< 129 [Active] PASS interrupts, ADC #1, Channel #21 */ 223 pass_0_interrupts_sar_54_IRQn = 130, /*!< 130 [Active] PASS interrupts, ADC #1, Channel #22 */ 224 pass_0_interrupts_sar_55_IRQn = 131, /*!< 131 [Active] PASS interrupts, ADC #1, Channel #23 */ 225 pass_0_interrupts_sar_56_IRQn = 132, /*!< 132 [Active] PASS interrupts, ADC #1, Channel #24 */ 226 pass_0_interrupts_sar_57_IRQn = 133, /*!< 133 [Active] PASS interrupts, ADC #1, Channel #25 */ 227 pass_0_interrupts_sar_58_IRQn = 134, /*!< 134 [Active] PASS interrupts, ADC #1, Channel #26 */ 228 pass_0_interrupts_sar_59_IRQn = 135, /*!< 135 [Active] PASS interrupts, ADC #1, Channel #27 */ 229 pass_0_interrupts_sar_60_IRQn = 136, /*!< 136 [Active] PASS interrupts, ADC #1, Channel #28 */ 230 pass_0_interrupts_sar_61_IRQn = 137, /*!< 137 [Active] PASS interrupts, ADC #1, Channel #29 */ 231 pass_0_interrupts_sar_62_IRQn = 138, /*!< 138 [Active] PASS interrupts, ADC #1, Channel #30 */ 232 pass_0_interrupts_sar_63_IRQn = 139, /*!< 139 [Active] PASS interrupts, ADC #1, Channel #31 */ 233 pass_0_interrupts_sar_64_IRQn = 140, /*!< 140 [Active] PASS interrupts, ADC #2, Channel #0 */ 234 pass_0_interrupts_sar_65_IRQn = 141, /*!< 141 [Active] PASS interrupts, ADC #2, Channel #1 */ 235 pass_0_interrupts_sar_66_IRQn = 142, /*!< 142 [Active] PASS interrupts, ADC #2, Channel #2 */ 236 pass_0_interrupts_sar_67_IRQn = 143, /*!< 143 [Active] PASS interrupts, ADC #2, Channel #3 */ 237 pass_0_interrupts_sar_68_IRQn = 144, /*!< 144 [Active] PASS interrupts, ADC #2, Channel #4 */ 238 pass_0_interrupts_sar_69_IRQn = 145, /*!< 145 [Active] PASS interrupts, ADC #2, Channel #5 */ 239 pass_0_interrupts_sar_70_IRQn = 146, /*!< 146 [Active] PASS interrupts, ADC #2, Channel #6 */ 240 pass_0_interrupts_sar_71_IRQn = 147, /*!< 147 [Active] PASS interrupts, ADC #2, Channel #7 */ 241 cpuss_interrupts_dmac_0_IRQn = 148, /*!< 148 [Active] CPUSS DMAC, Channel #0 */ 242 cpuss_interrupts_dmac_1_IRQn = 149, /*!< 149 [Active] CPUSS DMAC, Channel #1 */ 243 cpuss_interrupts_dmac_2_IRQn = 150, /*!< 150 [Active] CPUSS DMAC, Channel #2 */ 244 cpuss_interrupts_dmac_3_IRQn = 151, /*!< 151 [Active] CPUSS DMAC, Channel #3 */ 245 cpuss_interrupts_dw0_0_IRQn = 152, /*!< 152 [Active] CPUSS DataWire #0, Channel #0 */ 246 cpuss_interrupts_dw0_1_IRQn = 153, /*!< 153 [Active] CPUSS DataWire #0, Channel #1 */ 247 cpuss_interrupts_dw0_2_IRQn = 154, /*!< 154 [Active] CPUSS DataWire #0, Channel #2 */ 248 cpuss_interrupts_dw0_3_IRQn = 155, /*!< 155 [Active] CPUSS DataWire #0, Channel #3 */ 249 cpuss_interrupts_dw0_4_IRQn = 156, /*!< 156 [Active] CPUSS DataWire #0, Channel #4 */ 250 cpuss_interrupts_dw0_5_IRQn = 157, /*!< 157 [Active] CPUSS DataWire #0, Channel #5 */ 251 cpuss_interrupts_dw0_6_IRQn = 158, /*!< 158 [Active] CPUSS DataWire #0, Channel #6 */ 252 cpuss_interrupts_dw0_7_IRQn = 159, /*!< 159 [Active] CPUSS DataWire #0, Channel #7 */ 253 cpuss_interrupts_dw0_8_IRQn = 160, /*!< 160 [Active] CPUSS DataWire #0, Channel #8 */ 254 cpuss_interrupts_dw0_9_IRQn = 161, /*!< 161 [Active] CPUSS DataWire #0, Channel #9 */ 255 cpuss_interrupts_dw0_10_IRQn = 162, /*!< 162 [Active] CPUSS DataWire #0, Channel #10 */ 256 cpuss_interrupts_dw0_11_IRQn = 163, /*!< 163 [Active] CPUSS DataWire #0, Channel #11 */ 257 cpuss_interrupts_dw0_12_IRQn = 164, /*!< 164 [Active] CPUSS DataWire #0, Channel #12 */ 258 cpuss_interrupts_dw0_13_IRQn = 165, /*!< 165 [Active] CPUSS DataWire #0, Channel #13 */ 259 cpuss_interrupts_dw0_14_IRQn = 166, /*!< 166 [Active] CPUSS DataWire #0, Channel #14 */ 260 cpuss_interrupts_dw0_15_IRQn = 167, /*!< 167 [Active] CPUSS DataWire #0, Channel #15 */ 261 cpuss_interrupts_dw0_16_IRQn = 168, /*!< 168 [Active] CPUSS DataWire #0, Channel #16 */ 262 cpuss_interrupts_dw0_17_IRQn = 169, /*!< 169 [Active] CPUSS DataWire #0, Channel #17 */ 263 cpuss_interrupts_dw0_18_IRQn = 170, /*!< 170 [Active] CPUSS DataWire #0, Channel #18 */ 264 cpuss_interrupts_dw0_19_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #0, Channel #19 */ 265 cpuss_interrupts_dw0_20_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #0, Channel #20 */ 266 cpuss_interrupts_dw0_21_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #0, Channel #21 */ 267 cpuss_interrupts_dw0_22_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #22 */ 268 cpuss_interrupts_dw0_23_IRQn = 175, /*!< 175 [Active] CPUSS DataWire #0, Channel #23 */ 269 cpuss_interrupts_dw0_24_IRQn = 176, /*!< 176 [Active] CPUSS DataWire #0, Channel #24 */ 270 cpuss_interrupts_dw0_25_IRQn = 177, /*!< 177 [Active] CPUSS DataWire #0, Channel #25 */ 271 cpuss_interrupts_dw0_26_IRQn = 178, /*!< 178 [Active] CPUSS DataWire #0, Channel #26 */ 272 cpuss_interrupts_dw0_27_IRQn = 179, /*!< 179 [Active] CPUSS DataWire #0, Channel #27 */ 273 cpuss_interrupts_dw0_28_IRQn = 180, /*!< 180 [Active] CPUSS DataWire #0, Channel #28 */ 274 cpuss_interrupts_dw0_29_IRQn = 181, /*!< 181 [Active] CPUSS DataWire #0, Channel #29 */ 275 cpuss_interrupts_dw0_30_IRQn = 182, /*!< 182 [Active] CPUSS DataWire #0, Channel #30 */ 276 cpuss_interrupts_dw0_31_IRQn = 183, /*!< 183 [Active] CPUSS DataWire #0, Channel #31 */ 277 cpuss_interrupts_dw0_32_IRQn = 184, /*!< 184 [Active] CPUSS DataWire #0, Channel #32 */ 278 cpuss_interrupts_dw0_33_IRQn = 185, /*!< 185 [Active] CPUSS DataWire #0, Channel #33 */ 279 cpuss_interrupts_dw0_34_IRQn = 186, /*!< 186 [Active] CPUSS DataWire #0, Channel #34 */ 280 cpuss_interrupts_dw0_35_IRQn = 187, /*!< 187 [Active] CPUSS DataWire #0, Channel #35 */ 281 cpuss_interrupts_dw0_36_IRQn = 188, /*!< 188 [Active] CPUSS DataWire #0, Channel #36 */ 282 cpuss_interrupts_dw0_37_IRQn = 189, /*!< 189 [Active] CPUSS DataWire #0, Channel #37 */ 283 cpuss_interrupts_dw0_38_IRQn = 190, /*!< 190 [Active] CPUSS DataWire #0, Channel #38 */ 284 cpuss_interrupts_dw0_39_IRQn = 191, /*!< 191 [Active] CPUSS DataWire #0, Channel #39 */ 285 cpuss_interrupts_dw0_40_IRQn = 192, /*!< 192 [Active] CPUSS DataWire #0, Channel #40 */ 286 cpuss_interrupts_dw0_41_IRQn = 193, /*!< 193 [Active] CPUSS DataWire #0, Channel #41 */ 287 cpuss_interrupts_dw0_42_IRQn = 194, /*!< 194 [Active] CPUSS DataWire #0, Channel #42 */ 288 cpuss_interrupts_dw0_43_IRQn = 195, /*!< 195 [Active] CPUSS DataWire #0, Channel #43 */ 289 cpuss_interrupts_dw0_44_IRQn = 196, /*!< 196 [Active] CPUSS DataWire #0, Channel #44 */ 290 cpuss_interrupts_dw0_45_IRQn = 197, /*!< 197 [Active] CPUSS DataWire #0, Channel #45 */ 291 cpuss_interrupts_dw0_46_IRQn = 198, /*!< 198 [Active] CPUSS DataWire #0, Channel #46 */ 292 cpuss_interrupts_dw0_47_IRQn = 199, /*!< 199 [Active] CPUSS DataWire #0, Channel #47 */ 293 cpuss_interrupts_dw0_48_IRQn = 200, /*!< 200 [Active] CPUSS DataWire #0, Channel #48 */ 294 cpuss_interrupts_dw0_49_IRQn = 201, /*!< 201 [Active] CPUSS DataWire #0, Channel #49 */ 295 cpuss_interrupts_dw0_50_IRQn = 202, /*!< 202 [Active] CPUSS DataWire #0, Channel #50 */ 296 cpuss_interrupts_dw0_51_IRQn = 203, /*!< 203 [Active] CPUSS DataWire #0, Channel #51 */ 297 cpuss_interrupts_dw0_52_IRQn = 204, /*!< 204 [Active] CPUSS DataWire #0, Channel #52 */ 298 cpuss_interrupts_dw0_53_IRQn = 205, /*!< 205 [Active] CPUSS DataWire #0, Channel #53 */ 299 cpuss_interrupts_dw0_54_IRQn = 206, /*!< 206 [Active] CPUSS DataWire #0, Channel #54 */ 300 cpuss_interrupts_dw0_55_IRQn = 207, /*!< 207 [Active] CPUSS DataWire #0, Channel #55 */ 301 cpuss_interrupts_dw0_56_IRQn = 208, /*!< 208 [Active] CPUSS DataWire #0, Channel #56 */ 302 cpuss_interrupts_dw0_57_IRQn = 209, /*!< 209 [Active] CPUSS DataWire #0, Channel #57 */ 303 cpuss_interrupts_dw0_58_IRQn = 210, /*!< 210 [Active] CPUSS DataWire #0, Channel #58 */ 304 cpuss_interrupts_dw0_59_IRQn = 211, /*!< 211 [Active] CPUSS DataWire #0, Channel #59 */ 305 cpuss_interrupts_dw0_60_IRQn = 212, /*!< 212 [Active] CPUSS DataWire #0, Channel #60 */ 306 cpuss_interrupts_dw0_61_IRQn = 213, /*!< 213 [Active] CPUSS DataWire #0, Channel #61 */ 307 cpuss_interrupts_dw0_62_IRQn = 214, /*!< 214 [Active] CPUSS DataWire #0, Channel #62 */ 308 cpuss_interrupts_dw0_63_IRQn = 215, /*!< 215 [Active] CPUSS DataWire #0, Channel #63 */ 309 cpuss_interrupts_dw0_64_IRQn = 216, /*!< 216 [Active] CPUSS DataWire #0, Channel #64 */ 310 cpuss_interrupts_dw0_65_IRQn = 217, /*!< 217 [Active] CPUSS DataWire #0, Channel #65 */ 311 cpuss_interrupts_dw0_66_IRQn = 218, /*!< 218 [Active] CPUSS DataWire #0, Channel #66 */ 312 cpuss_interrupts_dw0_67_IRQn = 219, /*!< 219 [Active] CPUSS DataWire #0, Channel #67 */ 313 cpuss_interrupts_dw0_68_IRQn = 220, /*!< 220 [Active] CPUSS DataWire #0, Channel #68 */ 314 cpuss_interrupts_dw0_69_IRQn = 221, /*!< 221 [Active] CPUSS DataWire #0, Channel #69 */ 315 cpuss_interrupts_dw0_70_IRQn = 222, /*!< 222 [Active] CPUSS DataWire #0, Channel #70 */ 316 cpuss_interrupts_dw0_71_IRQn = 223, /*!< 223 [Active] CPUSS DataWire #0, Channel #71 */ 317 cpuss_interrupts_dw0_72_IRQn = 224, /*!< 224 [Active] CPUSS DataWire #0, Channel #72 */ 318 cpuss_interrupts_dw0_73_IRQn = 225, /*!< 225 [Active] CPUSS DataWire #0, Channel #73 */ 319 cpuss_interrupts_dw0_74_IRQn = 226, /*!< 226 [Active] CPUSS DataWire #0, Channel #74 */ 320 cpuss_interrupts_dw0_75_IRQn = 227, /*!< 227 [Active] CPUSS DataWire #0, Channel #75 */ 321 cpuss_interrupts_dw0_76_IRQn = 228, /*!< 228 [Active] CPUSS DataWire #0, Channel #76 */ 322 cpuss_interrupts_dw0_77_IRQn = 229, /*!< 229 [Active] CPUSS DataWire #0, Channel #77 */ 323 cpuss_interrupts_dw0_78_IRQn = 230, /*!< 230 [Active] CPUSS DataWire #0, Channel #78 */ 324 cpuss_interrupts_dw0_79_IRQn = 231, /*!< 231 [Active] CPUSS DataWire #0, Channel #79 */ 325 cpuss_interrupts_dw0_80_IRQn = 232, /*!< 232 [Active] CPUSS DataWire #0, Channel #80 */ 326 cpuss_interrupts_dw0_81_IRQn = 233, /*!< 233 [Active] CPUSS DataWire #0, Channel #81 */ 327 cpuss_interrupts_dw0_82_IRQn = 234, /*!< 234 [Active] CPUSS DataWire #0, Channel #82 */ 328 cpuss_interrupts_dw0_83_IRQn = 235, /*!< 235 [Active] CPUSS DataWire #0, Channel #83 */ 329 cpuss_interrupts_dw0_84_IRQn = 236, /*!< 236 [Active] CPUSS DataWire #0, Channel #84 */ 330 cpuss_interrupts_dw0_85_IRQn = 237, /*!< 237 [Active] CPUSS DataWire #0, Channel #85 */ 331 cpuss_interrupts_dw0_86_IRQn = 238, /*!< 238 [Active] CPUSS DataWire #0, Channel #86 */ 332 cpuss_interrupts_dw0_87_IRQn = 239, /*!< 239 [Active] CPUSS DataWire #0, Channel #87 */ 333 cpuss_interrupts_dw0_88_IRQn = 240, /*!< 240 [Active] CPUSS DataWire #0, Channel #88 */ 334 cpuss_interrupts_dw1_0_IRQn = 241, /*!< 241 [Active] CPUSS DataWire #1, Channel #0 */ 335 cpuss_interrupts_dw1_1_IRQn = 242, /*!< 242 [Active] CPUSS DataWire #1, Channel #1 */ 336 cpuss_interrupts_dw1_2_IRQn = 243, /*!< 243 [Active] CPUSS DataWire #1, Channel #2 */ 337 cpuss_interrupts_dw1_3_IRQn = 244, /*!< 244 [Active] CPUSS DataWire #1, Channel #3 */ 338 cpuss_interrupts_dw1_4_IRQn = 245, /*!< 245 [Active] CPUSS DataWire #1, Channel #4 */ 339 cpuss_interrupts_dw1_5_IRQn = 246, /*!< 246 [Active] CPUSS DataWire #1, Channel #5 */ 340 cpuss_interrupts_dw1_6_IRQn = 247, /*!< 247 [Active] CPUSS DataWire #1, Channel #6 */ 341 cpuss_interrupts_dw1_7_IRQn = 248, /*!< 248 [Active] CPUSS DataWire #1, Channel #7 */ 342 cpuss_interrupts_dw1_8_IRQn = 249, /*!< 249 [Active] CPUSS DataWire #1, Channel #8 */ 343 cpuss_interrupts_dw1_9_IRQn = 250, /*!< 250 [Active] CPUSS DataWire #1, Channel #9 */ 344 cpuss_interrupts_dw1_10_IRQn = 251, /*!< 251 [Active] CPUSS DataWire #1, Channel #10 */ 345 cpuss_interrupts_dw1_11_IRQn = 252, /*!< 252 [Active] CPUSS DataWire #1, Channel #11 */ 346 cpuss_interrupts_dw1_12_IRQn = 253, /*!< 253 [Active] CPUSS DataWire #1, Channel #12 */ 347 cpuss_interrupts_dw1_13_IRQn = 254, /*!< 254 [Active] CPUSS DataWire #1, Channel #13 */ 348 cpuss_interrupts_dw1_14_IRQn = 255, /*!< 255 [Active] CPUSS DataWire #1, Channel #14 */ 349 cpuss_interrupts_dw1_15_IRQn = 256, /*!< 256 [Active] CPUSS DataWire #1, Channel #15 */ 350 cpuss_interrupts_dw1_16_IRQn = 257, /*!< 257 [Active] CPUSS DataWire #1, Channel #16 */ 351 cpuss_interrupts_dw1_17_IRQn = 258, /*!< 258 [Active] CPUSS DataWire #1, Channel #17 */ 352 cpuss_interrupts_dw1_18_IRQn = 259, /*!< 259 [Active] CPUSS DataWire #1, Channel #18 */ 353 cpuss_interrupts_dw1_19_IRQn = 260, /*!< 260 [Active] CPUSS DataWire #1, Channel #19 */ 354 cpuss_interrupts_dw1_20_IRQn = 261, /*!< 261 [Active] CPUSS DataWire #1, Channel #20 */ 355 cpuss_interrupts_dw1_21_IRQn = 262, /*!< 262 [Active] CPUSS DataWire #1, Channel #21 */ 356 cpuss_interrupts_dw1_22_IRQn = 263, /*!< 263 [Active] CPUSS DataWire #1, Channel #22 */ 357 cpuss_interrupts_dw1_23_IRQn = 264, /*!< 264 [Active] CPUSS DataWire #1, Channel #23 */ 358 cpuss_interrupts_dw1_24_IRQn = 265, /*!< 265 [Active] CPUSS DataWire #1, Channel #24 */ 359 cpuss_interrupts_dw1_25_IRQn = 266, /*!< 266 [Active] CPUSS DataWire #1, Channel #25 */ 360 cpuss_interrupts_dw1_26_IRQn = 267, /*!< 267 [Active] CPUSS DataWire #1, Channel #26 */ 361 cpuss_interrupts_dw1_27_IRQn = 268, /*!< 268 [Active] CPUSS DataWire #1, Channel #27 */ 362 cpuss_interrupts_dw1_28_IRQn = 269, /*!< 269 [Active] CPUSS DataWire #1, Channel #28 */ 363 cpuss_interrupts_dw1_29_IRQn = 270, /*!< 270 [Active] CPUSS DataWire #1, Channel #29 */ 364 cpuss_interrupts_dw1_30_IRQn = 271, /*!< 271 [Active] CPUSS DataWire #1, Channel #30 */ 365 cpuss_interrupts_dw1_31_IRQn = 272, /*!< 272 [Active] CPUSS DataWire #1, Channel #31 */ 366 cpuss_interrupts_dw1_32_IRQn = 273, /*!< 273 [Active] CPUSS DataWire #1, Channel #32 */ 367 tcpwm_0_interrupts_0_IRQn = 274, /*!< 274 [Active] TCPWM Group #0, Counter #0 */ 368 tcpwm_0_interrupts_1_IRQn = 275, /*!< 275 [Active] TCPWM Group #0, Counter #1 */ 369 tcpwm_0_interrupts_2_IRQn = 276, /*!< 276 [Active] TCPWM Group #0, Counter #2 */ 370 tcpwm_0_interrupts_3_IRQn = 277, /*!< 277 [Active] TCPWM Group #0, Counter #3 */ 371 tcpwm_0_interrupts_4_IRQn = 278, /*!< 278 [Active] TCPWM Group #0, Counter #4 */ 372 tcpwm_0_interrupts_5_IRQn = 279, /*!< 279 [Active] TCPWM Group #0, Counter #5 */ 373 tcpwm_0_interrupts_6_IRQn = 280, /*!< 280 [Active] TCPWM Group #0, Counter #6 */ 374 tcpwm_0_interrupts_7_IRQn = 281, /*!< 281 [Active] TCPWM Group #0, Counter #7 */ 375 tcpwm_0_interrupts_8_IRQn = 282, /*!< 282 [Active] TCPWM Group #0, Counter #8 */ 376 tcpwm_0_interrupts_9_IRQn = 283, /*!< 283 [Active] TCPWM Group #0, Counter #9 */ 377 tcpwm_0_interrupts_10_IRQn = 284, /*!< 284 [Active] TCPWM Group #0, Counter #10 */ 378 tcpwm_0_interrupts_11_IRQn = 285, /*!< 285 [Active] TCPWM Group #0, Counter #11 */ 379 tcpwm_0_interrupts_12_IRQn = 286, /*!< 286 [Active] TCPWM Group #0, Counter #12 */ 380 tcpwm_0_interrupts_13_IRQn = 287, /*!< 287 [Active] TCPWM Group #0, Counter #13 */ 381 tcpwm_0_interrupts_14_IRQn = 288, /*!< 288 [Active] TCPWM Group #0, Counter #14 */ 382 tcpwm_0_interrupts_15_IRQn = 289, /*!< 289 [Active] TCPWM Group #0, Counter #15 */ 383 tcpwm_0_interrupts_16_IRQn = 290, /*!< 290 [Active] TCPWM Group #0, Counter #16 */ 384 tcpwm_0_interrupts_17_IRQn = 291, /*!< 291 [Active] TCPWM Group #0, Counter #17 */ 385 tcpwm_0_interrupts_18_IRQn = 292, /*!< 292 [Active] TCPWM Group #0, Counter #18 */ 386 tcpwm_0_interrupts_19_IRQn = 293, /*!< 293 [Active] TCPWM Group #0, Counter #19 */ 387 tcpwm_0_interrupts_20_IRQn = 294, /*!< 294 [Active] TCPWM Group #0, Counter #20 */ 388 tcpwm_0_interrupts_21_IRQn = 295, /*!< 295 [Active] TCPWM Group #0, Counter #21 */ 389 tcpwm_0_interrupts_22_IRQn = 296, /*!< 296 [Active] TCPWM Group #0, Counter #22 */ 390 tcpwm_0_interrupts_23_IRQn = 297, /*!< 297 [Active] TCPWM Group #0, Counter #23 */ 391 tcpwm_0_interrupts_24_IRQn = 298, /*!< 298 [Active] TCPWM Group #0, Counter #24 */ 392 tcpwm_0_interrupts_25_IRQn = 299, /*!< 299 [Active] TCPWM Group #0, Counter #25 */ 393 tcpwm_0_interrupts_26_IRQn = 300, /*!< 300 [Active] TCPWM Group #0, Counter #26 */ 394 tcpwm_0_interrupts_27_IRQn = 301, /*!< 301 [Active] TCPWM Group #0, Counter #27 */ 395 tcpwm_0_interrupts_28_IRQn = 302, /*!< 302 [Active] TCPWM Group #0, Counter #28 */ 396 tcpwm_0_interrupts_29_IRQn = 303, /*!< 303 [Active] TCPWM Group #0, Counter #29 */ 397 tcpwm_0_interrupts_30_IRQn = 304, /*!< 304 [Active] TCPWM Group #0, Counter #30 */ 398 tcpwm_0_interrupts_31_IRQn = 305, /*!< 305 [Active] TCPWM Group #0, Counter #31 */ 399 tcpwm_0_interrupts_32_IRQn = 306, /*!< 306 [Active] TCPWM Group #0, Counter #32 */ 400 tcpwm_0_interrupts_33_IRQn = 307, /*!< 307 [Active] TCPWM Group #0, Counter #33 */ 401 tcpwm_0_interrupts_34_IRQn = 308, /*!< 308 [Active] TCPWM Group #0, Counter #34 */ 402 tcpwm_0_interrupts_35_IRQn = 309, /*!< 309 [Active] TCPWM Group #0, Counter #35 */ 403 tcpwm_0_interrupts_36_IRQn = 310, /*!< 310 [Active] TCPWM Group #0, Counter #36 */ 404 tcpwm_0_interrupts_37_IRQn = 311, /*!< 311 [Active] TCPWM Group #0, Counter #37 */ 405 tcpwm_0_interrupts_38_IRQn = 312, /*!< 312 [Active] TCPWM Group #0, Counter #38 */ 406 tcpwm_0_interrupts_39_IRQn = 313, /*!< 313 [Active] TCPWM Group #0, Counter #39 */ 407 tcpwm_0_interrupts_40_IRQn = 314, /*!< 314 [Active] TCPWM Group #0, Counter #40 */ 408 tcpwm_0_interrupts_41_IRQn = 315, /*!< 315 [Active] TCPWM Group #0, Counter #41 */ 409 tcpwm_0_interrupts_42_IRQn = 316, /*!< 316 [Active] TCPWM Group #0, Counter #42 */ 410 tcpwm_0_interrupts_43_IRQn = 317, /*!< 317 [Active] TCPWM Group #0, Counter #43 */ 411 tcpwm_0_interrupts_44_IRQn = 318, /*!< 318 [Active] TCPWM Group #0, Counter #44 */ 412 tcpwm_0_interrupts_45_IRQn = 319, /*!< 319 [Active] TCPWM Group #0, Counter #45 */ 413 tcpwm_0_interrupts_46_IRQn = 320, /*!< 320 [Active] TCPWM Group #0, Counter #46 */ 414 tcpwm_0_interrupts_47_IRQn = 321, /*!< 321 [Active] TCPWM Group #0, Counter #47 */ 415 tcpwm_0_interrupts_48_IRQn = 322, /*!< 322 [Active] TCPWM Group #0, Counter #48 */ 416 tcpwm_0_interrupts_49_IRQn = 323, /*!< 323 [Active] TCPWM Group #0, Counter #49 */ 417 tcpwm_0_interrupts_50_IRQn = 324, /*!< 324 [Active] TCPWM Group #0, Counter #50 */ 418 tcpwm_0_interrupts_51_IRQn = 325, /*!< 325 [Active] TCPWM Group #0, Counter #51 */ 419 tcpwm_0_interrupts_52_IRQn = 326, /*!< 326 [Active] TCPWM Group #0, Counter #52 */ 420 tcpwm_0_interrupts_53_IRQn = 327, /*!< 327 [Active] TCPWM Group #0, Counter #53 */ 421 tcpwm_0_interrupts_54_IRQn = 328, /*!< 328 [Active] TCPWM Group #0, Counter #54 */ 422 tcpwm_0_interrupts_55_IRQn = 329, /*!< 329 [Active] TCPWM Group #0, Counter #55 */ 423 tcpwm_0_interrupts_56_IRQn = 330, /*!< 330 [Active] TCPWM Group #0, Counter #56 */ 424 tcpwm_0_interrupts_57_IRQn = 331, /*!< 331 [Active] TCPWM Group #0, Counter #57 */ 425 tcpwm_0_interrupts_58_IRQn = 332, /*!< 332 [Active] TCPWM Group #0, Counter #58 */ 426 tcpwm_0_interrupts_59_IRQn = 333, /*!< 333 [Active] TCPWM Group #0, Counter #59 */ 427 tcpwm_0_interrupts_60_IRQn = 334, /*!< 334 [Active] TCPWM Group #0, Counter #60 */ 428 tcpwm_0_interrupts_61_IRQn = 335, /*!< 335 [Active] TCPWM Group #0, Counter #61 */ 429 tcpwm_0_interrupts_62_IRQn = 336, /*!< 336 [Active] TCPWM Group #0, Counter #62 */ 430 tcpwm_0_interrupts_256_IRQn = 337, /*!< 337 [Active] TCPWM Group #1, Counter #0 */ 431 tcpwm_0_interrupts_257_IRQn = 338, /*!< 338 [Active] TCPWM Group #1, Counter #1 */ 432 tcpwm_0_interrupts_258_IRQn = 339, /*!< 339 [Active] TCPWM Group #1, Counter #2 */ 433 tcpwm_0_interrupts_259_IRQn = 340, /*!< 340 [Active] TCPWM Group #1, Counter #3 */ 434 tcpwm_0_interrupts_260_IRQn = 341, /*!< 341 [Active] TCPWM Group #1, Counter #4 */ 435 tcpwm_0_interrupts_261_IRQn = 342, /*!< 342 [Active] TCPWM Group #1, Counter #5 */ 436 tcpwm_0_interrupts_262_IRQn = 343, /*!< 343 [Active] TCPWM Group #1, Counter #6 */ 437 tcpwm_0_interrupts_263_IRQn = 344, /*!< 344 [Active] TCPWM Group #1, Counter #7 */ 438 tcpwm_0_interrupts_264_IRQn = 345, /*!< 345 [Active] TCPWM Group #1, Counter #8 */ 439 tcpwm_0_interrupts_265_IRQn = 346, /*!< 346 [Active] TCPWM Group #1, Counter #9 */ 440 tcpwm_0_interrupts_266_IRQn = 347, /*!< 347 [Active] TCPWM Group #1, Counter #10 */ 441 tcpwm_0_interrupts_267_IRQn = 348, /*!< 348 [Active] TCPWM Group #1, Counter #11 */ 442 tcpwm_0_interrupts_512_IRQn = 349, /*!< 349 [Active] TCPWM Group #2, Counter #0 */ 443 tcpwm_0_interrupts_513_IRQn = 350, /*!< 350 [Active] TCPWM Group #2, Counter #1 */ 444 tcpwm_0_interrupts_514_IRQn = 351, /*!< 351 [Active] TCPWM Group #2, Counter #2 */ 445 tcpwm_0_interrupts_515_IRQn = 352, /*!< 352 [Active] TCPWM Group #2, Counter #3 */ 446 disconnected_IRQn =1023 /*!< 1023 Disconnected */ 447 } cy_en_intr_t; 448 449 /******************************************************************************* 450 * Processor and Core Peripheral Section 451 *******************************************************************************/ 452 453 #if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ 454 (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ 455 (defined(__ARMCC_VERSION) && defined(__TARGET_ARCH_THUMB) && (__TARGET_ARCH_THUMB == 3)) || \ 456 (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) 457 458 /* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ 459 #define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ 460 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 461 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 462 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 463 #define __MPU_PRESENT 1 /*!< MPU present or not */ 464 465 /** \} Configuration_of_CMSIS */ 466 467 #include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ 468 469 #else 470 471 /* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ 472 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 473 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 474 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 475 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 476 #define __MPU_PRESENT 1 /*!< MPU present or not */ 477 #define __FPU_PRESENT 1 /*!< FPU present or not */ 478 #define __CM0P_PRESENT 1 /*!< CM0P present or not */ 479 #define __DTCM_PRESENT 0 /*!< Data Tightly Coupled Memory is present or not */ 480 #define __ICACHE_PRESENT 0 /*!< Instruction Cache present or not */ 481 #define __DCACHE_PRESENT 0 /*!< Data Cache present or not */ 482 483 /** \} Configuration_of_CMSIS */ 484 485 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 486 487 #endif 488 489 /* Memory Blocks */ 490 #define CY_ROM_BASE 0x00000000UL 491 #define CY_ROM_SIZE 0x00008000UL 492 #define CY_FLASH_LG_SBM_BASE 0x10000000UL 493 #define CY_FLASH_LG_SBM_SIZE 0x000F0000UL 494 #define CY_FLASH_LG_DBM0_BASE 0x10000000UL 495 #define CY_FLASH_LG_DBM0_SIZE 0x00078000UL 496 #define CY_FLASH_SM_DBM0_BASE 0x10078000UL 497 #define CY_FLASH_SM_DBM0_SIZE 0x00010000UL 498 #define CY_FLASH_SM_SBM_BASE 0x100F0000UL 499 #define CY_FLASH_SM_SBM_SIZE 0x00020000UL 500 #define CY_FLASH_LG_DBM1_BASE 0x12000000UL 501 #define CY_FLASH_LG_DBM1_SIZE 0x00078000UL 502 #define CY_FLASH_SM_DBM1_BASE 0x12078000UL 503 #define CY_FLASH_SM_DBM1_SIZE 0x00010000UL 504 #define CY_WFLASH_LG_SBM_BASE 0x14000000UL 505 #define CY_WFLASH_LG_SBM_SIZE 0x00012000UL 506 #define CY_WFLASH_LG_DBM0_BASE 0x14000000UL 507 #define CY_WFLASH_LG_DBM0_SIZE 0x00009000UL 508 #define CY_WFLASH_SM_DBM0_BASE 0x14009000UL 509 #define CY_WFLASH_SM_DBM0_SIZE 0x00003000UL 510 #define CY_WFLASH_SM_SBM_BASE 0x14012000UL 511 #define CY_WFLASH_SM_SBM_SIZE 0x00006000UL 512 #define CY_WFLASH_LG_DBM1_BASE 0x15000000UL 513 #define CY_WFLASH_LG_DBM1_SIZE 0x00009000UL 514 #define CY_WFLASH_SM_DBM1_BASE 0x15009000UL 515 #define CY_WFLASH_SM_DBM1_SIZE 0x00003000UL 516 #define CY_OTPFLASH_BASE 0x16000000UL 517 #define CY_OTPFLASH_SIZE 0x00008000UL 518 #define CY_SFLASH_BASE 0x17000000UL 519 #define CY_SFLASH_SIZE 0x00008000UL 520 #define CY_SFLASH1_BASE 0x17800000UL 521 #define CY_SFLASH1_SIZE 0x00008000UL 522 #define CY_EFUSE_BASE 0x402C0800UL 523 #define CY_EFUSE_SIZE 0x00000200UL 524 #define CY_CAN0MRAM_BASE 0x40530000UL 525 #define CY_CAN0MRAM_SIZE 0x00010000UL 526 #define CY_CAN1MRAM_BASE 0x40550000UL 527 #define CY_CAN1MRAM_SIZE 0x00010000UL 528 #define CY_SRAM_BASE 0x08000000UL 529 #define CY_SRAM_SIZE 0x00020000UL 530 531 #define CY_DEVICE_TVIIBE1M 532 #define CY_DEVICE_SERIES_CYT2B7 533 534 #include "system_psoc6.h" /*!< Category 1A System */ 535 536 /* IP List */ 537 #define CY_IP_MXTTCANFD 1u 538 #define CY_IP_MXTTCANFD_INSTANCES 2u 539 #define CY_IP_MXTTCANFD_VERSION 1u 540 #define CY_IP_M4CPUSS 1u 541 #define CY_IP_M4CPUSS_INSTANCES 1u 542 #define CY_IP_M4CPUSS_VERSION 2u 543 #define CY_IP_M4CPUSS_DMAC 1u 544 #define CY_IP_M4CPUSS_DMAC_INSTANCES 1u 545 #define CY_IP_M4CPUSS_DMAC_VERSION 2u 546 #define CY_IP_M4CPUSS_DMA 1u 547 #define CY_IP_M4CPUSS_DMA_INSTANCES 2u 548 #define CY_IP_M4CPUSS_DMA_VERSION 2u 549 #define CY_IP_MXCRYPTO 1u 550 #define CY_IP_MXCRYPTO_INSTANCES 1u 551 #define CY_IP_MXCRYPTO_VERSION 2u 552 #define CY_IP_MXDFT 1u 553 #define CY_IP_MXDFT_INSTANCES 1u 554 #define CY_IP_MXDFT_VERSION 1u 555 #define CY_IP_MXEFUSE 1u 556 #define CY_IP_MXEFUSE_INSTANCES 1u 557 #define CY_IP_MXEFUSE_VERSION 2u 558 #define CY_IP_MXEVTGEN 1u 559 #define CY_IP_MXEVTGEN_INSTANCES 1u 560 #define CY_IP_MXEVTGEN_VERSION 1u 561 #define CY_IP_MXS40IOSS 1u 562 #define CY_IP_MXS40IOSS_INSTANCES 1u 563 #define CY_IP_MXS40IOSS_VERSION 2u 564 #define CY_IP_MXLIN 1u 565 #define CY_IP_MXLIN_INSTANCES 1u 566 #define CY_IP_MXLIN_VERSION 1u 567 #define CY_IP_MXS40EPASS 1u 568 #define CY_IP_MXS40EPASS_INSTANCES 1u 569 #define CY_IP_MXS40EPASS_VERSION 1u 570 #define CY_IP_MXS40EPASS_ESAR 1u 571 #define CY_IP_MXS40EPASS_ESAR_INSTANCES 3u 572 #define CY_IP_MXS40EPASS_ESAR_VERSION 1u 573 #define CY_IP_MXPERI 1u 574 #define CY_IP_MXPERI_INSTANCES 1u 575 #define CY_IP_MXPERI_VERSION 2u 576 #define CY_IP_MXPERI_TR 1u 577 #define CY_IP_MXPERI_TR_INSTANCES 1u 578 #define CY_IP_MXPERI_TR_VERSION 2u 579 #define CY_IP_MXSCB 1u 580 #define CY_IP_MXSCB_INSTANCES 7u 581 #define CY_IP_MXSCB_VERSION 2u 582 #define CY_IP_MXS40SRSS 1u 583 #define CY_IP_MXS40SRSS_INSTANCES 1u 584 #define CY_IP_MXS40SRSS_VERSION 2u 585 #define CY_IP_MXS40SRSS_RTC 1u 586 #define CY_IP_MXS40SRSS_RTC_INSTANCES 1u 587 #define CY_IP_MXS40SRSS_RTC_VERSION 2u 588 #define CY_IP_MXS40SRSS_MCWDT 1u 589 #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u 590 #define CY_IP_MXS40SRSS_MCWDT_VERSION 2u 591 #define CY_IP_MXTCPWM 1u 592 #define CY_IP_MXTCPWM_INSTANCES 1u 593 #define CY_IP_MXTCPWM_VERSION 2u 594 595 #include "tviibe1m_config.h" 596 #include "gpio_tviibe1m_64_lqfp.h" 597 598 #define CY_SILICON_ID 0xE3C92301UL 599 #define CY_HF_CLK_MAX_FREQ 160000000UL 600 601 #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL 602 603 /******************************************************************************* 604 * SFLASH 605 *******************************************************************************/ 606 607 #define SFLASH_BASE 0x17000000UL 608 #define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x17000000 */ 609 610 /******************************************************************************* 611 * PERI 612 *******************************************************************************/ 613 614 #define PERI_BASE 0x40000000UL 615 #define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ 616 #define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ 617 #define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ 618 #define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ 619 #define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ 620 #define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ 621 #define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ 622 #define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ 623 #define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ 624 #define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ 625 #define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ 626 #define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ 627 #define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ 628 #define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ 629 #define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ 630 #define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ 631 #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ 632 #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ 633 #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ 634 #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ 635 #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ 636 #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ 637 #define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ 638 #define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ 639 #define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ 640 #define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ 641 #define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ 642 #define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ 643 644 /******************************************************************************* 645 * PERI_MS 646 *******************************************************************************/ 647 648 #define PERI_MS_BASE 0x40010000UL 649 #define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ 650 #define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ 651 #define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ 652 #define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ 653 #define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ 654 #define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ 655 #define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ 656 #define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ 657 #define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ 658 #define PERI_MS_PPU_PR8 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[8]) /* 0x40010200 */ 659 #define PERI_MS_PPU_PR9 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[9]) /* 0x40010240 */ 660 #define PERI_MS_PPU_PR10 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[10]) /* 0x40010280 */ 661 #define PERI_MS_PPU_PR11 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[11]) /* 0x400102C0 */ 662 #define PERI_MS_PPU_PR12 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[12]) /* 0x40010300 */ 663 #define PERI_MS_PPU_PR13 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[13]) /* 0x40010340 */ 664 #define PERI_MS_PPU_PR14 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[14]) /* 0x40010380 */ 665 #define PERI_MS_PPU_PR15 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[15]) /* 0x400103C0 */ 666 #define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ 667 #define PERI_MS_PPU_FX_PERI_SECURE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ 668 #define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ 669 #define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ 670 #define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ 671 #define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ 672 #define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ 673 #define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ 674 #define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ 675 #define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ 676 #define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ 677 #define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ 678 #define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ 679 #define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ 680 #define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ 681 #define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ 682 #define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ 683 #define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ 684 #define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ 685 #define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ 686 #define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ 687 #define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ 688 #define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ 689 #define PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ 690 #define PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ 691 #define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ 692 #define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ 693 #define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ 694 #define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ 695 #define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ 696 #define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ 697 #define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ 698 #define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ 699 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ 700 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ 701 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ 702 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ 703 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ 704 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ 705 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ 706 #define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ 707 #define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ 708 #define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ 709 #define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ 710 #define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ 711 #define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ 712 #define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ 713 #define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ 714 #define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ 715 #define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ 716 #define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ 717 #define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ 718 #define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ 719 #define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ 720 #define PERI_MS_PPU_FX_FLASHC_FlashMgmt ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ 721 #define PERI_MS_PPU_FX_FLASHC_MainSafety ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ 722 #define PERI_MS_PPU_FX_FLASHC_WorkSafety ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ 723 #define PERI_MS_PPU_FX_SRSS_GENERAL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ 724 #define PERI_MS_PPU_FX_SRSS_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ 725 #define PERI_MS_PPU_FX_SRSS_SECURE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ 726 #define PERI_MS_PPU_FX_MCWDT0_CONFIG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ 727 #define PERI_MS_PPU_FX_MCWDT1_CONFIG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ 728 #define PERI_MS_PPU_FX_MCWDT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ 729 #define PERI_MS_PPU_FX_MCWDT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ 730 #define PERI_MS_PPU_FX_WDT_CONFIG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ 731 #define PERI_MS_PPU_FX_WDT_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ 732 #define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ 733 #define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ 734 #define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ 735 #define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ 736 #define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ 737 #define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ 738 #define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ 739 #define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ 740 #define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ 741 #define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ 742 #define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ 743 #define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ 744 #define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ 745 #define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ 746 #define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ 747 #define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ 748 #define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ 749 #define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ 750 #define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ 751 #define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ 752 #define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ 753 #define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ 754 #define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ 755 #define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ 756 #define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ 757 #define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ 758 #define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ 759 #define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ 760 #define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ 761 #define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ 762 #define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ 763 #define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ 764 #define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ 765 #define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ 766 #define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ 767 #define PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ 768 #define PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ 769 #define PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ 770 #define PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ 771 #define PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ 772 #define PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ 773 #define PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ 774 #define PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ 775 #define PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ 776 #define PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ 777 #define PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ 778 #define PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ 779 #define PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ 780 #define PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ 781 #define PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ 782 #define PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ 783 #define PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ 784 #define PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ 785 #define PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ 786 #define PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ 787 #define PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ 788 #define PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ 789 #define PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ 790 #define PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ 791 #define PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ 792 #define PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ 793 #define PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ 794 #define PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ 795 #define PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ 796 #define PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ 797 #define PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ 798 #define PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ 799 #define PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ 800 #define PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ 801 #define PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ 802 #define PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ 803 #define PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ 804 #define PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ 805 #define PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ 806 #define PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ 807 #define PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ 808 #define PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ 809 #define PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ 810 #define PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ 811 #define PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ 812 #define PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ 813 #define PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ 814 #define PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ 815 #define PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ 816 #define PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ 817 #define PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ 818 #define PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ 819 #define PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ 820 #define PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ 821 #define PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ 822 #define PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ 823 #define PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ 824 #define PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ 825 #define PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ 826 #define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ 827 #define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ 828 #define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ 829 #define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ 830 #define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ 831 #define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ 832 #define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ 833 #define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ 834 #define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ 835 #define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ 836 #define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ 837 #define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ 838 #define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ 839 #define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ 840 #define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ 841 #define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ 842 #define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ 843 #define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ 844 #define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ 845 #define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ 846 #define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ 847 #define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ 848 #define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ 849 #define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ 850 #define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ 851 #define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ 852 #define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ 853 #define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ 854 #define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ 855 #define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ 856 #define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ 857 #define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ 858 #define PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ 859 #define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ 860 #define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ 861 #define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ 862 #define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ 863 #define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ 864 #define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ 865 #define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ 866 #define PERI_MS_PPU_FX_BIST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ 867 #define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ 868 #define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ 869 #define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ 870 #define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ 871 #define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ 872 #define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ 873 #define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ 874 #define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ 875 #define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ 876 #define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ 877 #define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ 878 #define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ 879 #define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ 880 #define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ 881 #define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ 882 #define PERI_MS_PPU_FX_HSIOM_PRT15_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ 883 #define PERI_MS_PPU_FX_HSIOM_PRT16_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ 884 #define PERI_MS_PPU_FX_HSIOM_PRT17_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ 885 #define PERI_MS_PPU_FX_HSIOM_PRT18_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ 886 #define PERI_MS_PPU_FX_HSIOM_PRT19_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ 887 #define PERI_MS_PPU_FX_HSIOM_PRT20_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ 888 #define PERI_MS_PPU_FX_HSIOM_PRT21_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ 889 #define PERI_MS_PPU_FX_HSIOM_PRT22_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ 890 #define PERI_MS_PPU_FX_HSIOM_PRT23_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ 891 #define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ 892 #define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ 893 #define PERI_MS_PPU_FX_HSIOM_ALTJTAG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ 894 #define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ 895 #define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[229]) /* 0x40014140 */ 896 #define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[230]) /* 0x40014180 */ 897 #define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[231]) /* 0x400141C0 */ 898 #define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[232]) /* 0x40014200 */ 899 #define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[233]) /* 0x40014240 */ 900 #define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[234]) /* 0x40014280 */ 901 #define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[235]) /* 0x400142C0 */ 902 #define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[236]) /* 0x40014300 */ 903 #define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[237]) /* 0x40014340 */ 904 #define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[238]) /* 0x40014380 */ 905 #define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[239]) /* 0x400143C0 */ 906 #define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[240]) /* 0x40014400 */ 907 #define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[241]) /* 0x40014440 */ 908 #define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[242]) /* 0x40014480 */ 909 #define PERI_MS_PPU_FX_GPIO_PRT15_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[243]) /* 0x400144C0 */ 910 #define PERI_MS_PPU_FX_GPIO_PRT16_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[244]) /* 0x40014500 */ 911 #define PERI_MS_PPU_FX_GPIO_PRT17_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[245]) /* 0x40014540 */ 912 #define PERI_MS_PPU_FX_GPIO_PRT18_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[246]) /* 0x40014580 */ 913 #define PERI_MS_PPU_FX_GPIO_PRT19_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[247]) /* 0x400145C0 */ 914 #define PERI_MS_PPU_FX_GPIO_PRT20_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[248]) /* 0x40014600 */ 915 #define PERI_MS_PPU_FX_GPIO_PRT21_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[249]) /* 0x40014640 */ 916 #define PERI_MS_PPU_FX_GPIO_PRT22_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[250]) /* 0x40014680 */ 917 #define PERI_MS_PPU_FX_GPIO_PRT23_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[251]) /* 0x400146C0 */ 918 #define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[252]) /* 0x40014700 */ 919 #define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[253]) /* 0x40014740 */ 920 #define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[254]) /* 0x40014780 */ 921 #define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[255]) /* 0x400147C0 */ 922 #define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[256]) /* 0x40014800 */ 923 #define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[257]) /* 0x40014840 */ 924 #define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[258]) /* 0x40014880 */ 925 #define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[259]) /* 0x400148C0 */ 926 #define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[260]) /* 0x40014900 */ 927 #define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[261]) /* 0x40014940 */ 928 #define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[262]) /* 0x40014980 */ 929 #define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[263]) /* 0x400149C0 */ 930 #define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[264]) /* 0x40014A00 */ 931 #define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[265]) /* 0x40014A40 */ 932 #define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[266]) /* 0x40014A80 */ 933 #define PERI_MS_PPU_FX_GPIO_PRT15_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[267]) /* 0x40014AC0 */ 934 #define PERI_MS_PPU_FX_GPIO_PRT16_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[268]) /* 0x40014B00 */ 935 #define PERI_MS_PPU_FX_GPIO_PRT17_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[269]) /* 0x40014B40 */ 936 #define PERI_MS_PPU_FX_GPIO_PRT18_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[270]) /* 0x40014B80 */ 937 #define PERI_MS_PPU_FX_GPIO_PRT19_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[271]) /* 0x40014BC0 */ 938 #define PERI_MS_PPU_FX_GPIO_PRT20_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[272]) /* 0x40014C00 */ 939 #define PERI_MS_PPU_FX_GPIO_PRT21_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[273]) /* 0x40014C40 */ 940 #define PERI_MS_PPU_FX_GPIO_PRT22_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[274]) /* 0x40014C80 */ 941 #define PERI_MS_PPU_FX_GPIO_PRT23_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[275]) /* 0x40014CC0 */ 942 #define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[276]) /* 0x40014D00 */ 943 #define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[277]) /* 0x40014D40 */ 944 #define PERI_MS_PPU_FX_SMARTIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[278]) /* 0x40014D80 */ 945 #define PERI_MS_PPU_FX_SMARTIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[279]) /* 0x40014DC0 */ 946 #define PERI_MS_PPU_FX_SMARTIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[280]) /* 0x40014E00 */ 947 #define PERI_MS_PPU_FX_SMARTIO_PRT15_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[281]) /* 0x40014E40 */ 948 #define PERI_MS_PPU_FX_SMARTIO_PRT17_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[282]) /* 0x40014E80 */ 949 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[283]) /* 0x40014EC0 */ 950 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[284]) /* 0x40014F00 */ 951 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[285]) /* 0x40014F40 */ 952 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[286]) /* 0x40014F80 */ 953 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[287]) /* 0x40014FC0 */ 954 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[288]) /* 0x40015000 */ 955 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[289]) /* 0x40015040 */ 956 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[290]) /* 0x40015080 */ 957 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT8_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[291]) /* 0x400150C0 */ 958 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT9_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[292]) /* 0x40015100 */ 959 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT10_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[293]) /* 0x40015140 */ 960 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT11_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[294]) /* 0x40015180 */ 961 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT12_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[295]) /* 0x400151C0 */ 962 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT13_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[296]) /* 0x40015200 */ 963 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT14_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[297]) /* 0x40015240 */ 964 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT15_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[298]) /* 0x40015280 */ 965 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT16_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[299]) /* 0x400152C0 */ 966 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT17_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[300]) /* 0x40015300 */ 967 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT18_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[301]) /* 0x40015340 */ 968 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT19_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[302]) /* 0x40015380 */ 969 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT20_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[303]) /* 0x400153C0 */ 970 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT21_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[304]) /* 0x40015400 */ 971 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT22_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[305]) /* 0x40015440 */ 972 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT23_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[306]) /* 0x40015480 */ 973 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT24_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[307]) /* 0x400154C0 */ 974 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT25_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[308]) /* 0x40015500 */ 975 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT26_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[309]) /* 0x40015540 */ 976 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT27_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[310]) /* 0x40015580 */ 977 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT28_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[311]) /* 0x400155C0 */ 978 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT29_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[312]) /* 0x40015600 */ 979 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT30_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[313]) /* 0x40015640 */ 980 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT31_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[314]) /* 0x40015680 */ 981 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT32_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[315]) /* 0x400156C0 */ 982 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT33_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[316]) /* 0x40015700 */ 983 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT34_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[317]) /* 0x40015740 */ 984 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT35_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[318]) /* 0x40015780 */ 985 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT36_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[319]) /* 0x400157C0 */ 986 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT37_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[320]) /* 0x40015800 */ 987 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT38_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[321]) /* 0x40015840 */ 988 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT39_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[322]) /* 0x40015880 */ 989 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT40_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[323]) /* 0x400158C0 */ 990 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT41_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[324]) /* 0x40015900 */ 991 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT42_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[325]) /* 0x40015940 */ 992 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT43_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[326]) /* 0x40015980 */ 993 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT44_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[327]) /* 0x400159C0 */ 994 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT45_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[328]) /* 0x40015A00 */ 995 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT46_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[329]) /* 0x40015A40 */ 996 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT47_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[330]) /* 0x40015A80 */ 997 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT48_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[331]) /* 0x40015AC0 */ 998 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT49_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[332]) /* 0x40015B00 */ 999 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT50_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[333]) /* 0x40015B40 */ 1000 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT51_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[334]) /* 0x40015B80 */ 1001 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT52_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[335]) /* 0x40015BC0 */ 1002 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT53_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[336]) /* 0x40015C00 */ 1003 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT54_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[337]) /* 0x40015C40 */ 1004 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT55_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[338]) /* 0x40015C80 */ 1005 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT56_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[339]) /* 0x40015CC0 */ 1006 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT57_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[340]) /* 0x40015D00 */ 1007 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT58_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[341]) /* 0x40015D40 */ 1008 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT59_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[342]) /* 0x40015D80 */ 1009 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT60_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[343]) /* 0x40015DC0 */ 1010 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT61_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[344]) /* 0x40015E00 */ 1011 #define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT62_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[345]) /* 0x40015E40 */ 1012 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[346]) /* 0x40015E80 */ 1013 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[347]) /* 0x40015EC0 */ 1014 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[348]) /* 0x40015F00 */ 1015 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[349]) /* 0x40015F40 */ 1016 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[350]) /* 0x40015F80 */ 1017 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[351]) /* 0x40015FC0 */ 1018 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[352]) /* 0x40016000 */ 1019 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[353]) /* 0x40016040 */ 1020 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT8_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[354]) /* 0x40016080 */ 1021 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT9_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[355]) /* 0x400160C0 */ 1022 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT10_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[356]) /* 0x40016100 */ 1023 #define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT11_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[357]) /* 0x40016140 */ 1024 #define PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[358]) /* 0x40016180 */ 1025 #define PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[359]) /* 0x400161C0 */ 1026 #define PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[360]) /* 0x40016200 */ 1027 #define PERI_MS_PPU_FX_TCPWM0_GRP2_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[361]) /* 0x40016240 */ 1028 #define PERI_MS_PPU_FX_EVTGEN0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[362]) /* 0x40016280 */ 1029 #define PERI_MS_PPU_FX_LIN0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[363]) /* 0x400162C0 */ 1030 #define PERI_MS_PPU_FX_LIN0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[364]) /* 0x40016300 */ 1031 #define PERI_MS_PPU_FX_LIN0_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[365]) /* 0x40016340 */ 1032 #define PERI_MS_PPU_FX_LIN0_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[366]) /* 0x40016380 */ 1033 #define PERI_MS_PPU_FX_LIN0_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[367]) /* 0x400163C0 */ 1034 #define PERI_MS_PPU_FX_LIN0_CH4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[368]) /* 0x40016400 */ 1035 #define PERI_MS_PPU_FX_LIN0_CH5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[369]) /* 0x40016440 */ 1036 #define PERI_MS_PPU_FX_LIN0_CH6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[370]) /* 0x40016480 */ 1037 #define PERI_MS_PPU_FX_LIN0_CH7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[371]) /* 0x400164C0 */ 1038 #define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[372]) /* 0x40016500 */ 1039 #define PERI_MS_PPU_FX_CANFD0_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[373]) /* 0x40016540 */ 1040 #define PERI_MS_PPU_FX_CANFD0_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[374]) /* 0x40016580 */ 1041 #define PERI_MS_PPU_FX_CANFD1_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[375]) /* 0x400165C0 */ 1042 #define PERI_MS_PPU_FX_CANFD1_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[376]) /* 0x40016600 */ 1043 #define PERI_MS_PPU_FX_CANFD1_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[377]) /* 0x40016640 */ 1044 #define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[378]) /* 0x40016680 */ 1045 #define PERI_MS_PPU_FX_CANFD1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[379]) /* 0x400166C0 */ 1046 #define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[380]) /* 0x40016700 */ 1047 #define PERI_MS_PPU_FX_CANFD1_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[381]) /* 0x40016740 */ 1048 #define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[382]) /* 0x40016780 */ 1049 #define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[383]) /* 0x400167C0 */ 1050 #define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[384]) /* 0x40016800 */ 1051 #define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[385]) /* 0x40016840 */ 1052 #define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[386]) /* 0x40016880 */ 1053 #define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[387]) /* 0x400168C0 */ 1054 #define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[388]) /* 0x40016900 */ 1055 #define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[389]) /* 0x40016940 */ 1056 #define PERI_MS_PPU_FX_PASS0_SAR0_SAR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[390]) /* 0x40016980 */ 1057 #define PERI_MS_PPU_FX_PASS0_SAR1_SAR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[391]) /* 0x400169C0 */ 1058 #define PERI_MS_PPU_FX_PASS0_SAR2_SAR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[392]) /* 0x40016A00 */ 1059 #define PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[393]) /* 0x40016A40 */ 1060 #define PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[394]) /* 0x40016A80 */ 1061 #define PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[395]) /* 0x40016AC0 */ 1062 #define PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[396]) /* 0x40016B00 */ 1063 #define PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[397]) /* 0x40016B40 */ 1064 #define PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[398]) /* 0x40016B80 */ 1065 #define PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[399]) /* 0x40016BC0 */ 1066 #define PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[400]) /* 0x40016C00 */ 1067 #define PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[401]) /* 0x40016C40 */ 1068 #define PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[402]) /* 0x40016C80 */ 1069 #define PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[403]) /* 0x40016CC0 */ 1070 #define PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[404]) /* 0x40016D00 */ 1071 #define PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[405]) /* 0x40016D40 */ 1072 #define PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[406]) /* 0x40016D80 */ 1073 #define PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[407]) /* 0x40016DC0 */ 1074 #define PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[408]) /* 0x40016E00 */ 1075 #define PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[409]) /* 0x40016E40 */ 1076 #define PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[410]) /* 0x40016E80 */ 1077 #define PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[411]) /* 0x40016EC0 */ 1078 #define PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[412]) /* 0x40016F00 */ 1079 #define PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[413]) /* 0x40016F40 */ 1080 #define PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[414]) /* 0x40016F80 */ 1081 #define PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[415]) /* 0x40016FC0 */ 1082 #define PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[416]) /* 0x40017000 */ 1083 #define PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[417]) /* 0x40017040 */ 1084 #define PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[418]) /* 0x40017080 */ 1085 #define PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[419]) /* 0x400170C0 */ 1086 #define PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[420]) /* 0x40017100 */ 1087 #define PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[421]) /* 0x40017140 */ 1088 #define PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[422]) /* 0x40017180 */ 1089 #define PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[423]) /* 0x400171C0 */ 1090 #define PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[424]) /* 0x40017200 */ 1091 #define PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[425]) /* 0x40017240 */ 1092 #define PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[426]) /* 0x40017280 */ 1093 #define PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[427]) /* 0x400172C0 */ 1094 #define PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[428]) /* 0x40017300 */ 1095 #define PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[429]) /* 0x40017340 */ 1096 #define PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[430]) /* 0x40017380 */ 1097 #define PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[431]) /* 0x400173C0 */ 1098 #define PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[432]) /* 0x40017400 */ 1099 #define PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[433]) /* 0x40017440 */ 1100 #define PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[434]) /* 0x40017480 */ 1101 #define PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[435]) /* 0x400174C0 */ 1102 #define PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[436]) /* 0x40017500 */ 1103 #define PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[437]) /* 0x40017540 */ 1104 #define PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[438]) /* 0x40017580 */ 1105 #define PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[439]) /* 0x400175C0 */ 1106 #define PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[440]) /* 0x40017600 */ 1107 #define PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[441]) /* 0x40017640 */ 1108 #define PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[442]) /* 0x40017680 */ 1109 #define PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[443]) /* 0x400176C0 */ 1110 #define PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[444]) /* 0x40017700 */ 1111 #define PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[445]) /* 0x40017740 */ 1112 #define PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[446]) /* 0x40017780 */ 1113 #define PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[447]) /* 0x400177C0 */ 1114 #define PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[448]) /* 0x40017800 */ 1115 #define PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[449]) /* 0x40017840 */ 1116 #define PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[450]) /* 0x40017880 */ 1117 #define PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[451]) /* 0x400178C0 */ 1118 #define PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[452]) /* 0x40017900 */ 1119 #define PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[453]) /* 0x40017940 */ 1120 #define PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[454]) /* 0x40017980 */ 1121 #define PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[455]) /* 0x400179C0 */ 1122 #define PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[456]) /* 0x40017A00 */ 1123 #define PERI_MS_PPU_FX_PASS0_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[457]) /* 0x40017A40 */ 1124 1125 /******************************************************************************* 1126 * CRYPTO 1127 *******************************************************************************/ 1128 1129 #define CRYPTO_BASE 0x40100000UL 1130 #define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ 1131 1132 /******************************************************************************* 1133 * CPUSS 1134 *******************************************************************************/ 1135 1136 #define CPUSS_BASE 0x40200000UL 1137 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ 1138 1139 /******************************************************************************* 1140 * FAULT 1141 *******************************************************************************/ 1142 1143 #define FAULT_BASE 0x40210000UL 1144 #define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ 1145 #define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ 1146 #define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ 1147 #define FAULT_STRUCT2 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[2]) /* 0x40210200 */ 1148 #define FAULT_STRUCT3 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[3]) /* 0x40210300 */ 1149 1150 /******************************************************************************* 1151 * IPC 1152 *******************************************************************************/ 1153 1154 #define IPC_BASE 0x40220000UL 1155 #define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ 1156 #define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ 1157 #define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ 1158 #define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ 1159 #define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ 1160 #define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ 1161 #define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ 1162 #define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ 1163 #define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ 1164 #define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ 1165 #define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ 1166 #define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ 1167 #define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ 1168 #define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ 1169 #define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ 1170 #define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ 1171 #define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ 1172 1173 /******************************************************************************* 1174 * PROT 1175 *******************************************************************************/ 1176 1177 #define PROT_BASE 0x40230000UL 1178 #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ 1179 #define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ 1180 #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ 1181 #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ 1182 #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ 1183 #define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ 1184 #define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ 1185 #define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ 1186 #define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ 1187 #define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ 1188 #define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ 1189 #define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ 1190 #define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ 1191 #define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ 1192 #define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ 1193 #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ 1194 #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ 1195 #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ 1196 #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ 1197 #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ 1198 #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ 1199 #define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ 1200 #define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ 1201 #define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ 1202 #define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ 1203 #define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ 1204 #define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ 1205 #define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ 1206 #define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ 1207 #define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ 1208 #define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ 1209 #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ 1210 #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ 1211 #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ 1212 #define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ 1213 #define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ 1214 #define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ 1215 #define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ 1216 #define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ 1217 #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ 1218 #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ 1219 #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ 1220 1221 /******************************************************************************* 1222 * FLASHC 1223 *******************************************************************************/ 1224 1225 #define FLASHC_BASE 0x40240000UL 1226 #define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ 1227 #define FLASHC_FM_CTL_ECT ((FLASHC_FM_CTL_ECT_Type*) &FLASHC->FM_CTL_ECT) /* 0x4024F000 */ 1228 1229 /******************************************************************************* 1230 * SRSS 1231 *******************************************************************************/ 1232 1233 #define SRSS_BASE 0x40260000UL 1234 #define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ 1235 #define CSV_HF ((CSV_HF_Type*) &SRSS->CSV_HF) /* 0x40261400 */ 1236 #define CSV_HF_CSV0 ((CSV_HF_CSV_Type*) &SRSS->CSV_HF.CSV[0]) /* 0x40261400 */ 1237 #define CSV_HF_CSV1 ((CSV_HF_CSV_Type*) &SRSS->CSV_HF.CSV[1]) /* 0x40261410 */ 1238 #define CSV_HF_CSV2 ((CSV_HF_CSV_Type*) &SRSS->CSV_HF.CSV[2]) /* 0x40261420 */ 1239 #define CSV_REF ((CSV_REF_Type*) &SRSS->CSV_REF) /* 0x40261710 */ 1240 #define CSV_REF_CSV ((CSV_REF_CSV_Type*) &SRSS->CSV_REF.CSV) /* 0x40261710 */ 1241 #define CSV_LF ((CSV_LF_Type*) &SRSS->CSV_LF) /* 0x40261720 */ 1242 #define CSV_LF_CSV ((CSV_LF_CSV_Type*) &SRSS->CSV_LF.CSV) /* 0x40261720 */ 1243 #define CSV_ILO ((CSV_ILO_Type*) &SRSS->CSV_ILO) /* 0x40261730 */ 1244 #define CSV_ILO_CSV ((CSV_ILO_CSV_Type*) &SRSS->CSV_ILO.CSV) /* 0x40261730 */ 1245 #define MCWDT0 ((MCWDT_Type*) &SRSS->MCWDT[0]) /* 0x40268000 */ 1246 #define MCWDT1 ((MCWDT_Type*) &SRSS->MCWDT[1]) /* 0x40268100 */ 1247 #define MCWDT0_CTR0 ((MCWDT_CTR_Type*) &SRSS->MCWDT[0].CTR[0]) /* 0x40268000 */ 1248 #define MCWDT0_CTR1 ((MCWDT_CTR_Type*) &SRSS->MCWDT[0].CTR[1]) /* 0x40268020 */ 1249 #define MCWDT1_CTR0 ((MCWDT_CTR_Type*) &SRSS->MCWDT[1].CTR[0]) /* 0x40268100 */ 1250 #define MCWDT1_CTR1 ((MCWDT_CTR_Type*) &SRSS->MCWDT[1].CTR[1]) /* 0x40268120 */ 1251 #define WDT ((WDT_Type*) &SRSS->WDT_STRUCT) /* 0x4026C000 */ 1252 1253 /******************************************************************************* 1254 * BACKUP 1255 *******************************************************************************/ 1256 1257 #define BACKUP_BASE 0x40270000UL 1258 #define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ 1259 1260 /******************************************************************************* 1261 * DW 1262 *******************************************************************************/ 1263 1264 #define DW0_BASE 0x40280000UL 1265 #define DW1_BASE 0x40290000UL 1266 #define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ 1267 #define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ 1268 #define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ 1269 #define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ 1270 #define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ 1271 #define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ 1272 #define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ 1273 #define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ 1274 #define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ 1275 #define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ 1276 #define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ 1277 #define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ 1278 #define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ 1279 #define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ 1280 #define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ 1281 #define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ 1282 #define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ 1283 #define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ 1284 #define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ 1285 #define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ 1286 #define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ 1287 #define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ 1288 #define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ 1289 #define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ 1290 #define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ 1291 #define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ 1292 #define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ 1293 #define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ 1294 #define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ 1295 #define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ 1296 #define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ 1297 #define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ 1298 #define DW0_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[30]) /* 0x40288780 */ 1299 #define DW0_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[31]) /* 0x402887C0 */ 1300 #define DW0_CH_STRUCT32 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[32]) /* 0x40288800 */ 1301 #define DW0_CH_STRUCT33 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[33]) /* 0x40288840 */ 1302 #define DW0_CH_STRUCT34 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[34]) /* 0x40288880 */ 1303 #define DW0_CH_STRUCT35 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[35]) /* 0x402888C0 */ 1304 #define DW0_CH_STRUCT36 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[36]) /* 0x40288900 */ 1305 #define DW0_CH_STRUCT37 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[37]) /* 0x40288940 */ 1306 #define DW0_CH_STRUCT38 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[38]) /* 0x40288980 */ 1307 #define DW0_CH_STRUCT39 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[39]) /* 0x402889C0 */ 1308 #define DW0_CH_STRUCT40 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[40]) /* 0x40288A00 */ 1309 #define DW0_CH_STRUCT41 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[41]) /* 0x40288A40 */ 1310 #define DW0_CH_STRUCT42 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[42]) /* 0x40288A80 */ 1311 #define DW0_CH_STRUCT43 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[43]) /* 0x40288AC0 */ 1312 #define DW0_CH_STRUCT44 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[44]) /* 0x40288B00 */ 1313 #define DW0_CH_STRUCT45 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[45]) /* 0x40288B40 */ 1314 #define DW0_CH_STRUCT46 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[46]) /* 0x40288B80 */ 1315 #define DW0_CH_STRUCT47 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[47]) /* 0x40288BC0 */ 1316 #define DW0_CH_STRUCT48 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[48]) /* 0x40288C00 */ 1317 #define DW0_CH_STRUCT49 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[49]) /* 0x40288C40 */ 1318 #define DW0_CH_STRUCT50 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[50]) /* 0x40288C80 */ 1319 #define DW0_CH_STRUCT51 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[51]) /* 0x40288CC0 */ 1320 #define DW0_CH_STRUCT52 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[52]) /* 0x40288D00 */ 1321 #define DW0_CH_STRUCT53 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[53]) /* 0x40288D40 */ 1322 #define DW0_CH_STRUCT54 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[54]) /* 0x40288D80 */ 1323 #define DW0_CH_STRUCT55 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[55]) /* 0x40288DC0 */ 1324 #define DW0_CH_STRUCT56 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[56]) /* 0x40288E00 */ 1325 #define DW0_CH_STRUCT57 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[57]) /* 0x40288E40 */ 1326 #define DW0_CH_STRUCT58 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[58]) /* 0x40288E80 */ 1327 #define DW0_CH_STRUCT59 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[59]) /* 0x40288EC0 */ 1328 #define DW0_CH_STRUCT60 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[60]) /* 0x40288F00 */ 1329 #define DW0_CH_STRUCT61 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[61]) /* 0x40288F40 */ 1330 #define DW0_CH_STRUCT62 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[62]) /* 0x40288F80 */ 1331 #define DW0_CH_STRUCT63 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[63]) /* 0x40288FC0 */ 1332 #define DW0_CH_STRUCT64 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[64]) /* 0x40289000 */ 1333 #define DW0_CH_STRUCT65 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[65]) /* 0x40289040 */ 1334 #define DW0_CH_STRUCT66 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[66]) /* 0x40289080 */ 1335 #define DW0_CH_STRUCT67 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[67]) /* 0x402890C0 */ 1336 #define DW0_CH_STRUCT68 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[68]) /* 0x40289100 */ 1337 #define DW0_CH_STRUCT69 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[69]) /* 0x40289140 */ 1338 #define DW0_CH_STRUCT70 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[70]) /* 0x40289180 */ 1339 #define DW0_CH_STRUCT71 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[71]) /* 0x402891C0 */ 1340 #define DW0_CH_STRUCT72 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[72]) /* 0x40289200 */ 1341 #define DW0_CH_STRUCT73 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[73]) /* 0x40289240 */ 1342 #define DW0_CH_STRUCT74 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[74]) /* 0x40289280 */ 1343 #define DW0_CH_STRUCT75 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[75]) /* 0x402892C0 */ 1344 #define DW0_CH_STRUCT76 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[76]) /* 0x40289300 */ 1345 #define DW0_CH_STRUCT77 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[77]) /* 0x40289340 */ 1346 #define DW0_CH_STRUCT78 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[78]) /* 0x40289380 */ 1347 #define DW0_CH_STRUCT79 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[79]) /* 0x402893C0 */ 1348 #define DW0_CH_STRUCT80 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[80]) /* 0x40289400 */ 1349 #define DW0_CH_STRUCT81 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[81]) /* 0x40289440 */ 1350 #define DW0_CH_STRUCT82 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[82]) /* 0x40289480 */ 1351 #define DW0_CH_STRUCT83 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[83]) /* 0x402894C0 */ 1352 #define DW0_CH_STRUCT84 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[84]) /* 0x40289500 */ 1353 #define DW0_CH_STRUCT85 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[85]) /* 0x40289540 */ 1354 #define DW0_CH_STRUCT86 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[86]) /* 0x40289580 */ 1355 #define DW0_CH_STRUCT87 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[87]) /* 0x402895C0 */ 1356 #define DW0_CH_STRUCT88 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[88]) /* 0x40289600 */ 1357 #define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ 1358 #define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ 1359 #define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ 1360 #define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ 1361 #define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ 1362 #define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ 1363 #define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ 1364 #define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ 1365 #define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ 1366 #define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ 1367 #define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ 1368 #define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ 1369 #define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ 1370 #define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ 1371 #define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ 1372 #define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ 1373 #define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ 1374 #define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ 1375 #define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ 1376 #define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ 1377 #define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ 1378 #define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ 1379 #define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ 1380 #define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ 1381 #define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ 1382 #define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ 1383 #define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ 1384 #define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ 1385 #define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ 1386 #define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ 1387 #define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ 1388 #define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ 1389 #define DW1_CH_STRUCT32 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[32]) /* 0x40298800 */ 1390 1391 /******************************************************************************* 1392 * DMAC 1393 *******************************************************************************/ 1394 1395 #define DMAC_BASE 0x402A0000UL 1396 #define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ 1397 #define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ 1398 #define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ 1399 #define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ 1400 #define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ 1401 1402 /******************************************************************************* 1403 * EFUSE 1404 *******************************************************************************/ 1405 1406 #define EFUSE_BASE 0x402C0000UL 1407 #define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ 1408 1409 /******************************************************************************* 1410 * HSIOM 1411 *******************************************************************************/ 1412 1413 #define HSIOM_BASE 0x40300000UL 1414 #define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ 1415 #define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ 1416 #define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ 1417 #define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ 1418 #define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ 1419 #define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ 1420 #define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ 1421 #define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ 1422 #define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ 1423 #define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ 1424 #define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ 1425 #define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ 1426 #define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ 1427 #define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ 1428 #define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ 1429 #define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ 1430 #define HSIOM_PRT15 ((HSIOM_PRT_Type*) &HSIOM->PRT[15]) /* 0x403000F0 */ 1431 #define HSIOM_PRT16 ((HSIOM_PRT_Type*) &HSIOM->PRT[16]) /* 0x40300100 */ 1432 #define HSIOM_PRT17 ((HSIOM_PRT_Type*) &HSIOM->PRT[17]) /* 0x40300110 */ 1433 #define HSIOM_PRT18 ((HSIOM_PRT_Type*) &HSIOM->PRT[18]) /* 0x40300120 */ 1434 #define HSIOM_PRT19 ((HSIOM_PRT_Type*) &HSIOM->PRT[19]) /* 0x40300130 */ 1435 #define HSIOM_PRT20 ((HSIOM_PRT_Type*) &HSIOM->PRT[20]) /* 0x40300140 */ 1436 #define HSIOM_PRT21 ((HSIOM_PRT_Type*) &HSIOM->PRT[21]) /* 0x40300150 */ 1437 #define HSIOM_PRT22 ((HSIOM_PRT_Type*) &HSIOM->PRT[22]) /* 0x40300160 */ 1438 #define HSIOM_PRT23 ((HSIOM_PRT_Type*) &HSIOM->PRT[23]) /* 0x40300170 */ 1439 1440 /******************************************************************************* 1441 * GPIO 1442 *******************************************************************************/ 1443 1444 #define GPIO_BASE 0x40310000UL 1445 #define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ 1446 #define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ 1447 #define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ 1448 #define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ 1449 #define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ 1450 #define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ 1451 #define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ 1452 #define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ 1453 #define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ 1454 #define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ 1455 #define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ 1456 #define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ 1457 #define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ 1458 #define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ 1459 #define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ 1460 #define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ 1461 #define GPIO_PRT15 ((GPIO_PRT_Type*) &GPIO->PRT[15]) /* 0x40310780 */ 1462 #define GPIO_PRT16 ((GPIO_PRT_Type*) &GPIO->PRT[16]) /* 0x40310800 */ 1463 #define GPIO_PRT17 ((GPIO_PRT_Type*) &GPIO->PRT[17]) /* 0x40310880 */ 1464 #define GPIO_PRT18 ((GPIO_PRT_Type*) &GPIO->PRT[18]) /* 0x40310900 */ 1465 #define GPIO_PRT19 ((GPIO_PRT_Type*) &GPIO->PRT[19]) /* 0x40310980 */ 1466 #define GPIO_PRT20 ((GPIO_PRT_Type*) &GPIO->PRT[20]) /* 0x40310A00 */ 1467 #define GPIO_PRT21 ((GPIO_PRT_Type*) &GPIO->PRT[21]) /* 0x40310A80 */ 1468 #define GPIO_PRT22 ((GPIO_PRT_Type*) &GPIO->PRT[22]) /* 0x40310B00 */ 1469 #define GPIO_PRT23 ((GPIO_PRT_Type*) &GPIO->PRT[23]) /* 0x40310B80 */ 1470 1471 /******************************************************************************* 1472 * SMARTIO 1473 *******************************************************************************/ 1474 1475 #define SMARTIO_BASE 0x40320000UL 1476 #define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ 1477 #define SMARTIO_PRT12 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[12]) /* 0x40320C00 */ 1478 #define SMARTIO_PRT13 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[13]) /* 0x40320D00 */ 1479 #define SMARTIO_PRT14 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[14]) /* 0x40320E00 */ 1480 #define SMARTIO_PRT15 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[15]) /* 0x40320F00 */ 1481 #define SMARTIO_PRT17 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[17]) /* 0x40321100 */ 1482 1483 /******************************************************************************* 1484 * TCPWM 1485 *******************************************************************************/ 1486 1487 #define TCPWM0_BASE 0x40380000UL 1488 #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ 1489 #define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ 1490 #define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ 1491 #define TCPWM0_GRP2 ((TCPWM_GRP_Type*) &TCPWM0->GRP[2]) /* 0x40390000 */ 1492 #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ 1493 #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ 1494 #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ 1495 #define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ 1496 #define TCPWM0_GRP0_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[4]) /* 0x40380200 */ 1497 #define TCPWM0_GRP0_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[5]) /* 0x40380280 */ 1498 #define TCPWM0_GRP0_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[6]) /* 0x40380300 */ 1499 #define TCPWM0_GRP0_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[7]) /* 0x40380380 */ 1500 #define TCPWM0_GRP0_CNT8 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[8]) /* 0x40380400 */ 1501 #define TCPWM0_GRP0_CNT9 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[9]) /* 0x40380480 */ 1502 #define TCPWM0_GRP0_CNT10 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[10]) /* 0x40380500 */ 1503 #define TCPWM0_GRP0_CNT11 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[11]) /* 0x40380580 */ 1504 #define TCPWM0_GRP0_CNT12 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[12]) /* 0x40380600 */ 1505 #define TCPWM0_GRP0_CNT13 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[13]) /* 0x40380680 */ 1506 #define TCPWM0_GRP0_CNT14 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[14]) /* 0x40380700 */ 1507 #define TCPWM0_GRP0_CNT15 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[15]) /* 0x40380780 */ 1508 #define TCPWM0_GRP0_CNT16 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[16]) /* 0x40380800 */ 1509 #define TCPWM0_GRP0_CNT17 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[17]) /* 0x40380880 */ 1510 #define TCPWM0_GRP0_CNT18 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[18]) /* 0x40380900 */ 1511 #define TCPWM0_GRP0_CNT19 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[19]) /* 0x40380980 */ 1512 #define TCPWM0_GRP0_CNT20 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[20]) /* 0x40380A00 */ 1513 #define TCPWM0_GRP0_CNT21 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[21]) /* 0x40380A80 */ 1514 #define TCPWM0_GRP0_CNT22 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[22]) /* 0x40380B00 */ 1515 #define TCPWM0_GRP0_CNT23 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[23]) /* 0x40380B80 */ 1516 #define TCPWM0_GRP0_CNT24 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[24]) /* 0x40380C00 */ 1517 #define TCPWM0_GRP0_CNT25 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[25]) /* 0x40380C80 */ 1518 #define TCPWM0_GRP0_CNT26 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[26]) /* 0x40380D00 */ 1519 #define TCPWM0_GRP0_CNT27 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[27]) /* 0x40380D80 */ 1520 #define TCPWM0_GRP0_CNT28 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[28]) /* 0x40380E00 */ 1521 #define TCPWM0_GRP0_CNT29 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[29]) /* 0x40380E80 */ 1522 #define TCPWM0_GRP0_CNT30 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[30]) /* 0x40380F00 */ 1523 #define TCPWM0_GRP0_CNT31 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[31]) /* 0x40380F80 */ 1524 #define TCPWM0_GRP0_CNT32 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[32]) /* 0x40381000 */ 1525 #define TCPWM0_GRP0_CNT33 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[33]) /* 0x40381080 */ 1526 #define TCPWM0_GRP0_CNT34 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[34]) /* 0x40381100 */ 1527 #define TCPWM0_GRP0_CNT35 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[35]) /* 0x40381180 */ 1528 #define TCPWM0_GRP0_CNT36 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[36]) /* 0x40381200 */ 1529 #define TCPWM0_GRP0_CNT37 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[37]) /* 0x40381280 */ 1530 #define TCPWM0_GRP0_CNT38 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[38]) /* 0x40381300 */ 1531 #define TCPWM0_GRP0_CNT39 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[39]) /* 0x40381380 */ 1532 #define TCPWM0_GRP0_CNT40 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[40]) /* 0x40381400 */ 1533 #define TCPWM0_GRP0_CNT41 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[41]) /* 0x40381480 */ 1534 #define TCPWM0_GRP0_CNT42 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[42]) /* 0x40381500 */ 1535 #define TCPWM0_GRP0_CNT43 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[43]) /* 0x40381580 */ 1536 #define TCPWM0_GRP0_CNT44 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[44]) /* 0x40381600 */ 1537 #define TCPWM0_GRP0_CNT45 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[45]) /* 0x40381680 */ 1538 #define TCPWM0_GRP0_CNT46 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[46]) /* 0x40381700 */ 1539 #define TCPWM0_GRP0_CNT47 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[47]) /* 0x40381780 */ 1540 #define TCPWM0_GRP0_CNT48 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[48]) /* 0x40381800 */ 1541 #define TCPWM0_GRP0_CNT49 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[49]) /* 0x40381880 */ 1542 #define TCPWM0_GRP0_CNT50 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[50]) /* 0x40381900 */ 1543 #define TCPWM0_GRP0_CNT51 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[51]) /* 0x40381980 */ 1544 #define TCPWM0_GRP0_CNT52 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[52]) /* 0x40381A00 */ 1545 #define TCPWM0_GRP0_CNT53 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[53]) /* 0x40381A80 */ 1546 #define TCPWM0_GRP0_CNT54 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[54]) /* 0x40381B00 */ 1547 #define TCPWM0_GRP0_CNT55 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[55]) /* 0x40381B80 */ 1548 #define TCPWM0_GRP0_CNT56 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[56]) /* 0x40381C00 */ 1549 #define TCPWM0_GRP0_CNT57 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[57]) /* 0x40381C80 */ 1550 #define TCPWM0_GRP0_CNT58 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[58]) /* 0x40381D00 */ 1551 #define TCPWM0_GRP0_CNT59 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[59]) /* 0x40381D80 */ 1552 #define TCPWM0_GRP0_CNT60 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[60]) /* 0x40381E00 */ 1553 #define TCPWM0_GRP0_CNT61 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[61]) /* 0x40381E80 */ 1554 #define TCPWM0_GRP0_CNT62 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[62]) /* 0x40381F00 */ 1555 #define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ 1556 #define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ 1557 #define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ 1558 #define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ 1559 #define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ 1560 #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ 1561 #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ 1562 #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ 1563 #define TCPWM0_GRP1_CNT8 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[8]) /* 0x40388400 */ 1564 #define TCPWM0_GRP1_CNT9 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[9]) /* 0x40388480 */ 1565 #define TCPWM0_GRP1_CNT10 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[10]) /* 0x40388500 */ 1566 #define TCPWM0_GRP1_CNT11 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[11]) /* 0x40388580 */ 1567 #define TCPWM0_GRP2_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[2].CNT[0]) /* 0x40390000 */ 1568 #define TCPWM0_GRP2_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[2].CNT[1]) /* 0x40390080 */ 1569 #define TCPWM0_GRP2_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[2].CNT[2]) /* 0x40390100 */ 1570 #define TCPWM0_GRP2_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[2].CNT[3]) /* 0x40390180 */ 1571 1572 /******************************************************************************* 1573 * EVTGEN 1574 *******************************************************************************/ 1575 1576 #define EVTGEN0_BASE 0x403F0000UL 1577 #define EVTGEN0 ((EVTGEN_Type*) EVTGEN0_BASE) /* 0x403F0000 */ 1578 #define EVTGEN0_COMP_STRUCT0 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[0]) /* 0x403F0800 */ 1579 #define EVTGEN0_COMP_STRUCT1 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[1]) /* 0x403F0820 */ 1580 #define EVTGEN0_COMP_STRUCT2 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[2]) /* 0x403F0840 */ 1581 #define EVTGEN0_COMP_STRUCT3 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[3]) /* 0x403F0860 */ 1582 #define EVTGEN0_COMP_STRUCT4 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[4]) /* 0x403F0880 */ 1583 #define EVTGEN0_COMP_STRUCT5 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[5]) /* 0x403F08A0 */ 1584 #define EVTGEN0_COMP_STRUCT6 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[6]) /* 0x403F08C0 */ 1585 #define EVTGEN0_COMP_STRUCT7 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[7]) /* 0x403F08E0 */ 1586 #define EVTGEN0_COMP_STRUCT8 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[8]) /* 0x403F0900 */ 1587 #define EVTGEN0_COMP_STRUCT9 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[9]) /* 0x403F0920 */ 1588 #define EVTGEN0_COMP_STRUCT10 ((EVTGEN_COMP_STRUCT_Type*) &EVTGEN0->COMP_STRUCT[10]) /* 0x403F0940 */ 1589 1590 /******************************************************************************* 1591 * LIN 1592 *******************************************************************************/ 1593 1594 #define LIN0_BASE 0x40500000UL 1595 #define LIN0 ((LIN_Type*) LIN0_BASE) /* 0x40500000 */ 1596 #define LIN0_CH0 ((LIN_CH_Type*) &LIN0->CH[0]) /* 0x40508000 */ 1597 #define LIN0_CH1 ((LIN_CH_Type*) &LIN0->CH[1]) /* 0x40508100 */ 1598 #define LIN0_CH2 ((LIN_CH_Type*) &LIN0->CH[2]) /* 0x40508200 */ 1599 #define LIN0_CH3 ((LIN_CH_Type*) &LIN0->CH[3]) /* 0x40508300 */ 1600 #define LIN0_CH4 ((LIN_CH_Type*) &LIN0->CH[4]) /* 0x40508400 */ 1601 #define LIN0_CH7 ((LIN_CH_Type*) &LIN0->CH[7]) /* 0x40508700 */ 1602 1603 /******************************************************************************* 1604 * CANFD 1605 *******************************************************************************/ 1606 1607 #define CANFD0_BASE 0x40520000UL 1608 #define CANFD1_BASE 0x40540000UL 1609 #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ 1610 #define CANFD1 ((CANFD_Type*) CANFD1_BASE) /* 0x40540000 */ 1611 #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ 1612 #define CANFD0_CH1 ((CANFD_CH_Type*) &CANFD0->CH[1]) /* 0x40520200 */ 1613 #define CANFD0_CH2 ((CANFD_CH_Type*) &CANFD0->CH[2]) /* 0x40520400 */ 1614 #define CANFD1_CH0 ((CANFD_CH_Type*) &CANFD1->CH[0]) /* 0x40540000 */ 1615 #define CANFD1_CH2 ((CANFD_CH_Type*) &CANFD1->CH[2]) /* 0x40540400 */ 1616 #define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ 1617 #define CANFD0_CH1_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[1].M_TTCAN) /* 0x40520200 */ 1618 #define CANFD0_CH2_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[2].M_TTCAN) /* 0x40520400 */ 1619 #define CANFD1_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD1->CH[0].M_TTCAN) /* 0x40540000 */ 1620 #define CANFD1_CH2_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD1->CH[2].M_TTCAN) /* 0x40540400 */ 1621 1622 /******************************************************************************* 1623 * SCB 1624 *******************************************************************************/ 1625 1626 #define SCB0_BASE 0x40600000UL 1627 #define SCB1_BASE 0x40610000UL 1628 #define SCB2_BASE 0x40620000UL 1629 #define SCB3_BASE 0x40630000UL 1630 #define SCB4_BASE 0x40640000UL 1631 #define SCB5_BASE 0x40650000UL 1632 #define SCB7_BASE 0x40670000UL 1633 #define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ 1634 #define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ 1635 #define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ 1636 #define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ 1637 #define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ 1638 #define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ 1639 #define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ 1640 1641 /******************************************************************************* 1642 * PASS 1643 *******************************************************************************/ 1644 1645 #define PASS0_BASE 0x40900000UL 1646 #define PASS0 ((PASS_Type*) PASS0_BASE) /* 0x40900000 */ 1647 #define PASS0_SAR0 ((PASS_SAR_Type*) &PASS0->SAR[0]) /* 0x40900000 */ 1648 #define PASS0_SAR1 ((PASS_SAR_Type*) &PASS0->SAR[1]) /* 0x40901000 */ 1649 #define PASS0_SAR2 ((PASS_SAR_Type*) &PASS0->SAR[2]) /* 0x40902000 */ 1650 #define PASS0_SAR0_CH0 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[0]) /* 0x40900800 */ 1651 #define PASS0_SAR0_CH1 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[1]) /* 0x40900840 */ 1652 #define PASS0_SAR0_CH2 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[2]) /* 0x40900880 */ 1653 #define PASS0_SAR0_CH3 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[3]) /* 0x409008C0 */ 1654 #define PASS0_SAR0_CH4 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[4]) /* 0x40900900 */ 1655 #define PASS0_SAR0_CH5 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[5]) /* 0x40900940 */ 1656 #define PASS0_SAR0_CH6 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[6]) /* 0x40900980 */ 1657 #define PASS0_SAR0_CH7 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[7]) /* 0x409009C0 */ 1658 #define PASS0_SAR0_CH8 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[8]) /* 0x40900A00 */ 1659 #define PASS0_SAR0_CH9 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[9]) /* 0x40900A40 */ 1660 #define PASS0_SAR0_CH10 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[10]) /* 0x40900A80 */ 1661 #define PASS0_SAR0_CH11 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[11]) /* 0x40900AC0 */ 1662 #define PASS0_SAR0_CH12 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[12]) /* 0x40900B00 */ 1663 #define PASS0_SAR0_CH13 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[13]) /* 0x40900B40 */ 1664 #define PASS0_SAR0_CH14 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[14]) /* 0x40900B80 */ 1665 #define PASS0_SAR0_CH15 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[15]) /* 0x40900BC0 */ 1666 #define PASS0_SAR0_CH16 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[16]) /* 0x40900C00 */ 1667 #define PASS0_SAR0_CH17 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[17]) /* 0x40900C40 */ 1668 #define PASS0_SAR0_CH18 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[18]) /* 0x40900C80 */ 1669 #define PASS0_SAR0_CH19 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[19]) /* 0x40900CC0 */ 1670 #define PASS0_SAR0_CH20 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[20]) /* 0x40900D00 */ 1671 #define PASS0_SAR0_CH21 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[21]) /* 0x40900D40 */ 1672 #define PASS0_SAR0_CH22 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[22]) /* 0x40900D80 */ 1673 #define PASS0_SAR0_CH23 ((PASS_SAR_CH_Type*) &PASS0->SAR[0].CH[23]) /* 0x40900DC0 */ 1674 #define PASS0_SAR1_CH0 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[0]) /* 0x40901800 */ 1675 #define PASS0_SAR1_CH1 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[1]) /* 0x40901840 */ 1676 #define PASS0_SAR1_CH2 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[2]) /* 0x40901880 */ 1677 #define PASS0_SAR1_CH3 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[3]) /* 0x409018C0 */ 1678 #define PASS0_SAR1_CH4 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[4]) /* 0x40901900 */ 1679 #define PASS0_SAR1_CH5 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[5]) /* 0x40901940 */ 1680 #define PASS0_SAR1_CH6 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[6]) /* 0x40901980 */ 1681 #define PASS0_SAR1_CH7 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[7]) /* 0x409019C0 */ 1682 #define PASS0_SAR1_CH8 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[8]) /* 0x40901A00 */ 1683 #define PASS0_SAR1_CH9 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[9]) /* 0x40901A40 */ 1684 #define PASS0_SAR1_CH10 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[10]) /* 0x40901A80 */ 1685 #define PASS0_SAR1_CH11 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[11]) /* 0x40901AC0 */ 1686 #define PASS0_SAR1_CH12 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[12]) /* 0x40901B00 */ 1687 #define PASS0_SAR1_CH13 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[13]) /* 0x40901B40 */ 1688 #define PASS0_SAR1_CH14 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[14]) /* 0x40901B80 */ 1689 #define PASS0_SAR1_CH15 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[15]) /* 0x40901BC0 */ 1690 #define PASS0_SAR1_CH16 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[16]) /* 0x40901C00 */ 1691 #define PASS0_SAR1_CH17 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[17]) /* 0x40901C40 */ 1692 #define PASS0_SAR1_CH18 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[18]) /* 0x40901C80 */ 1693 #define PASS0_SAR1_CH19 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[19]) /* 0x40901CC0 */ 1694 #define PASS0_SAR1_CH20 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[20]) /* 0x40901D00 */ 1695 #define PASS0_SAR1_CH21 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[21]) /* 0x40901D40 */ 1696 #define PASS0_SAR1_CH22 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[22]) /* 0x40901D80 */ 1697 #define PASS0_SAR1_CH23 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[23]) /* 0x40901DC0 */ 1698 #define PASS0_SAR1_CH24 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[24]) /* 0x40901E00 */ 1699 #define PASS0_SAR1_CH25 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[25]) /* 0x40901E40 */ 1700 #define PASS0_SAR1_CH26 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[26]) /* 0x40901E80 */ 1701 #define PASS0_SAR1_CH27 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[27]) /* 0x40901EC0 */ 1702 #define PASS0_SAR1_CH28 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[28]) /* 0x40901F00 */ 1703 #define PASS0_SAR1_CH29 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[29]) /* 0x40901F40 */ 1704 #define PASS0_SAR1_CH30 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[30]) /* 0x40901F80 */ 1705 #define PASS0_SAR1_CH31 ((PASS_SAR_CH_Type*) &PASS0->SAR[1].CH[31]) /* 0x40901FC0 */ 1706 #define PASS0_SAR2_CH0 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[0]) /* 0x40902800 */ 1707 #define PASS0_SAR2_CH1 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[1]) /* 0x40902840 */ 1708 #define PASS0_SAR2_CH2 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[2]) /* 0x40902880 */ 1709 #define PASS0_SAR2_CH3 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[3]) /* 0x409028C0 */ 1710 #define PASS0_SAR2_CH4 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[4]) /* 0x40902900 */ 1711 #define PASS0_SAR2_CH5 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[5]) /* 0x40902940 */ 1712 #define PASS0_SAR2_CH6 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[6]) /* 0x40902980 */ 1713 #define PASS0_SAR2_CH7 ((PASS_SAR_CH_Type*) &PASS0->SAR[2].CH[7]) /* 0x409029C0 */ 1714 #define PASS0_EPASS_MMIO ((PASS_EPASS_MMIO_Type*) &PASS0->EPASS_MMIO) /* 0x409F0000 */ 1715 1716 /** \} CYT2B73BAE */ 1717 1718 #endif /* _CYT2B73BAE_H_ */ 1719 1720 1721 /* [] END OF FILE */ 1722
