1 /***************************************************************************//** 2 * \file cyip_smif_v4.h 3 * 4 * \brief 5 * SMIF IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SMIF_V4_H_ 28 #define _CYIP_SMIF_V4_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SMIF 34 *******************************************************************************/ 35 36 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SECTION_SIZE 0x00000100UL 37 #define SMIF_SMIF_BRIDGE_SECTION_SIZE 0x00010000UL 38 #define SMIF_CORE_SMIF_CRYPTO_SECTION_SIZE 0x00000080UL 39 #define SMIF_CORE_DEVICE_SECTION_SIZE 0x00000080UL 40 #define SMIF_CORE_SECTION_SIZE 0x00010000UL 41 #define SMIF_SECTION_SIZE 0x00040000UL 42 43 /** 44 * \brief 'Remap regions' which define how XIP accesses can be remapped into SMIF physical spaces (SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION) 45 */ 46 typedef struct { 47 __IOM uint32_t CTL; /*!< 0x00000000 Control bits for remap region */ 48 __IM uint32_t RESERVED[3]; 49 __IOM uint32_t ADDR; /*!< 0x00000010 Base address of remap region */ 50 __IOM uint32_t MASK; /*!< 0x00000014 Mask value to be paired with ADDR */ 51 __IOM uint32_t SMIF0_REMAP; /*!< 0x00000018 Base address for remaps into SMIF0 physical memory space */ 52 __IOM uint32_t SMIF1_REMAP; /*!< 0x0000001C Base address for remaps into SMIF1 physical memory space */ 53 __IM uint32_t RESERVED1[56]; 54 } SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_Type; /*!< Size = 256 (0x100) */ 55 56 /** 57 * \brief AXI/AHB interleaving and FOTA bridge (SMIF_SMIF_BRIDGE) 58 */ 59 typedef struct { 60 __IOM uint32_t CTL; /*!< 0x00000000 Global control registers for the bridge */ 61 __IM uint32_t RESERVED[1023]; 62 SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_Type SMIF_REMAP_REGION[8]; /*!< 0x00001000 'Remap regions' which define how XIP accesses can be remapped 63 into SMIF physical spaces */ 64 __IM uint32_t RESERVED1[14848]; 65 } SMIF_SMIF_BRIDGE_Type; /*!< Size = 65536 (0x10000) */ 66 67 /** 68 * \brief Cryptography registers (one set for each key) (SMIF_CORE_SMIF_CRYPTO) 69 */ 70 typedef struct { 71 __IOM uint32_t CRYPTO_CMD; /*!< 0x00000000 Cryptography command */ 72 __IOM uint32_t CRYPTO_ADDR; /*!< 0x00000004 Cryptography base address */ 73 __IOM uint32_t CRYPTO_MASK; /*!< 0x00000008 Cryptography mask */ 74 __IOM uint32_t CRYPTO_SUBREGION; /*!< 0x0000000C Cryptography subregion disable */ 75 __IM uint32_t RESERVED[4]; 76 __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000020 Cryptography input 0 */ 77 __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000024 Cryptography input 1 */ 78 __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000028 Cryptography input 2 */ 79 __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000002C Cryptography input 3 */ 80 __IM uint32_t RESERVED1[4]; 81 __OM uint32_t CRYPTO_KEY0; /*!< 0x00000040 Cryptography key 0 */ 82 __OM uint32_t CRYPTO_KEY1; /*!< 0x00000044 Cryptography key 1 */ 83 __OM uint32_t CRYPTO_KEY2; /*!< 0x00000048 Cryptography key 2 */ 84 __OM uint32_t CRYPTO_KEY3; /*!< 0x0000004C Cryptography key 3 */ 85 __IM uint32_t RESERVED2[4]; 86 __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000060 Cryptography output 0 */ 87 __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000064 Cryptography output 1 */ 88 __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000068 Cryptography output 2 */ 89 __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000006C Cryptography output 3 */ 90 __IM uint32_t RESERVED3[4]; 91 } SMIF_CORE_SMIF_CRYPTO_Type; /*!< Size = 128 (0x80) */ 92 93 /** 94 * \brief Device (only used for XIP acceses) (SMIF_CORE_DEVICE) 95 */ 96 typedef struct { 97 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 98 __IM uint32_t RESERVED; 99 __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */ 100 __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */ 101 __IM uint32_t RESERVED1[4]; 102 __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */ 103 __IM uint32_t RESERVED2; 104 __IOM uint32_t RX_CAPTURE_CONFIG; /*!< 0x00000028 RX capture configuration */ 105 __IM uint32_t RESERVED3; 106 __IM uint32_t RD_STATUS; /*!< 0x00000030 Read status */ 107 __IM uint32_t RESERVED4[3]; 108 __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */ 109 __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */ 110 __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */ 111 __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */ 112 __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */ 113 __IOM uint32_t RD_CRC_CTL; /*!< 0x00000054 Read Bus CRC control */ 114 __IOM uint32_t RD_BOUND_CTL; /*!< 0x00000058 Read boundary control */ 115 __IM uint32_t RESERVED5; 116 __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */ 117 __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */ 118 __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */ 119 __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */ 120 __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */ 121 __IOM uint32_t WR_CRC_CTL; /*!< 0x00000074 Write Bus CRC control */ 122 __IM uint32_t RESERVED6[2]; 123 } SMIF_CORE_DEVICE_Type; /*!< Size = 128 (0x80) */ 124 125 /** 126 * \brief Serial Memory Interface (SMIF_CORE) 127 */ 128 typedef struct { 129 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 130 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 131 __IOM uint32_t CTL2; /*!< 0x00000008 Control 2 */ 132 __IM uint32_t RESERVED; 133 __IM uint32_t DLP_DELAY_TAP_SEL0; /*!< 0x00000010 DLP Delay Tap Select Register 0 */ 134 __IM uint32_t DLP_DELAY_TAP_SEL1; /*!< 0x00000014 DLP Delay Tap Select Register 1 */ 135 __IOM uint32_t DLP_CTL; /*!< 0x00000018 DLP Control Register */ 136 __IM uint32_t RESERVED1; 137 __IM uint32_t DLP_STATUS0; /*!< 0x00000020 DLP Status Register 0 */ 138 __IM uint32_t DLP_STATUS1; /*!< 0x00000024 DLP Status Register 1 */ 139 __IM uint32_t RESERVED2[7]; 140 __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */ 141 __IM uint32_t TX_CMD_MMIO_FIFO_STATUS; /*!< 0x00000048 Transmitter command MMIO FIFO status */ 142 __IM uint32_t RESERVED3; 143 __OM uint32_t TX_CMD_MMIO_FIFO_WR; /*!< 0x00000050 Transmitter command MMIO FIFO write */ 144 __IM uint32_t RESERVED4[11]; 145 __IOM uint32_t TX_DATA_MMIO_FIFO_CTL; /*!< 0x00000080 Transmitter data MMIO FIFO control */ 146 __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */ 147 __IM uint32_t TX_DATA_MMIO_FIFO_STATUS; /*!< 0x00000088 Transmitter data MMIO FIFO status */ 148 __IM uint32_t RESERVED5; 149 __OM uint32_t TX_DATA_MMIO_FIFO_WR1; /*!< 0x00000090 Transmitter data MMIO FIFO write */ 150 __OM uint32_t TX_DATA_MMIO_FIFO_WR2; /*!< 0x00000094 Transmitter data MMIO FIFO write */ 151 __OM uint32_t TX_DATA_MMIO_FIFO_WR4; /*!< 0x00000098 Transmitter data MMIO FIFO write */ 152 __OM uint32_t TX_DATA_MMIO_FIFO_WR1ODD; /*!< 0x0000009C Transmitter data MMIO FIFO write */ 153 __IM uint32_t RESERVED6[8]; 154 __IOM uint32_t RX_DATA_MMIO_FIFO_CTL; /*!< 0x000000C0 Receiver data MMIO FIFO control */ 155 __IM uint32_t RX_DATA_MMIO_FIFO_STATUS; /*!< 0x000000C4 Receiver data MMIO FIFO status */ 156 __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C8 Receiver data FIFO status */ 157 __IM uint32_t RESERVED7; 158 __IM uint32_t RX_DATA_MMIO_FIFO_RD1; /*!< 0x000000D0 Receiver data MMIO FIFO read */ 159 __IM uint32_t RX_DATA_MMIO_FIFO_RD2; /*!< 0x000000D4 Receiver data MMIO FIFO read */ 160 __IM uint32_t RX_DATA_MMIO_FIFO_RD4; /*!< 0x000000D8 Receiver data MMIO FIFO read */ 161 __IM uint32_t RESERVED8; 162 __IM uint32_t RX_DATA_MMIO_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data MMIO FIFO silent read */ 163 __IM uint32_t RESERVED9[7]; 164 __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */ 165 __IM uint32_t RESERVED10; 166 __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */ 167 __IM uint32_t RESERVED11[29]; 168 __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */ 169 __IM uint32_t RESERVED12; 170 __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */ 171 __IM uint32_t RESERVED13[29]; 172 SMIF_CORE_SMIF_CRYPTO_Type SMIF_CRYPTO_BLOCK[8]; /*!< 0x00000200 Cryptography registers (one set for each key) */ 173 __IOM uint32_t CRC_CMD; /*!< 0x00000600 CRC Command */ 174 __IM uint32_t RESERVED14[7]; 175 __IOM uint32_t CRC_INPUT0; /*!< 0x00000620 CRC input 0 */ 176 __IOM uint32_t CRC_INPUT1; /*!< 0x00000624 CRC input 1 */ 177 __IM uint32_t RESERVED15[6]; 178 __IM uint32_t CRC_OUTPUT; /*!< 0x00000640 CRC output */ 179 __IM uint32_t RESERVED16[95]; 180 __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ 181 __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ 182 __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ 183 __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ 184 __IM uint32_t RESERVED17[12]; 185 SMIF_CORE_DEVICE_Type DEVICE[4]; /*!< 0x00000800 Device (only used for XIP acceses) */ 186 __IM uint32_t RESERVED18[15744]; 187 } SMIF_CORE_Type; /*!< Size = 65536 (0x10000) */ 188 189 /** 190 * \brief SMIF subsystem (bridge + 2 core SMIFs, OR no bridge and 1 core SMIF) (SMIF) 191 */ 192 typedef struct { 193 SMIF_SMIF_BRIDGE_Type SMIF_BRIDGE; /*!< 0x00000000 AXI/AHB interleaving and FOTA bridge */ 194 __IM uint32_t RESERVED[16384]; 195 SMIF_CORE_Type CORE[2]; /*!< 0x00020000 Serial Memory Interface */ 196 } SMIF_STRUCT_Type; /*!< Size = 262144 (0x40000) */ 197 198 199 /* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.CTL */ 200 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_USE_SMIF_Pos 0UL 201 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_USE_SMIF_Msk 0x3UL 202 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_INTLV_STEP_SIZE_Pos 16UL 203 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_INTLV_STEP_SIZE_Msk 0x70000UL 204 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_SMIF_SPACE_Pos 31UL 205 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_SMIF_SPACE_Msk 0x80000000UL 206 /* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.ADDR */ 207 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_ADDR_ADDR_Pos 20UL 208 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_ADDR_ADDR_Msk 0x1FF00000UL 209 /* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.MASK */ 210 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_MASK_MASK_Pos 20UL 211 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_MASK_MASK_Msk 0x1FF00000UL 212 /* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.SMIF0_REMAP */ 213 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF0_REMAP_SMIF0_REMAP_Pos 20UL 214 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF0_REMAP_SMIF0_REMAP_Msk 0x1FF00000UL 215 /* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.SMIF1_REMAP */ 216 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF1_REMAP_SMIF1_REMAP_Pos 20UL 217 #define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF1_REMAP_SMIF1_REMAP_Msk 0x1FF00000UL 218 219 220 /* SMIF_SMIF_BRIDGE.CTL */ 221 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF0_Pos 0UL 222 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF0_Msk 0x1UL 223 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF1_Pos 1UL 224 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF1_Msk 0x2UL 225 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF0_Pos 8UL 226 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF0_Msk 0x100UL 227 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF1_Pos 9UL 228 #define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF1_Msk 0x200UL 229 #define SMIF_SMIF_BRIDGE_CTL_ENABLED_Pos 31UL 230 #define SMIF_SMIF_BRIDGE_CTL_ENABLED_Msk 0x80000000UL 231 232 233 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_CMD */ 234 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Pos 0UL 235 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Msk 0x1UL 236 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_ADDR */ 237 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_ADDR_ADDR_Pos 8UL 238 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_ADDR_ADDR_Msk 0xFFFFFF00UL 239 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_MASK */ 240 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_MASK_MASK_Pos 8UL 241 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_MASK_MASK_Msk 0xFFFFFF00UL 242 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_SUBREGION */ 243 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_SUBREGION_SUBREGION_DISABLE_Pos 0UL 244 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_SUBREGION_SUBREGION_DISABLE_Msk 0xFFUL 245 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT0 */ 246 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_LSB_Pos 0UL 247 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_LSB_Msk 0xFUL 248 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_MSB_Pos 4UL 249 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_MSB_Msk 0xFFFFFFF0UL 250 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT1 */ 251 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT1_INPUT_Pos 0UL 252 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL 253 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT2 */ 254 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT2_INPUT_Pos 0UL 255 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL 256 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT3 */ 257 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT3_INPUT_Pos 0UL 258 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL 259 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY0 */ 260 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY0_KEY_Pos 0UL 261 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL 262 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY1 */ 263 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY1_KEY_Pos 0UL 264 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL 265 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY2 */ 266 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY2_KEY_Pos 0UL 267 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL 268 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY3 */ 269 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY3_KEY_Pos 0UL 270 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL 271 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT0 */ 272 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL 273 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL 274 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT1 */ 275 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL 276 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL 277 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT2 */ 278 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL 279 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL 280 /* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT3 */ 281 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL 282 #define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL 283 284 285 /* SMIF_CORE_DEVICE.CTL */ 286 #define SMIF_CORE_DEVICE_CTL_WR_EN_Pos 0UL 287 #define SMIF_CORE_DEVICE_CTL_WR_EN_Msk 0x1UL 288 #define SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Pos 4UL 289 #define SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Msk 0x10UL 290 #define SMIF_CORE_DEVICE_CTL_DATA_SEL_Pos 8UL 291 #define SMIF_CORE_DEVICE_CTL_DATA_SEL_Msk 0x300UL 292 #define SMIF_CORE_DEVICE_CTL_MERGE_TIMEOUT_Pos 12UL 293 #define SMIF_CORE_DEVICE_CTL_MERGE_TIMEOUT_Msk 0x7000UL 294 #define SMIF_CORE_DEVICE_CTL_MERGE_EN_Pos 15UL 295 #define SMIF_CORE_DEVICE_CTL_MERGE_EN_Msk 0x8000UL 296 #define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_Pos 16UL 297 #define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_Msk 0x3FFF0000UL 298 #define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_EN_Pos 30UL 299 #define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_EN_Msk 0x40000000UL 300 #define SMIF_CORE_DEVICE_CTL_ENABLED_Pos 31UL 301 #define SMIF_CORE_DEVICE_CTL_ENABLED_Msk 0x80000000UL 302 /* SMIF_CORE_DEVICE.ADDR */ 303 #define SMIF_CORE_DEVICE_ADDR_ADDR_Pos 8UL 304 #define SMIF_CORE_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL 305 /* SMIF_CORE_DEVICE.MASK */ 306 #define SMIF_CORE_DEVICE_MASK_MASK_Pos 8UL 307 #define SMIF_CORE_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL 308 /* SMIF_CORE_DEVICE.ADDR_CTL */ 309 #define SMIF_CORE_DEVICE_ADDR_CTL_SIZE3_Pos 0UL 310 #define SMIF_CORE_DEVICE_ADDR_CTL_SIZE3_Msk 0x7UL 311 #define SMIF_CORE_DEVICE_ADDR_CTL_DIV2_Pos 8UL 312 #define SMIF_CORE_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL 313 /* SMIF_CORE_DEVICE.RX_CAPTURE_CONFIG */ 314 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_NEG_SDL_TAP_SEL_Pos 0UL 315 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_NEG_SDL_TAP_SEL_Msk 0xFUL 316 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_POS_SDL_TAP_SEL_Pos 4UL 317 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_POS_SDL_TAP_SEL_Msk 0xF0UL 318 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_PIPELINE_NEG_DAT_Pos 16UL 319 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_PIPELINE_NEG_DAT_Msk 0x10000UL 320 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_SWAP_BYTES_Pos 17UL 321 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_SWAP_BYTES_Msk 0x20000UL 322 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_PIPELINE_POS_DAT_Pos 24UL 323 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_PIPELINE_POS_DAT_Msk 0x1000000UL 324 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_SWAP_BYTES_Pos 25UL 325 #define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_SWAP_BYTES_Msk 0x2000000UL 326 /* SMIF_CORE_DEVICE.RD_STATUS */ 327 #define SMIF_CORE_DEVICE_RD_STATUS_FS_STATUS_Pos 0UL 328 #define SMIF_CORE_DEVICE_RD_STATUS_FS_STATUS_Msk 0xFFUL 329 /* SMIF_CORE_DEVICE.RD_CMD_CTL */ 330 #define SMIF_CORE_DEVICE_RD_CMD_CTL_CODE_Pos 0UL 331 #define SMIF_CORE_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL 332 #define SMIF_CORE_DEVICE_RD_CMD_CTL_CODEH_Pos 8UL 333 #define SMIF_CORE_DEVICE_RD_CMD_CTL_CODEH_Msk 0xFF00UL 334 #define SMIF_CORE_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL 335 #define SMIF_CORE_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL 336 #define SMIF_CORE_DEVICE_RD_CMD_CTL_DDR_MODE_Pos 18UL 337 #define SMIF_CORE_DEVICE_RD_CMD_CTL_DDR_MODE_Msk 0x40000UL 338 #define SMIF_CORE_DEVICE_RD_CMD_CTL_PRESENT2_Pos 30UL 339 #define SMIF_CORE_DEVICE_RD_CMD_CTL_PRESENT2_Msk 0xC0000000UL 340 /* SMIF_CORE_DEVICE.RD_ADDR_CTL */ 341 #define SMIF_CORE_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL 342 #define SMIF_CORE_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL 343 #define SMIF_CORE_DEVICE_RD_ADDR_CTL_DDR_MODE_Pos 18UL 344 #define SMIF_CORE_DEVICE_RD_ADDR_CTL_DDR_MODE_Msk 0x40000UL 345 /* SMIF_CORE_DEVICE.RD_MODE_CTL */ 346 #define SMIF_CORE_DEVICE_RD_MODE_CTL_CODE_Pos 0UL 347 #define SMIF_CORE_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL 348 #define SMIF_CORE_DEVICE_RD_MODE_CTL_CODEH_Pos 8UL 349 #define SMIF_CORE_DEVICE_RD_MODE_CTL_CODEH_Msk 0xFF00UL 350 #define SMIF_CORE_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL 351 #define SMIF_CORE_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL 352 #define SMIF_CORE_DEVICE_RD_MODE_CTL_DDR_MODE_Pos 18UL 353 #define SMIF_CORE_DEVICE_RD_MODE_CTL_DDR_MODE_Msk 0x40000UL 354 #define SMIF_CORE_DEVICE_RD_MODE_CTL_PRESENT2_Pos 30UL 355 #define SMIF_CORE_DEVICE_RD_MODE_CTL_PRESENT2_Msk 0xC0000000UL 356 /* SMIF_CORE_DEVICE.RD_DUMMY_CTL */ 357 #define SMIF_CORE_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL 358 #define SMIF_CORE_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL 359 #define SMIF_CORE_DEVICE_RD_DUMMY_CTL_PRESENT2_Pos 30UL 360 #define SMIF_CORE_DEVICE_RD_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL 361 /* SMIF_CORE_DEVICE.RD_DATA_CTL */ 362 #define SMIF_CORE_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL 363 #define SMIF_CORE_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL 364 #define SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Pos 18UL 365 #define SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Msk 0x40000UL 366 /* SMIF_CORE_DEVICE.RD_CRC_CTL */ 367 #define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Pos 0UL 368 #define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Msk 0xFFUL 369 #define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Pos 8UL 370 #define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Msk 0xFF00UL 371 #define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL 372 #define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL 373 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL 374 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL 375 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL 376 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL 377 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL 378 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL 379 #define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Pos 28UL 380 #define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Msk 0x10000000UL 381 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL 382 #define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL 383 #define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL 384 #define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL 385 /* SMIF_CORE_DEVICE.RD_BOUND_CTL */ 386 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SIZE5_Pos 0UL 387 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SIZE5_Msk 0x1FUL 388 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Pos 16UL 389 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Msk 0x30000UL 390 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Pos 20UL 391 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Msk 0x300000UL 392 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Pos 28UL 393 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Msk 0x10000000UL 394 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_PRESENT_Pos 31UL 395 #define SMIF_CORE_DEVICE_RD_BOUND_CTL_PRESENT_Msk 0x80000000UL 396 /* SMIF_CORE_DEVICE.WR_CMD_CTL */ 397 #define SMIF_CORE_DEVICE_WR_CMD_CTL_CODE_Pos 0UL 398 #define SMIF_CORE_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL 399 #define SMIF_CORE_DEVICE_WR_CMD_CTL_CODEH_Pos 8UL 400 #define SMIF_CORE_DEVICE_WR_CMD_CTL_CODEH_Msk 0xFF00UL 401 #define SMIF_CORE_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL 402 #define SMIF_CORE_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL 403 #define SMIF_CORE_DEVICE_WR_CMD_CTL_DDR_MODE_Pos 18UL 404 #define SMIF_CORE_DEVICE_WR_CMD_CTL_DDR_MODE_Msk 0x40000UL 405 #define SMIF_CORE_DEVICE_WR_CMD_CTL_PRESENT2_Pos 30UL 406 #define SMIF_CORE_DEVICE_WR_CMD_CTL_PRESENT2_Msk 0xC0000000UL 407 /* SMIF_CORE_DEVICE.WR_ADDR_CTL */ 408 #define SMIF_CORE_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL 409 #define SMIF_CORE_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL 410 #define SMIF_CORE_DEVICE_WR_ADDR_CTL_DDR_MODE_Pos 18UL 411 #define SMIF_CORE_DEVICE_WR_ADDR_CTL_DDR_MODE_Msk 0x40000UL 412 /* SMIF_CORE_DEVICE.WR_MODE_CTL */ 413 #define SMIF_CORE_DEVICE_WR_MODE_CTL_CODE_Pos 0UL 414 #define SMIF_CORE_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL 415 #define SMIF_CORE_DEVICE_WR_MODE_CTL_CODEH_Pos 8UL 416 #define SMIF_CORE_DEVICE_WR_MODE_CTL_CODEH_Msk 0xFF00UL 417 #define SMIF_CORE_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL 418 #define SMIF_CORE_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL 419 #define SMIF_CORE_DEVICE_WR_MODE_CTL_DDR_MODE_Pos 18UL 420 #define SMIF_CORE_DEVICE_WR_MODE_CTL_DDR_MODE_Msk 0x40000UL 421 #define SMIF_CORE_DEVICE_WR_MODE_CTL_PRESENT2_Pos 30UL 422 #define SMIF_CORE_DEVICE_WR_MODE_CTL_PRESENT2_Msk 0xC0000000UL 423 /* SMIF_CORE_DEVICE.WR_DUMMY_CTL */ 424 #define SMIF_CORE_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL 425 #define SMIF_CORE_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL 426 #define SMIF_CORE_DEVICE_WR_DUMMY_CTL_RWDS_EN_Pos 17UL 427 #define SMIF_CORE_DEVICE_WR_DUMMY_CTL_RWDS_EN_Msk 0x20000UL 428 #define SMIF_CORE_DEVICE_WR_DUMMY_CTL_PRESENT2_Pos 30UL 429 #define SMIF_CORE_DEVICE_WR_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL 430 /* SMIF_CORE_DEVICE.WR_DATA_CTL */ 431 #define SMIF_CORE_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL 432 #define SMIF_CORE_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL 433 #define SMIF_CORE_DEVICE_WR_DATA_CTL_DDR_MODE_Pos 18UL 434 #define SMIF_CORE_DEVICE_WR_DATA_CTL_DDR_MODE_Msk 0x40000UL 435 /* SMIF_CORE_DEVICE.WR_CRC_CTL */ 436 #define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL 437 #define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL 438 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL 439 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL 440 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL 441 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL 442 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL 443 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL 444 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL 445 #define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL 446 #define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL 447 #define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL 448 449 450 /* SMIF_CORE.CTL */ 451 #define SMIF_CORE_CTL_XIP_MODE_Pos 0UL 452 #define SMIF_CORE_CTL_XIP_MODE_Msk 0x1UL 453 #define SMIF_CORE_CTL_DESELECT_DELAY_Pos 16UL 454 #define SMIF_CORE_CTL_DESELECT_DELAY_Msk 0x70000UL 455 #define SMIF_CORE_CTL_SELECT_SETUP_DELAY_Pos 20UL 456 #define SMIF_CORE_CTL_SELECT_SETUP_DELAY_Msk 0x300000UL 457 #define SMIF_CORE_CTL_SELECT_HOLD_DELAY_Pos 22UL 458 #define SMIF_CORE_CTL_SELECT_HOLD_DELAY_Msk 0xC00000UL 459 #define SMIF_CORE_CTL_BLOCK_Pos 24UL 460 #define SMIF_CORE_CTL_BLOCK_Msk 0x1000000UL 461 #define SMIF_CORE_CTL_CLOCK_IF_SEL_Pos 25UL 462 #define SMIF_CORE_CTL_CLOCK_IF_SEL_Msk 0x2000000UL 463 #define SMIF_CORE_CTL_ENABLED_Pos 31UL 464 #define SMIF_CORE_CTL_ENABLED_Msk 0x80000000UL 465 /* SMIF_CORE.STATUS */ 466 #define SMIF_CORE_STATUS_DLL_LOCKED_Pos 0UL 467 #define SMIF_CORE_STATUS_DLL_LOCKED_Msk 0x1UL 468 #define SMIF_CORE_STATUS_BUSY_Pos 31UL 469 #define SMIF_CORE_STATUS_BUSY_Msk 0x80000000UL 470 /* SMIF_CORE.CTL2 */ 471 #define SMIF_CORE_CTL2_DLL_SPEED_MODE_Pos 0UL 472 #define SMIF_CORE_CTL2_DLL_SPEED_MODE_Msk 0x3UL 473 #define SMIF_CORE_CTL2_CLKOUT_DIV_Pos 4UL 474 #define SMIF_CORE_CTL2_CLKOUT_DIV_Msk 0x30UL 475 #define SMIF_CORE_CTL2_MDL_TAP_SEL_Pos 8UL 476 #define SMIF_CORE_CTL2_MDL_TAP_SEL_Msk 0xF00UL 477 #define SMIF_CORE_CTL2_RX_CAPTURE_MODE_Pos 20UL 478 #define SMIF_CORE_CTL2_RX_CAPTURE_MODE_Msk 0x300000UL 479 #define SMIF_CORE_CTL2_RX_CHASE_MARGIN_Pos 22UL 480 #define SMIF_CORE_CTL2_RX_CHASE_MARGIN_Msk 0xC00000UL 481 #define SMIF_CORE_CTL2_TX_SDR_EXTRA_SETUP_Pos 31UL 482 #define SMIF_CORE_CTL2_TX_SDR_EXTRA_SETUP_Msk 0x80000000UL 483 /* SMIF_CORE.DLP_DELAY_TAP_SEL0 */ 484 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT0_TAP_SEL_Pos 0UL 485 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT0_TAP_SEL_Msk 0xFFUL 486 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT1_TAP_SEL_Pos 8UL 487 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT1_TAP_SEL_Msk 0xFF00UL 488 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT2_TAP_SEL_Pos 16UL 489 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT2_TAP_SEL_Msk 0xFF0000UL 490 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT3_TAP_SEL_Pos 24UL 491 #define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT3_TAP_SEL_Msk 0xFF000000UL 492 /* SMIF_CORE.DLP_DELAY_TAP_SEL1 */ 493 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT4_TAP_SEL_Pos 0UL 494 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT4_TAP_SEL_Msk 0xFFUL 495 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT5_TAP_SEL_Pos 8UL 496 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT5_TAP_SEL_Msk 0xFF00UL 497 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT6_TAP_SEL_Pos 16UL 498 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT6_TAP_SEL_Msk 0xFF0000UL 499 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT7_TAP_SEL_Pos 24UL 500 #define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT7_TAP_SEL_Msk 0xFF000000UL 501 /* SMIF_CORE.DLP_CTL */ 502 #define SMIF_CORE_DLP_CTL_DLP_Pos 0UL 503 #define SMIF_CORE_DLP_CTL_DLP_Msk 0xFFFFUL 504 #define SMIF_CORE_DLP_CTL_DLP_SIZE_Pos 16UL 505 #define SMIF_CORE_DLP_CTL_DLP_SIZE_Msk 0xF0000UL 506 #define SMIF_CORE_DLP_CTL_DLP_WARNING_LEVEL_Pos 24UL 507 #define SMIF_CORE_DLP_CTL_DLP_WARNING_LEVEL_Msk 0xF000000UL 508 /* SMIF_CORE.DLP_STATUS0 */ 509 #define SMIF_CORE_DLP_STATUS0_DATA_BIT0_Pos 0UL 510 #define SMIF_CORE_DLP_STATUS0_DATA_BIT0_Msk 0x1FUL 511 #define SMIF_CORE_DLP_STATUS0_DATA_BIT1_Pos 8UL 512 #define SMIF_CORE_DLP_STATUS0_DATA_BIT1_Msk 0x1F00UL 513 #define SMIF_CORE_DLP_STATUS0_DATA_BIT2_Pos 16UL 514 #define SMIF_CORE_DLP_STATUS0_DATA_BIT2_Msk 0x1F0000UL 515 #define SMIF_CORE_DLP_STATUS0_DATA_BIT3_Pos 24UL 516 #define SMIF_CORE_DLP_STATUS0_DATA_BIT3_Msk 0x1F000000UL 517 /* SMIF_CORE.DLP_STATUS1 */ 518 #define SMIF_CORE_DLP_STATUS1_DATA_BIT4_Pos 0UL 519 #define SMIF_CORE_DLP_STATUS1_DATA_BIT4_Msk 0x1FUL 520 #define SMIF_CORE_DLP_STATUS1_DATA_BIT5_Pos 8UL 521 #define SMIF_CORE_DLP_STATUS1_DATA_BIT5_Msk 0x1F00UL 522 #define SMIF_CORE_DLP_STATUS1_DATA_BIT6_Pos 16UL 523 #define SMIF_CORE_DLP_STATUS1_DATA_BIT6_Msk 0x1F0000UL 524 #define SMIF_CORE_DLP_STATUS1_DATA_BIT7_Pos 24UL 525 #define SMIF_CORE_DLP_STATUS1_DATA_BIT7_Msk 0x1F000000UL 526 /* SMIF_CORE.TX_CMD_FIFO_STATUS */ 527 #define SMIF_CORE_TX_CMD_FIFO_STATUS_USED4_Pos 0UL 528 #define SMIF_CORE_TX_CMD_FIFO_STATUS_USED4_Msk 0xFUL 529 /* SMIF_CORE.TX_CMD_MMIO_FIFO_STATUS */ 530 #define SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Pos 0UL 531 #define SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 532 /* SMIF_CORE.TX_CMD_MMIO_FIFO_WR */ 533 #define SMIF_CORE_TX_CMD_MMIO_FIFO_WR_DATA27_Pos 0UL 534 #define SMIF_CORE_TX_CMD_MMIO_FIFO_WR_DATA27_Msk 0x7FFFFFFUL 535 /* SMIF_CORE.TX_DATA_MMIO_FIFO_CTL */ 536 #define SMIF_CORE_TX_DATA_MMIO_FIFO_CTL_TX_TRIGGER_LEVEL_Pos 0UL 537 #define SMIF_CORE_TX_DATA_MMIO_FIFO_CTL_TX_TRIGGER_LEVEL_Msk 0x7UL 538 /* SMIF_CORE.TX_DATA_FIFO_STATUS */ 539 #define SMIF_CORE_TX_DATA_FIFO_STATUS_USED4_Pos 0UL 540 #define SMIF_CORE_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 541 /* SMIF_CORE.TX_DATA_MMIO_FIFO_STATUS */ 542 #define SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL 543 #define SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 544 /* SMIF_CORE.TX_DATA_MMIO_FIFO_WR1 */ 545 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1_DATA0_Pos 0UL 546 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1_DATA0_Msk 0xFFUL 547 /* SMIF_CORE.TX_DATA_MMIO_FIFO_WR2 */ 548 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA0_Pos 0UL 549 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA0_Msk 0xFFUL 550 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA1_Pos 8UL 551 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA1_Msk 0xFF00UL 552 /* SMIF_CORE.TX_DATA_MMIO_FIFO_WR4 */ 553 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA0_Pos 0UL 554 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA0_Msk 0xFFUL 555 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA1_Pos 8UL 556 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA1_Msk 0xFF00UL 557 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA2_Pos 16UL 558 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA2_Msk 0xFF0000UL 559 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA3_Pos 24UL 560 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA3_Msk 0xFF000000UL 561 /* SMIF_CORE.TX_DATA_MMIO_FIFO_WR1ODD */ 562 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1ODD_DATA0_Pos 0UL 563 #define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1ODD_DATA0_Msk 0xFFUL 564 /* SMIF_CORE.RX_DATA_MMIO_FIFO_CTL */ 565 #define SMIF_CORE_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Pos 0UL 566 #define SMIF_CORE_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Msk 0x7UL 567 /* SMIF_CORE.RX_DATA_MMIO_FIFO_STATUS */ 568 #define SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL 569 #define SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 570 /* SMIF_CORE.RX_DATA_FIFO_STATUS */ 571 #define SMIF_CORE_RX_DATA_FIFO_STATUS_USED4_Pos 0UL 572 #define SMIF_CORE_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 573 #define SMIF_CORE_RX_DATA_FIFO_STATUS_RX_SR_USED_Pos 8UL 574 #define SMIF_CORE_RX_DATA_FIFO_STATUS_RX_SR_USED_Msk 0x100UL 575 /* SMIF_CORE.RX_DATA_MMIO_FIFO_RD1 */ 576 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_DATA0_Pos 0UL 577 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_DATA0_Msk 0xFFUL 578 /* SMIF_CORE.RX_DATA_MMIO_FIFO_RD2 */ 579 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA0_Pos 0UL 580 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA0_Msk 0xFFUL 581 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA1_Pos 8UL 582 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA1_Msk 0xFF00UL 583 /* SMIF_CORE.RX_DATA_MMIO_FIFO_RD4 */ 584 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA0_Pos 0UL 585 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA0_Msk 0xFFUL 586 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA1_Pos 8UL 587 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA1_Msk 0xFF00UL 588 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA2_Pos 16UL 589 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA2_Msk 0xFF0000UL 590 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA3_Pos 24UL 591 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA3_Msk 0xFF000000UL 592 /* SMIF_CORE.RX_DATA_MMIO_FIFO_RD1_SILENT */ 593 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Pos 0UL 594 #define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL 595 /* SMIF_CORE.SLOW_CA_CTL */ 596 #define SMIF_CORE_SLOW_CA_CTL_WAY_Pos 16UL 597 #define SMIF_CORE_SLOW_CA_CTL_WAY_Msk 0x30000UL 598 #define SMIF_CORE_SLOW_CA_CTL_SET_ADDR_Pos 24UL 599 #define SMIF_CORE_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL 600 #define SMIF_CORE_SLOW_CA_CTL_PREF_EN_Pos 30UL 601 #define SMIF_CORE_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL 602 #define SMIF_CORE_SLOW_CA_CTL_ENABLED_Pos 31UL 603 #define SMIF_CORE_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL 604 /* SMIF_CORE.SLOW_CA_CMD */ 605 #define SMIF_CORE_SLOW_CA_CMD_INV_Pos 0UL 606 #define SMIF_CORE_SLOW_CA_CMD_INV_Msk 0x1UL 607 /* SMIF_CORE.FAST_CA_CTL */ 608 #define SMIF_CORE_FAST_CA_CTL_WAY_Pos 16UL 609 #define SMIF_CORE_FAST_CA_CTL_WAY_Msk 0x30000UL 610 #define SMIF_CORE_FAST_CA_CTL_SET_ADDR_Pos 24UL 611 #define SMIF_CORE_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL 612 #define SMIF_CORE_FAST_CA_CTL_PREF_EN_Pos 30UL 613 #define SMIF_CORE_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL 614 #define SMIF_CORE_FAST_CA_CTL_ENABLED_Pos 31UL 615 #define SMIF_CORE_FAST_CA_CTL_ENABLED_Msk 0x80000000UL 616 /* SMIF_CORE.FAST_CA_CMD */ 617 #define SMIF_CORE_FAST_CA_CMD_INV_Pos 0UL 618 #define SMIF_CORE_FAST_CA_CMD_INV_Msk 0x1UL 619 /* SMIF_CORE.CRC_CMD */ 620 #define SMIF_CORE_CRC_CMD_START_Pos 0UL 621 #define SMIF_CORE_CRC_CMD_START_Msk 0x1UL 622 #define SMIF_CORE_CRC_CMD_CONTINUE_Pos 1UL 623 #define SMIF_CORE_CRC_CMD_CONTINUE_Msk 0x2UL 624 /* SMIF_CORE.CRC_INPUT0 */ 625 #define SMIF_CORE_CRC_INPUT0_INPUT_Pos 0UL 626 #define SMIF_CORE_CRC_INPUT0_INPUT_Msk 0xFFFFFFFFUL 627 /* SMIF_CORE.CRC_INPUT1 */ 628 #define SMIF_CORE_CRC_INPUT1_INPUT_Pos 0UL 629 #define SMIF_CORE_CRC_INPUT1_INPUT_Msk 0xFFFFFFFFUL 630 /* SMIF_CORE.CRC_OUTPUT */ 631 #define SMIF_CORE_CRC_OUTPUT_CRC_OUTPUT_Pos 0UL 632 #define SMIF_CORE_CRC_OUTPUT_CRC_OUTPUT_Msk 0xFFUL 633 /* SMIF_CORE.INTR */ 634 #define SMIF_CORE_INTR_TR_TX_REQ_Pos 0UL 635 #define SMIF_CORE_INTR_TR_TX_REQ_Msk 0x1UL 636 #define SMIF_CORE_INTR_TR_RX_REQ_Pos 1UL 637 #define SMIF_CORE_INTR_TR_RX_REQ_Msk 0x2UL 638 #define SMIF_CORE_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL 639 #define SMIF_CORE_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL 640 #define SMIF_CORE_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL 641 #define SMIF_CORE_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 642 #define SMIF_CORE_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL 643 #define SMIF_CORE_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 644 #define SMIF_CORE_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 645 #define SMIF_CORE_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 646 #define SMIF_CORE_INTR_DLP_FAIL_Pos 8UL 647 #define SMIF_CORE_INTR_DLP_FAIL_Msk 0x100UL 648 #define SMIF_CORE_INTR_DLP_WARNING_Pos 12UL 649 #define SMIF_CORE_INTR_DLP_WARNING_Msk 0x1000UL 650 #define SMIF_CORE_INTR_DLL_LOCK_Pos 13UL 651 #define SMIF_CORE_INTR_DLL_LOCK_Msk 0x2000UL 652 #define SMIF_CORE_INTR_DLL_UNLOCK_Pos 14UL 653 #define SMIF_CORE_INTR_DLL_UNLOCK_Msk 0x4000UL 654 #define SMIF_CORE_INTR_CRC_ERROR_Pos 16UL 655 #define SMIF_CORE_INTR_CRC_ERROR_Msk 0x10000UL 656 #define SMIF_CORE_INTR_FS_STATUS_ERROR_Pos 17UL 657 #define SMIF_CORE_INTR_FS_STATUS_ERROR_Msk 0x20000UL 658 /* SMIF_CORE.INTR_SET */ 659 #define SMIF_CORE_INTR_SET_TR_TX_REQ_Pos 0UL 660 #define SMIF_CORE_INTR_SET_TR_TX_REQ_Msk 0x1UL 661 #define SMIF_CORE_INTR_SET_TR_RX_REQ_Pos 1UL 662 #define SMIF_CORE_INTR_SET_TR_RX_REQ_Msk 0x2UL 663 #define SMIF_CORE_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL 664 #define SMIF_CORE_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL 665 #define SMIF_CORE_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL 666 #define SMIF_CORE_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 667 #define SMIF_CORE_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL 668 #define SMIF_CORE_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 669 #define SMIF_CORE_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 670 #define SMIF_CORE_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 671 #define SMIF_CORE_INTR_SET_DLP_FAIL_Pos 8UL 672 #define SMIF_CORE_INTR_SET_DLP_FAIL_Msk 0x100UL 673 #define SMIF_CORE_INTR_SET_DLP_WARNING_Pos 12UL 674 #define SMIF_CORE_INTR_SET_DLP_WARNING_Msk 0x1000UL 675 #define SMIF_CORE_INTR_SET_DLL_LOCK_Pos 13UL 676 #define SMIF_CORE_INTR_SET_DLL_LOCK_Msk 0x2000UL 677 #define SMIF_CORE_INTR_SET_DLL_UNLOCK_Pos 14UL 678 #define SMIF_CORE_INTR_SET_DLL_UNLOCK_Msk 0x4000UL 679 #define SMIF_CORE_INTR_SET_CRC_ERROR_Pos 16UL 680 #define SMIF_CORE_INTR_SET_CRC_ERROR_Msk 0x10000UL 681 #define SMIF_CORE_INTR_SET_FS_STATUS_ERROR_Pos 17UL 682 #define SMIF_CORE_INTR_SET_FS_STATUS_ERROR_Msk 0x20000UL 683 /* SMIF_CORE.INTR_MASK */ 684 #define SMIF_CORE_INTR_MASK_TR_TX_REQ_Pos 0UL 685 #define SMIF_CORE_INTR_MASK_TR_TX_REQ_Msk 0x1UL 686 #define SMIF_CORE_INTR_MASK_TR_RX_REQ_Pos 1UL 687 #define SMIF_CORE_INTR_MASK_TR_RX_REQ_Msk 0x2UL 688 #define SMIF_CORE_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL 689 #define SMIF_CORE_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL 690 #define SMIF_CORE_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL 691 #define SMIF_CORE_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 692 #define SMIF_CORE_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL 693 #define SMIF_CORE_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 694 #define SMIF_CORE_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 695 #define SMIF_CORE_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 696 #define SMIF_CORE_INTR_MASK_DLP_FAIL_Pos 8UL 697 #define SMIF_CORE_INTR_MASK_DLP_FAIL_Msk 0x100UL 698 #define SMIF_CORE_INTR_MASK_DLP_WARNING_Pos 12UL 699 #define SMIF_CORE_INTR_MASK_DLP_WARNING_Msk 0x1000UL 700 #define SMIF_CORE_INTR_MASK_DLL_LOCK_Pos 13UL 701 #define SMIF_CORE_INTR_MASK_DLL_LOCK_Msk 0x2000UL 702 #define SMIF_CORE_INTR_MASK_DLL_UNLOCK_Pos 14UL 703 #define SMIF_CORE_INTR_MASK_DLL_UNLOCK_Msk 0x4000UL 704 #define SMIF_CORE_INTR_MASK_CRC_ERROR_Pos 16UL 705 #define SMIF_CORE_INTR_MASK_CRC_ERROR_Msk 0x10000UL 706 #define SMIF_CORE_INTR_MASK_FS_STATUS_ERROR_Pos 17UL 707 #define SMIF_CORE_INTR_MASK_FS_STATUS_ERROR_Msk 0x20000UL 708 /* SMIF_CORE.INTR_MASKED */ 709 #define SMIF_CORE_INTR_MASKED_TR_TX_REQ_Pos 0UL 710 #define SMIF_CORE_INTR_MASKED_TR_TX_REQ_Msk 0x1UL 711 #define SMIF_CORE_INTR_MASKED_TR_RX_REQ_Pos 1UL 712 #define SMIF_CORE_INTR_MASKED_TR_RX_REQ_Msk 0x2UL 713 #define SMIF_CORE_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL 714 #define SMIF_CORE_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL 715 #define SMIF_CORE_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL 716 #define SMIF_CORE_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 717 #define SMIF_CORE_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL 718 #define SMIF_CORE_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 719 #define SMIF_CORE_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 720 #define SMIF_CORE_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 721 #define SMIF_CORE_INTR_MASKED_DLP_FAIL_Pos 8UL 722 #define SMIF_CORE_INTR_MASKED_DLP_FAIL_Msk 0x100UL 723 #define SMIF_CORE_INTR_MASKED_DLP_WARNING_Pos 12UL 724 #define SMIF_CORE_INTR_MASKED_DLP_WARNING_Msk 0x1000UL 725 #define SMIF_CORE_INTR_MASKED_DLL_LOCK_Pos 13UL 726 #define SMIF_CORE_INTR_MASKED_DLL_LOCK_Msk 0x2000UL 727 #define SMIF_CORE_INTR_MASKED_DLL_UNLOCK_Pos 14UL 728 #define SMIF_CORE_INTR_MASKED_DLL_UNLOCK_Msk 0x4000UL 729 #define SMIF_CORE_INTR_MASKED_CRC_ERROR_Pos 16UL 730 #define SMIF_CORE_INTR_MASKED_CRC_ERROR_Msk 0x10000UL 731 #define SMIF_CORE_INTR_MASKED_FS_STATUS_ERROR_Pos 17UL 732 #define SMIF_CORE_INTR_MASKED_FS_STATUS_ERROR_Msk 0x20000UL 733 734 735 #endif /* _CYIP_SMIF_V4_H_ */ 736 737 738 /* [] END OF FILE */ 739
