1 /***************************************************************************//** 2 * \file cyip_peri_ms_v2.h 3 * 4 * \brief 5 * PERI_MS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PERI_MS_V2_H_ 28 #define _CYIP_PERI_MS_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PERI_MS 34 *******************************************************************************/ 35 36 #define PERI_MS_PPU_PR_V2_SECTION_SIZE 0x00000040UL 37 #define PERI_MS_PPU_FX_V2_SECTION_SIZE 0x00000040UL 38 #define PERI_MS_V2_SECTION_SIZE 0x00010000UL 39 40 /** 41 * \brief Programmable protection structure pair (PERI_MS_PPU_PR) 42 */ 43 typedef struct { 44 __IOM uint32_t SL_ADDR; /*!< 0x00000000 Slave region, base address */ 45 __IOM uint32_t SL_SIZE; /*!< 0x00000004 Slave region, size */ 46 __IM uint32_t RESERVED[2]; 47 __IOM uint32_t SL_ATT0; /*!< 0x00000010 Slave attributes 0 */ 48 __IOM uint32_t SL_ATT1; /*!< 0x00000014 Slave attributes 1 */ 49 __IOM uint32_t SL_ATT2; /*!< 0x00000018 Slave attributes 2 */ 50 __IOM uint32_t SL_ATT3; /*!< 0x0000001C Slave attributes 3 */ 51 __IM uint32_t MS_ADDR; /*!< 0x00000020 Master region, base address */ 52 __IM uint32_t MS_SIZE; /*!< 0x00000024 Master region, size */ 53 __IM uint32_t RESERVED1[2]; 54 __IOM uint32_t MS_ATT0; /*!< 0x00000030 Master attributes 0 */ 55 __IOM uint32_t MS_ATT1; /*!< 0x00000034 Master attributes 1 */ 56 __IOM uint32_t MS_ATT2; /*!< 0x00000038 Master attributes 2 */ 57 __IOM uint32_t MS_ATT3; /*!< 0x0000003C Master attributes 3 */ 58 } PERI_MS_PPU_PR_V2_Type; /*!< Size = 64 (0x40) */ 59 60 /** 61 * \brief Fixed protection structure pair (PERI_MS_PPU_FX) 62 */ 63 typedef struct { 64 __IM uint32_t SL_ADDR; /*!< 0x00000000 Slave region, base address */ 65 __IM uint32_t SL_SIZE; /*!< 0x00000004 Slave region, size */ 66 __IM uint32_t RESERVED[2]; 67 __IOM uint32_t SL_ATT0; /*!< 0x00000010 Slave attributes 0 */ 68 __IOM uint32_t SL_ATT1; /*!< 0x00000014 Slave attributes 1 */ 69 __IOM uint32_t SL_ATT2; /*!< 0x00000018 Slave attributes 2 */ 70 __IOM uint32_t SL_ATT3; /*!< 0x0000001C Slave attributes 3 */ 71 __IM uint32_t MS_ADDR; /*!< 0x00000020 Master region, base address */ 72 __IM uint32_t MS_SIZE; /*!< 0x00000024 Master region, size */ 73 __IM uint32_t RESERVED1[2]; 74 __IOM uint32_t MS_ATT0; /*!< 0x00000030 Master attributes 0 */ 75 __IOM uint32_t MS_ATT1; /*!< 0x00000034 Master attributes 1 */ 76 __IOM uint32_t MS_ATT2; /*!< 0x00000038 Master attributes 2 */ 77 __IOM uint32_t MS_ATT3; /*!< 0x0000003C Master attributes 3 */ 78 } PERI_MS_PPU_FX_V2_Type; /*!< Size = 64 (0x40) */ 79 80 /** 81 * \brief Peripheral interconnect, master interface (PERI_MS) 82 */ 83 typedef struct { 84 PERI_MS_PPU_PR_V2_Type PPU_PR[32]; /*!< 0x00000000 Programmable protection structure pair */ 85 PERI_MS_PPU_FX_V2_Type PPU_FX[992]; /*!< 0x00000800 Fixed protection structure pair */ 86 } PERI_MS_V2_Type; /*!< Size = 65536 (0x10000) */ 87 88 89 /* PERI_MS_PPU_PR.SL_ADDR */ 90 #define PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Pos 2UL 91 #define PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk 0xFFFFFFFCUL 92 /* PERI_MS_PPU_PR.SL_SIZE */ 93 #define PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE_Pos 24UL 94 #define PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE_Msk 0x1F000000UL 95 #define PERI_MS_PPU_PR_V2_SL_SIZE_VALID_Pos 31UL 96 #define PERI_MS_PPU_PR_V2_SL_SIZE_VALID_Msk 0x80000000UL 97 /* PERI_MS_PPU_PR.SL_ATT0 */ 98 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UR_Pos 0UL 99 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UR_Msk 0x1UL 100 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UW_Pos 1UL 101 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UW_Msk 0x2UL 102 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PR_Pos 2UL 103 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PR_Msk 0x4UL 104 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PW_Pos 3UL 105 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PW_Msk 0x8UL 106 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_NS_Pos 4UL 107 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_NS_Msk 0x10UL 108 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UR_Pos 8UL 109 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UR_Msk 0x100UL 110 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UW_Pos 9UL 111 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UW_Msk 0x200UL 112 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PR_Pos 10UL 113 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PR_Msk 0x400UL 114 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PW_Pos 11UL 115 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PW_Msk 0x800UL 116 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_NS_Pos 12UL 117 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_NS_Msk 0x1000UL 118 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UR_Pos 16UL 119 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UR_Msk 0x10000UL 120 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UW_Pos 17UL 121 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UW_Msk 0x20000UL 122 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PR_Pos 18UL 123 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PR_Msk 0x40000UL 124 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PW_Pos 19UL 125 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PW_Msk 0x80000UL 126 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_NS_Pos 20UL 127 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_NS_Msk 0x100000UL 128 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UR_Pos 24UL 129 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UR_Msk 0x1000000UL 130 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UW_Pos 25UL 131 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UW_Msk 0x2000000UL 132 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PR_Pos 26UL 133 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PR_Msk 0x4000000UL 134 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PW_Pos 27UL 135 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PW_Msk 0x8000000UL 136 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_NS_Pos 28UL 137 #define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_NS_Msk 0x10000000UL 138 /* PERI_MS_PPU_PR.SL_ATT1 */ 139 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UR_Pos 0UL 140 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UR_Msk 0x1UL 141 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UW_Pos 1UL 142 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UW_Msk 0x2UL 143 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PR_Pos 2UL 144 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PR_Msk 0x4UL 145 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PW_Pos 3UL 146 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PW_Msk 0x8UL 147 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_NS_Pos 4UL 148 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_NS_Msk 0x10UL 149 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UR_Pos 8UL 150 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UR_Msk 0x100UL 151 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UW_Pos 9UL 152 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UW_Msk 0x200UL 153 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PR_Pos 10UL 154 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PR_Msk 0x400UL 155 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PW_Pos 11UL 156 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PW_Msk 0x800UL 157 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_NS_Pos 12UL 158 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_NS_Msk 0x1000UL 159 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UR_Pos 16UL 160 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UR_Msk 0x10000UL 161 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UW_Pos 17UL 162 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UW_Msk 0x20000UL 163 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PR_Pos 18UL 164 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PR_Msk 0x40000UL 165 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PW_Pos 19UL 166 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PW_Msk 0x80000UL 167 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_NS_Pos 20UL 168 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_NS_Msk 0x100000UL 169 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UR_Pos 24UL 170 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UR_Msk 0x1000000UL 171 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UW_Pos 25UL 172 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UW_Msk 0x2000000UL 173 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PR_Pos 26UL 174 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PR_Msk 0x4000000UL 175 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PW_Pos 27UL 176 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PW_Msk 0x8000000UL 177 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_NS_Pos 28UL 178 #define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_NS_Msk 0x10000000UL 179 /* PERI_MS_PPU_PR.SL_ATT2 */ 180 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UR_Pos 0UL 181 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UR_Msk 0x1UL 182 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UW_Pos 1UL 183 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UW_Msk 0x2UL 184 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PR_Pos 2UL 185 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PR_Msk 0x4UL 186 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PW_Pos 3UL 187 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PW_Msk 0x8UL 188 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_NS_Pos 4UL 189 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_NS_Msk 0x10UL 190 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UR_Pos 8UL 191 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UR_Msk 0x100UL 192 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UW_Pos 9UL 193 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UW_Msk 0x200UL 194 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PR_Pos 10UL 195 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PR_Msk 0x400UL 196 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PW_Pos 11UL 197 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PW_Msk 0x800UL 198 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_NS_Pos 12UL 199 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_NS_Msk 0x1000UL 200 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UR_Pos 16UL 201 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UR_Msk 0x10000UL 202 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UW_Pos 17UL 203 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UW_Msk 0x20000UL 204 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PR_Pos 18UL 205 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PR_Msk 0x40000UL 206 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PW_Pos 19UL 207 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PW_Msk 0x80000UL 208 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_NS_Pos 20UL 209 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_NS_Msk 0x100000UL 210 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UR_Pos 24UL 211 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UR_Msk 0x1000000UL 212 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UW_Pos 25UL 213 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UW_Msk 0x2000000UL 214 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PR_Pos 26UL 215 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PR_Msk 0x4000000UL 216 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PW_Pos 27UL 217 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PW_Msk 0x8000000UL 218 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_NS_Pos 28UL 219 #define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_NS_Msk 0x10000000UL 220 /* PERI_MS_PPU_PR.SL_ATT3 */ 221 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UR_Pos 0UL 222 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UR_Msk 0x1UL 223 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UW_Pos 1UL 224 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UW_Msk 0x2UL 225 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PR_Pos 2UL 226 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PR_Msk 0x4UL 227 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PW_Pos 3UL 228 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PW_Msk 0x8UL 229 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_NS_Pos 4UL 230 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_NS_Msk 0x10UL 231 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UR_Pos 8UL 232 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UR_Msk 0x100UL 233 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UW_Pos 9UL 234 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UW_Msk 0x200UL 235 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PR_Pos 10UL 236 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PR_Msk 0x400UL 237 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PW_Pos 11UL 238 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PW_Msk 0x800UL 239 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_NS_Pos 12UL 240 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_NS_Msk 0x1000UL 241 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UR_Pos 16UL 242 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UR_Msk 0x10000UL 243 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UW_Pos 17UL 244 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UW_Msk 0x20000UL 245 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PR_Pos 18UL 246 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PR_Msk 0x40000UL 247 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PW_Pos 19UL 248 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PW_Msk 0x80000UL 249 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_NS_Pos 20UL 250 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_NS_Msk 0x100000UL 251 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UR_Pos 24UL 252 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UR_Msk 0x1000000UL 253 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UW_Pos 25UL 254 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UW_Msk 0x2000000UL 255 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PR_Pos 26UL 256 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PR_Msk 0x4000000UL 257 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PW_Pos 27UL 258 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PW_Msk 0x8000000UL 259 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_NS_Pos 28UL 260 #define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_NS_Msk 0x10000000UL 261 /* PERI_MS_PPU_PR.MS_ADDR */ 262 #define PERI_MS_PPU_PR_V2_MS_ADDR_ADDR26_Pos 6UL 263 #define PERI_MS_PPU_PR_V2_MS_ADDR_ADDR26_Msk 0xFFFFFFC0UL 264 /* PERI_MS_PPU_PR.MS_SIZE */ 265 #define PERI_MS_PPU_PR_V2_MS_SIZE_REGION_SIZE_Pos 24UL 266 #define PERI_MS_PPU_PR_V2_MS_SIZE_REGION_SIZE_Msk 0x1F000000UL 267 #define PERI_MS_PPU_PR_V2_MS_SIZE_VALID_Pos 31UL 268 #define PERI_MS_PPU_PR_V2_MS_SIZE_VALID_Msk 0x80000000UL 269 /* PERI_MS_PPU_PR.MS_ATT0 */ 270 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UR_Pos 0UL 271 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UR_Msk 0x1UL 272 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UW_Pos 1UL 273 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UW_Msk 0x2UL 274 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PR_Pos 2UL 275 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PR_Msk 0x4UL 276 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PW_Pos 3UL 277 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PW_Msk 0x8UL 278 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS_Pos 4UL 279 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS_Msk 0x10UL 280 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos 8UL 281 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Msk 0x100UL 282 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UW_Pos 9UL 283 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UW_Msk 0x200UL 284 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PR_Pos 10UL 285 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PR_Msk 0x400UL 286 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PW_Pos 11UL 287 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PW_Msk 0x800UL 288 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_NS_Pos 12UL 289 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_NS_Msk 0x1000UL 290 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UR_Pos 16UL 291 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UR_Msk 0x10000UL 292 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UW_Pos 17UL 293 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UW_Msk 0x20000UL 294 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PR_Pos 18UL 295 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PR_Msk 0x40000UL 296 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PW_Pos 19UL 297 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PW_Msk 0x80000UL 298 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_NS_Pos 20UL 299 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_NS_Msk 0x100000UL 300 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UR_Pos 24UL 301 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UR_Msk 0x1000000UL 302 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UW_Pos 25UL 303 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UW_Msk 0x2000000UL 304 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PR_Pos 26UL 305 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PR_Msk 0x4000000UL 306 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PW_Pos 27UL 307 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PW_Msk 0x8000000UL 308 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_NS_Pos 28UL 309 #define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_NS_Msk 0x10000000UL 310 /* PERI_MS_PPU_PR.MS_ATT1 */ 311 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UR_Pos 0UL 312 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UR_Msk 0x1UL 313 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UW_Pos 1UL 314 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UW_Msk 0x2UL 315 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PR_Pos 2UL 316 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PR_Msk 0x4UL 317 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PW_Pos 3UL 318 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PW_Msk 0x8UL 319 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_NS_Pos 4UL 320 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_NS_Msk 0x10UL 321 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UR_Pos 8UL 322 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UR_Msk 0x100UL 323 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UW_Pos 9UL 324 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UW_Msk 0x200UL 325 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PR_Pos 10UL 326 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PR_Msk 0x400UL 327 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PW_Pos 11UL 328 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PW_Msk 0x800UL 329 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_NS_Pos 12UL 330 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_NS_Msk 0x1000UL 331 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UR_Pos 16UL 332 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UR_Msk 0x10000UL 333 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UW_Pos 17UL 334 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UW_Msk 0x20000UL 335 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PR_Pos 18UL 336 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PR_Msk 0x40000UL 337 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PW_Pos 19UL 338 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PW_Msk 0x80000UL 339 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_NS_Pos 20UL 340 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_NS_Msk 0x100000UL 341 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UR_Pos 24UL 342 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UR_Msk 0x1000000UL 343 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UW_Pos 25UL 344 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UW_Msk 0x2000000UL 345 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PR_Pos 26UL 346 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PR_Msk 0x4000000UL 347 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PW_Pos 27UL 348 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PW_Msk 0x8000000UL 349 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_NS_Pos 28UL 350 #define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_NS_Msk 0x10000000UL 351 /* PERI_MS_PPU_PR.MS_ATT2 */ 352 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UR_Pos 0UL 353 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UR_Msk 0x1UL 354 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UW_Pos 1UL 355 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UW_Msk 0x2UL 356 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PR_Pos 2UL 357 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PR_Msk 0x4UL 358 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PW_Pos 3UL 359 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PW_Msk 0x8UL 360 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_NS_Pos 4UL 361 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_NS_Msk 0x10UL 362 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UR_Pos 8UL 363 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UR_Msk 0x100UL 364 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UW_Pos 9UL 365 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UW_Msk 0x200UL 366 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PR_Pos 10UL 367 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PR_Msk 0x400UL 368 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PW_Pos 11UL 369 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PW_Msk 0x800UL 370 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_NS_Pos 12UL 371 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_NS_Msk 0x1000UL 372 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UR_Pos 16UL 373 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UR_Msk 0x10000UL 374 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UW_Pos 17UL 375 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UW_Msk 0x20000UL 376 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PR_Pos 18UL 377 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PR_Msk 0x40000UL 378 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PW_Pos 19UL 379 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PW_Msk 0x80000UL 380 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_NS_Pos 20UL 381 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_NS_Msk 0x100000UL 382 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UR_Pos 24UL 383 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UR_Msk 0x1000000UL 384 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UW_Pos 25UL 385 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UW_Msk 0x2000000UL 386 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PR_Pos 26UL 387 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PR_Msk 0x4000000UL 388 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PW_Pos 27UL 389 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PW_Msk 0x8000000UL 390 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_NS_Pos 28UL 391 #define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_NS_Msk 0x10000000UL 392 /* PERI_MS_PPU_PR.MS_ATT3 */ 393 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UR_Pos 0UL 394 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UR_Msk 0x1UL 395 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UW_Pos 1UL 396 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UW_Msk 0x2UL 397 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PR_Pos 2UL 398 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PR_Msk 0x4UL 399 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PW_Pos 3UL 400 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PW_Msk 0x8UL 401 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_NS_Pos 4UL 402 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_NS_Msk 0x10UL 403 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UR_Pos 8UL 404 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UR_Msk 0x100UL 405 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UW_Pos 9UL 406 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UW_Msk 0x200UL 407 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PR_Pos 10UL 408 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PR_Msk 0x400UL 409 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PW_Pos 11UL 410 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PW_Msk 0x800UL 411 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_NS_Pos 12UL 412 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_NS_Msk 0x1000UL 413 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UR_Pos 16UL 414 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UR_Msk 0x10000UL 415 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UW_Pos 17UL 416 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UW_Msk 0x20000UL 417 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PR_Pos 18UL 418 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PR_Msk 0x40000UL 419 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PW_Pos 19UL 420 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PW_Msk 0x80000UL 421 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_NS_Pos 20UL 422 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_NS_Msk 0x100000UL 423 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UR_Pos 24UL 424 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UR_Msk 0x1000000UL 425 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UW_Pos 25UL 426 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UW_Msk 0x2000000UL 427 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PR_Pos 26UL 428 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PR_Msk 0x4000000UL 429 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PW_Pos 27UL 430 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PW_Msk 0x8000000UL 431 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_NS_Pos 28UL 432 #define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_NS_Msk 0x10000000UL 433 434 435 /* PERI_MS_PPU_FX.SL_ADDR */ 436 #define PERI_MS_PPU_FX_V2_SL_ADDR_ADDR30_Pos 2UL 437 #define PERI_MS_PPU_FX_V2_SL_ADDR_ADDR30_Msk 0xFFFFFFFCUL 438 /* PERI_MS_PPU_FX.SL_SIZE */ 439 #define PERI_MS_PPU_FX_V2_SL_SIZE_REGION_SIZE_Pos 24UL 440 #define PERI_MS_PPU_FX_V2_SL_SIZE_REGION_SIZE_Msk 0x1F000000UL 441 #define PERI_MS_PPU_FX_V2_SL_SIZE_VALID_Pos 31UL 442 #define PERI_MS_PPU_FX_V2_SL_SIZE_VALID_Msk 0x80000000UL 443 /* PERI_MS_PPU_FX.SL_ATT0 */ 444 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UR_Pos 0UL 445 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UR_Msk 0x1UL 446 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UW_Pos 1UL 447 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UW_Msk 0x2UL 448 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PR_Pos 2UL 449 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PR_Msk 0x4UL 450 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PW_Pos 3UL 451 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PW_Msk 0x8UL 452 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_NS_Pos 4UL 453 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_NS_Msk 0x10UL 454 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UR_Pos 8UL 455 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UR_Msk 0x100UL 456 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UW_Pos 9UL 457 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UW_Msk 0x200UL 458 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PR_Pos 10UL 459 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PR_Msk 0x400UL 460 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PW_Pos 11UL 461 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PW_Msk 0x800UL 462 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_NS_Pos 12UL 463 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_NS_Msk 0x1000UL 464 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UR_Pos 16UL 465 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UR_Msk 0x10000UL 466 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UW_Pos 17UL 467 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UW_Msk 0x20000UL 468 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PR_Pos 18UL 469 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PR_Msk 0x40000UL 470 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PW_Pos 19UL 471 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PW_Msk 0x80000UL 472 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_NS_Pos 20UL 473 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_NS_Msk 0x100000UL 474 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UR_Pos 24UL 475 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UR_Msk 0x1000000UL 476 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UW_Pos 25UL 477 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UW_Msk 0x2000000UL 478 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PR_Pos 26UL 479 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PR_Msk 0x4000000UL 480 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PW_Pos 27UL 481 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PW_Msk 0x8000000UL 482 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_NS_Pos 28UL 483 #define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_NS_Msk 0x10000000UL 484 /* PERI_MS_PPU_FX.SL_ATT1 */ 485 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UR_Pos 0UL 486 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UR_Msk 0x1UL 487 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UW_Pos 1UL 488 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UW_Msk 0x2UL 489 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PR_Pos 2UL 490 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PR_Msk 0x4UL 491 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PW_Pos 3UL 492 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PW_Msk 0x8UL 493 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_NS_Pos 4UL 494 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_NS_Msk 0x10UL 495 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UR_Pos 8UL 496 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UR_Msk 0x100UL 497 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UW_Pos 9UL 498 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UW_Msk 0x200UL 499 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PR_Pos 10UL 500 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PR_Msk 0x400UL 501 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PW_Pos 11UL 502 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PW_Msk 0x800UL 503 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_NS_Pos 12UL 504 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_NS_Msk 0x1000UL 505 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UR_Pos 16UL 506 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UR_Msk 0x10000UL 507 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UW_Pos 17UL 508 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UW_Msk 0x20000UL 509 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PR_Pos 18UL 510 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PR_Msk 0x40000UL 511 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PW_Pos 19UL 512 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PW_Msk 0x80000UL 513 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_NS_Pos 20UL 514 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_NS_Msk 0x100000UL 515 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UR_Pos 24UL 516 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UR_Msk 0x1000000UL 517 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UW_Pos 25UL 518 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UW_Msk 0x2000000UL 519 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PR_Pos 26UL 520 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PR_Msk 0x4000000UL 521 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PW_Pos 27UL 522 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PW_Msk 0x8000000UL 523 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_NS_Pos 28UL 524 #define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_NS_Msk 0x10000000UL 525 /* PERI_MS_PPU_FX.SL_ATT2 */ 526 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UR_Pos 0UL 527 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UR_Msk 0x1UL 528 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UW_Pos 1UL 529 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UW_Msk 0x2UL 530 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PR_Pos 2UL 531 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PR_Msk 0x4UL 532 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PW_Pos 3UL 533 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PW_Msk 0x8UL 534 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_NS_Pos 4UL 535 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_NS_Msk 0x10UL 536 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UR_Pos 8UL 537 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UR_Msk 0x100UL 538 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UW_Pos 9UL 539 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UW_Msk 0x200UL 540 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PR_Pos 10UL 541 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PR_Msk 0x400UL 542 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PW_Pos 11UL 543 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PW_Msk 0x800UL 544 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_NS_Pos 12UL 545 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_NS_Msk 0x1000UL 546 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UR_Pos 16UL 547 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UR_Msk 0x10000UL 548 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UW_Pos 17UL 549 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UW_Msk 0x20000UL 550 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PR_Pos 18UL 551 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PR_Msk 0x40000UL 552 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PW_Pos 19UL 553 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PW_Msk 0x80000UL 554 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_NS_Pos 20UL 555 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_NS_Msk 0x100000UL 556 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UR_Pos 24UL 557 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UR_Msk 0x1000000UL 558 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UW_Pos 25UL 559 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UW_Msk 0x2000000UL 560 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PR_Pos 26UL 561 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PR_Msk 0x4000000UL 562 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PW_Pos 27UL 563 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PW_Msk 0x8000000UL 564 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_NS_Pos 28UL 565 #define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_NS_Msk 0x10000000UL 566 /* PERI_MS_PPU_FX.SL_ATT3 */ 567 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UR_Pos 0UL 568 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UR_Msk 0x1UL 569 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UW_Pos 1UL 570 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UW_Msk 0x2UL 571 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PR_Pos 2UL 572 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PR_Msk 0x4UL 573 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PW_Pos 3UL 574 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PW_Msk 0x8UL 575 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_NS_Pos 4UL 576 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_NS_Msk 0x10UL 577 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UR_Pos 8UL 578 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UR_Msk 0x100UL 579 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UW_Pos 9UL 580 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UW_Msk 0x200UL 581 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PR_Pos 10UL 582 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PR_Msk 0x400UL 583 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PW_Pos 11UL 584 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PW_Msk 0x800UL 585 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_NS_Pos 12UL 586 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_NS_Msk 0x1000UL 587 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UR_Pos 16UL 588 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UR_Msk 0x10000UL 589 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UW_Pos 17UL 590 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UW_Msk 0x20000UL 591 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PR_Pos 18UL 592 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PR_Msk 0x40000UL 593 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PW_Pos 19UL 594 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PW_Msk 0x80000UL 595 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_NS_Pos 20UL 596 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_NS_Msk 0x100000UL 597 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UR_Pos 24UL 598 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UR_Msk 0x1000000UL 599 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UW_Pos 25UL 600 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UW_Msk 0x2000000UL 601 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PR_Pos 26UL 602 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PR_Msk 0x4000000UL 603 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PW_Pos 27UL 604 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PW_Msk 0x8000000UL 605 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_NS_Pos 28UL 606 #define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_NS_Msk 0x10000000UL 607 /* PERI_MS_PPU_FX.MS_ADDR */ 608 #define PERI_MS_PPU_FX_V2_MS_ADDR_ADDR26_Pos 6UL 609 #define PERI_MS_PPU_FX_V2_MS_ADDR_ADDR26_Msk 0xFFFFFFC0UL 610 /* PERI_MS_PPU_FX.MS_SIZE */ 611 #define PERI_MS_PPU_FX_V2_MS_SIZE_REGION_SIZE_Pos 24UL 612 #define PERI_MS_PPU_FX_V2_MS_SIZE_REGION_SIZE_Msk 0x1F000000UL 613 #define PERI_MS_PPU_FX_V2_MS_SIZE_VALID_Pos 31UL 614 #define PERI_MS_PPU_FX_V2_MS_SIZE_VALID_Msk 0x80000000UL 615 /* PERI_MS_PPU_FX.MS_ATT0 */ 616 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UR_Pos 0UL 617 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UR_Msk 0x1UL 618 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UW_Pos 1UL 619 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UW_Msk 0x2UL 620 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PR_Pos 2UL 621 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PR_Msk 0x4UL 622 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PW_Pos 3UL 623 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PW_Msk 0x8UL 624 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_NS_Pos 4UL 625 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_NS_Msk 0x10UL 626 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UR_Pos 8UL 627 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UR_Msk 0x100UL 628 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UW_Pos 9UL 629 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UW_Msk 0x200UL 630 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PR_Pos 10UL 631 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PR_Msk 0x400UL 632 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PW_Pos 11UL 633 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PW_Msk 0x800UL 634 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_NS_Pos 12UL 635 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_NS_Msk 0x1000UL 636 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UR_Pos 16UL 637 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UR_Msk 0x10000UL 638 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UW_Pos 17UL 639 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UW_Msk 0x20000UL 640 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PR_Pos 18UL 641 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PR_Msk 0x40000UL 642 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PW_Pos 19UL 643 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PW_Msk 0x80000UL 644 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_NS_Pos 20UL 645 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_NS_Msk 0x100000UL 646 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UR_Pos 24UL 647 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UR_Msk 0x1000000UL 648 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UW_Pos 25UL 649 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UW_Msk 0x2000000UL 650 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PR_Pos 26UL 651 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PR_Msk 0x4000000UL 652 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PW_Pos 27UL 653 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PW_Msk 0x8000000UL 654 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_NS_Pos 28UL 655 #define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_NS_Msk 0x10000000UL 656 /* PERI_MS_PPU_FX.MS_ATT1 */ 657 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UR_Pos 0UL 658 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UR_Msk 0x1UL 659 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UW_Pos 1UL 660 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UW_Msk 0x2UL 661 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PR_Pos 2UL 662 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PR_Msk 0x4UL 663 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PW_Pos 3UL 664 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PW_Msk 0x8UL 665 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_NS_Pos 4UL 666 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_NS_Msk 0x10UL 667 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UR_Pos 8UL 668 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UR_Msk 0x100UL 669 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UW_Pos 9UL 670 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UW_Msk 0x200UL 671 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PR_Pos 10UL 672 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PR_Msk 0x400UL 673 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PW_Pos 11UL 674 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PW_Msk 0x800UL 675 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_NS_Pos 12UL 676 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_NS_Msk 0x1000UL 677 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UR_Pos 16UL 678 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UR_Msk 0x10000UL 679 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UW_Pos 17UL 680 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UW_Msk 0x20000UL 681 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PR_Pos 18UL 682 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PR_Msk 0x40000UL 683 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PW_Pos 19UL 684 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PW_Msk 0x80000UL 685 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_NS_Pos 20UL 686 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_NS_Msk 0x100000UL 687 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UR_Pos 24UL 688 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UR_Msk 0x1000000UL 689 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UW_Pos 25UL 690 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UW_Msk 0x2000000UL 691 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PR_Pos 26UL 692 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PR_Msk 0x4000000UL 693 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PW_Pos 27UL 694 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PW_Msk 0x8000000UL 695 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_NS_Pos 28UL 696 #define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_NS_Msk 0x10000000UL 697 /* PERI_MS_PPU_FX.MS_ATT2 */ 698 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UR_Pos 0UL 699 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UR_Msk 0x1UL 700 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UW_Pos 1UL 701 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UW_Msk 0x2UL 702 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PR_Pos 2UL 703 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PR_Msk 0x4UL 704 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PW_Pos 3UL 705 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PW_Msk 0x8UL 706 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_NS_Pos 4UL 707 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_NS_Msk 0x10UL 708 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UR_Pos 8UL 709 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UR_Msk 0x100UL 710 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UW_Pos 9UL 711 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UW_Msk 0x200UL 712 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PR_Pos 10UL 713 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PR_Msk 0x400UL 714 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PW_Pos 11UL 715 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PW_Msk 0x800UL 716 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_NS_Pos 12UL 717 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_NS_Msk 0x1000UL 718 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UR_Pos 16UL 719 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UR_Msk 0x10000UL 720 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UW_Pos 17UL 721 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UW_Msk 0x20000UL 722 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PR_Pos 18UL 723 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PR_Msk 0x40000UL 724 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PW_Pos 19UL 725 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PW_Msk 0x80000UL 726 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_NS_Pos 20UL 727 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_NS_Msk 0x100000UL 728 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UR_Pos 24UL 729 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UR_Msk 0x1000000UL 730 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UW_Pos 25UL 731 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UW_Msk 0x2000000UL 732 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PR_Pos 26UL 733 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PR_Msk 0x4000000UL 734 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PW_Pos 27UL 735 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PW_Msk 0x8000000UL 736 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_NS_Pos 28UL 737 #define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_NS_Msk 0x10000000UL 738 /* PERI_MS_PPU_FX.MS_ATT3 */ 739 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UR_Pos 0UL 740 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UR_Msk 0x1UL 741 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UW_Pos 1UL 742 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UW_Msk 0x2UL 743 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PR_Pos 2UL 744 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PR_Msk 0x4UL 745 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PW_Pos 3UL 746 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PW_Msk 0x8UL 747 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_NS_Pos 4UL 748 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_NS_Msk 0x10UL 749 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UR_Pos 8UL 750 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UR_Msk 0x100UL 751 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UW_Pos 9UL 752 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UW_Msk 0x200UL 753 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PR_Pos 10UL 754 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PR_Msk 0x400UL 755 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PW_Pos 11UL 756 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PW_Msk 0x800UL 757 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_NS_Pos 12UL 758 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_NS_Msk 0x1000UL 759 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UR_Pos 16UL 760 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UR_Msk 0x10000UL 761 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UW_Pos 17UL 762 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UW_Msk 0x20000UL 763 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PR_Pos 18UL 764 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PR_Msk 0x40000UL 765 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PW_Pos 19UL 766 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PW_Msk 0x80000UL 767 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_NS_Pos 20UL 768 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_NS_Msk 0x100000UL 769 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UR_Pos 24UL 770 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UR_Msk 0x1000000UL 771 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UW_Pos 25UL 772 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UW_Msk 0x2000000UL 773 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PR_Pos 26UL 774 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PR_Msk 0x4000000UL 775 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PW_Pos 27UL 776 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PW_Msk 0x8000000UL 777 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_NS_Pos 28UL 778 #define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_NS_Msk 0x10000000UL 779 780 781 #endif /* _CYIP_PERI_MS_V2_H_ */ 782 783 784 /* [] END OF FILE */ 785
