1 /***************************************************************************//**
2 * \file cyip_pd.h
3 *
4 * \brief
5 * PD IP definitions
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYIP_PD_H_
28 #define _CYIP_PD_H_
29 
30 #include "cyip_headers.h"
31 
32 /*******************************************************************************
33 *                                      PD
34 *******************************************************************************/
35 
36 #define PD_SECTION_SIZE                         0x00000400UL
37 
38 /**
39   * \brief Power Domain and Switch Block (PD)
40   */
41 typedef struct {
42   __IOM uint32_t CTL;                           /*!< 0x00000000 Power Domain Control */
43    __IM uint32_t RESERVED[3];
44    __IM uint32_t STATUS;                        /*!< 0x00000010 Power Domain Status */
45    __IM uint32_t RESERVED1[27];
46   __IOM uint32_t TRIM;                          /*!< 0x00000080 Power Switch Trim */
47 } PD_Type;                                      /*!< Size = 132 (0x84) */
48 
49 
50 /* PD.CTL */
51 #define PD_CTL_PWR_MODE_Pos                     0UL
52 #define PD_CTL_PWR_MODE_Msk                     0x3UL
53 /* PD.STATUS */
54 #define PD_STATUS_PWR_DONE_Pos                  4UL
55 #define PD_STATUS_PWR_DONE_Msk                  0x10UL
56 /* PD.TRIM */
57 #define PD_TRIM_PWRSW_WAIT_CNT_Pos              0UL
58 #define PD_TRIM_PWRSW_WAIT_CNT_Msk              0x3UL
59 
60 
61 #endif /* _CYIP_PD_H_ */
62 
63 
64 /* [] END OF FILE */
65