1 /***************************************************************************//** 2 * \file cyip_i2s.h 3 * 4 * \brief 5 * I2S IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_I2S_H_ 28 #define _CYIP_I2S_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * I2S 34 *******************************************************************************/ 35 36 #define I2S_SECTION_SIZE 0x00001000UL 37 38 /** 39 * \brief I2S registers (I2S) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 43 __IM uint32_t RESERVED[3]; 44 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ 45 __IM uint32_t RESERVED1[3]; 46 __IOM uint32_t CMD; /*!< 0x00000020 Command */ 47 __IM uint32_t RESERVED2[7]; 48 __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */ 49 __IM uint32_t RESERVED3[15]; 50 __IOM uint32_t TX_CTL; /*!< 0x00000080 Transmitter control */ 51 __IOM uint32_t TX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */ 52 __IM uint32_t RESERVED4[6]; 53 __IOM uint32_t RX_CTL; /*!< 0x000000A0 Receiver control */ 54 __IOM uint32_t RX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */ 55 __IM uint32_t RESERVED5[86]; 56 __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */ 57 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */ 58 __OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */ 59 __IM uint32_t RESERVED6[61]; 60 __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */ 61 __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */ 62 __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */ 63 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */ 64 __IM uint32_t RESERVED7[764]; 65 __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */ 66 __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */ 67 __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */ 68 __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */ 69 } I2S_V1_Type; /*!< Size = 3856 (0xF10) */ 70 71 72 /* I2S.CTL */ 73 #define I2S_CTL_TX_ENABLED_Pos 30UL 74 #define I2S_CTL_TX_ENABLED_Msk 0x40000000UL 75 #define I2S_CTL_RX_ENABLED_Pos 31UL 76 #define I2S_CTL_RX_ENABLED_Msk 0x80000000UL 77 /* I2S.CLOCK_CTL */ 78 #define I2S_CLOCK_CTL_CLOCK_DIV_Pos 0UL 79 #define I2S_CLOCK_CTL_CLOCK_DIV_Msk 0x3FUL 80 #define I2S_CLOCK_CTL_CLOCK_SEL_Pos 8UL 81 #define I2S_CLOCK_CTL_CLOCK_SEL_Msk 0x100UL 82 /* I2S.CMD */ 83 #define I2S_CMD_TX_START_Pos 0UL 84 #define I2S_CMD_TX_START_Msk 0x1UL 85 #define I2S_CMD_TX_PAUSE_Pos 8UL 86 #define I2S_CMD_TX_PAUSE_Msk 0x100UL 87 #define I2S_CMD_RX_START_Pos 16UL 88 #define I2S_CMD_RX_START_Msk 0x10000UL 89 /* I2S.TR_CTL */ 90 #define I2S_TR_CTL_TX_REQ_EN_Pos 0UL 91 #define I2S_TR_CTL_TX_REQ_EN_Msk 0x1UL 92 #define I2S_TR_CTL_RX_REQ_EN_Pos 16UL 93 #define I2S_TR_CTL_RX_REQ_EN_Msk 0x10000UL 94 /* I2S.TX_CTL */ 95 #define I2S_TX_CTL_B_CLOCK_INV_Pos 3UL 96 #define I2S_TX_CTL_B_CLOCK_INV_Msk 0x8UL 97 #define I2S_TX_CTL_CH_NR_Pos 4UL 98 #define I2S_TX_CTL_CH_NR_Msk 0x70UL 99 #define I2S_TX_CTL_MS_Pos 7UL 100 #define I2S_TX_CTL_MS_Msk 0x80UL 101 #define I2S_TX_CTL_I2S_MODE_Pos 8UL 102 #define I2S_TX_CTL_I2S_MODE_Msk 0x300UL 103 #define I2S_TX_CTL_WS_PULSE_Pos 10UL 104 #define I2S_TX_CTL_WS_PULSE_Msk 0x400UL 105 #define I2S_TX_CTL_OVHDATA_Pos 12UL 106 #define I2S_TX_CTL_OVHDATA_Msk 0x1000UL 107 #define I2S_TX_CTL_WD_EN_Pos 13UL 108 #define I2S_TX_CTL_WD_EN_Msk 0x2000UL 109 #define I2S_TX_CTL_CH_LEN_Pos 16UL 110 #define I2S_TX_CTL_CH_LEN_Msk 0x70000UL 111 #define I2S_TX_CTL_WORD_LEN_Pos 20UL 112 #define I2S_TX_CTL_WORD_LEN_Msk 0x700000UL 113 #define I2S_TX_CTL_SCKO_POL_Pos 24UL 114 #define I2S_TX_CTL_SCKO_POL_Msk 0x1000000UL 115 #define I2S_TX_CTL_SCKI_POL_Pos 25UL 116 #define I2S_TX_CTL_SCKI_POL_Msk 0x2000000UL 117 /* I2S.TX_WATCHDOG */ 118 #define I2S_TX_WATCHDOG_WD_COUNTER_Pos 0UL 119 #define I2S_TX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL 120 /* I2S.RX_CTL */ 121 #define I2S_RX_CTL_B_CLOCK_INV_Pos 3UL 122 #define I2S_RX_CTL_B_CLOCK_INV_Msk 0x8UL 123 #define I2S_RX_CTL_CH_NR_Pos 4UL 124 #define I2S_RX_CTL_CH_NR_Msk 0x70UL 125 #define I2S_RX_CTL_MS_Pos 7UL 126 #define I2S_RX_CTL_MS_Msk 0x80UL 127 #define I2S_RX_CTL_I2S_MODE_Pos 8UL 128 #define I2S_RX_CTL_I2S_MODE_Msk 0x300UL 129 #define I2S_RX_CTL_WS_PULSE_Pos 10UL 130 #define I2S_RX_CTL_WS_PULSE_Msk 0x400UL 131 #define I2S_RX_CTL_WD_EN_Pos 13UL 132 #define I2S_RX_CTL_WD_EN_Msk 0x2000UL 133 #define I2S_RX_CTL_CH_LEN_Pos 16UL 134 #define I2S_RX_CTL_CH_LEN_Msk 0x70000UL 135 #define I2S_RX_CTL_WORD_LEN_Pos 20UL 136 #define I2S_RX_CTL_WORD_LEN_Msk 0x700000UL 137 #define I2S_RX_CTL_BIT_EXTENSION_Pos 23UL 138 #define I2S_RX_CTL_BIT_EXTENSION_Msk 0x800000UL 139 #define I2S_RX_CTL_SCKO_POL_Pos 24UL 140 #define I2S_RX_CTL_SCKO_POL_Msk 0x1000000UL 141 #define I2S_RX_CTL_SCKI_POL_Pos 25UL 142 #define I2S_RX_CTL_SCKI_POL_Msk 0x2000000UL 143 /* I2S.RX_WATCHDOG */ 144 #define I2S_RX_WATCHDOG_WD_COUNTER_Pos 0UL 145 #define I2S_RX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL 146 /* I2S.TX_FIFO_CTL */ 147 #define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 148 #define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL 149 #define I2S_TX_FIFO_CTL_CLEAR_Pos 16UL 150 #define I2S_TX_FIFO_CTL_CLEAR_Msk 0x10000UL 151 #define I2S_TX_FIFO_CTL_FREEZE_Pos 17UL 152 #define I2S_TX_FIFO_CTL_FREEZE_Msk 0x20000UL 153 /* I2S.TX_FIFO_STATUS */ 154 #define I2S_TX_FIFO_STATUS_USED_Pos 0UL 155 #define I2S_TX_FIFO_STATUS_USED_Msk 0x1FFUL 156 #define I2S_TX_FIFO_STATUS_RD_PTR_Pos 16UL 157 #define I2S_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 158 #define I2S_TX_FIFO_STATUS_WR_PTR_Pos 24UL 159 #define I2S_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 160 /* I2S.TX_FIFO_WR */ 161 #define I2S_TX_FIFO_WR_DATA_Pos 0UL 162 #define I2S_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL 163 /* I2S.RX_FIFO_CTL */ 164 #define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 165 #define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL 166 #define I2S_RX_FIFO_CTL_CLEAR_Pos 16UL 167 #define I2S_RX_FIFO_CTL_CLEAR_Msk 0x10000UL 168 #define I2S_RX_FIFO_CTL_FREEZE_Pos 17UL 169 #define I2S_RX_FIFO_CTL_FREEZE_Msk 0x20000UL 170 /* I2S.RX_FIFO_STATUS */ 171 #define I2S_RX_FIFO_STATUS_USED_Pos 0UL 172 #define I2S_RX_FIFO_STATUS_USED_Msk 0x1FFUL 173 #define I2S_RX_FIFO_STATUS_RD_PTR_Pos 16UL 174 #define I2S_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 175 #define I2S_RX_FIFO_STATUS_WR_PTR_Pos 24UL 176 #define I2S_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 177 /* I2S.RX_FIFO_RD */ 178 #define I2S_RX_FIFO_RD_DATA_Pos 0UL 179 #define I2S_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL 180 /* I2S.RX_FIFO_RD_SILENT */ 181 #define I2S_RX_FIFO_RD_SILENT_DATA_Pos 0UL 182 #define I2S_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL 183 /* I2S.INTR */ 184 #define I2S_INTR_TX_TRIGGER_Pos 0UL 185 #define I2S_INTR_TX_TRIGGER_Msk 0x1UL 186 #define I2S_INTR_TX_NOT_FULL_Pos 1UL 187 #define I2S_INTR_TX_NOT_FULL_Msk 0x2UL 188 #define I2S_INTR_TX_EMPTY_Pos 4UL 189 #define I2S_INTR_TX_EMPTY_Msk 0x10UL 190 #define I2S_INTR_TX_OVERFLOW_Pos 5UL 191 #define I2S_INTR_TX_OVERFLOW_Msk 0x20UL 192 #define I2S_INTR_TX_UNDERFLOW_Pos 6UL 193 #define I2S_INTR_TX_UNDERFLOW_Msk 0x40UL 194 #define I2S_INTR_TX_WD_Pos 8UL 195 #define I2S_INTR_TX_WD_Msk 0x100UL 196 #define I2S_INTR_RX_TRIGGER_Pos 16UL 197 #define I2S_INTR_RX_TRIGGER_Msk 0x10000UL 198 #define I2S_INTR_RX_NOT_EMPTY_Pos 18UL 199 #define I2S_INTR_RX_NOT_EMPTY_Msk 0x40000UL 200 #define I2S_INTR_RX_FULL_Pos 19UL 201 #define I2S_INTR_RX_FULL_Msk 0x80000UL 202 #define I2S_INTR_RX_OVERFLOW_Pos 21UL 203 #define I2S_INTR_RX_OVERFLOW_Msk 0x200000UL 204 #define I2S_INTR_RX_UNDERFLOW_Pos 22UL 205 #define I2S_INTR_RX_UNDERFLOW_Msk 0x400000UL 206 #define I2S_INTR_RX_WD_Pos 24UL 207 #define I2S_INTR_RX_WD_Msk 0x1000000UL 208 /* I2S.INTR_SET */ 209 #define I2S_INTR_SET_TX_TRIGGER_Pos 0UL 210 #define I2S_INTR_SET_TX_TRIGGER_Msk 0x1UL 211 #define I2S_INTR_SET_TX_NOT_FULL_Pos 1UL 212 #define I2S_INTR_SET_TX_NOT_FULL_Msk 0x2UL 213 #define I2S_INTR_SET_TX_EMPTY_Pos 4UL 214 #define I2S_INTR_SET_TX_EMPTY_Msk 0x10UL 215 #define I2S_INTR_SET_TX_OVERFLOW_Pos 5UL 216 #define I2S_INTR_SET_TX_OVERFLOW_Msk 0x20UL 217 #define I2S_INTR_SET_TX_UNDERFLOW_Pos 6UL 218 #define I2S_INTR_SET_TX_UNDERFLOW_Msk 0x40UL 219 #define I2S_INTR_SET_TX_WD_Pos 8UL 220 #define I2S_INTR_SET_TX_WD_Msk 0x100UL 221 #define I2S_INTR_SET_RX_TRIGGER_Pos 16UL 222 #define I2S_INTR_SET_RX_TRIGGER_Msk 0x10000UL 223 #define I2S_INTR_SET_RX_NOT_EMPTY_Pos 18UL 224 #define I2S_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL 225 #define I2S_INTR_SET_RX_FULL_Pos 19UL 226 #define I2S_INTR_SET_RX_FULL_Msk 0x80000UL 227 #define I2S_INTR_SET_RX_OVERFLOW_Pos 21UL 228 #define I2S_INTR_SET_RX_OVERFLOW_Msk 0x200000UL 229 #define I2S_INTR_SET_RX_UNDERFLOW_Pos 22UL 230 #define I2S_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL 231 #define I2S_INTR_SET_RX_WD_Pos 24UL 232 #define I2S_INTR_SET_RX_WD_Msk 0x1000000UL 233 /* I2S.INTR_MASK */ 234 #define I2S_INTR_MASK_TX_TRIGGER_Pos 0UL 235 #define I2S_INTR_MASK_TX_TRIGGER_Msk 0x1UL 236 #define I2S_INTR_MASK_TX_NOT_FULL_Pos 1UL 237 #define I2S_INTR_MASK_TX_NOT_FULL_Msk 0x2UL 238 #define I2S_INTR_MASK_TX_EMPTY_Pos 4UL 239 #define I2S_INTR_MASK_TX_EMPTY_Msk 0x10UL 240 #define I2S_INTR_MASK_TX_OVERFLOW_Pos 5UL 241 #define I2S_INTR_MASK_TX_OVERFLOW_Msk 0x20UL 242 #define I2S_INTR_MASK_TX_UNDERFLOW_Pos 6UL 243 #define I2S_INTR_MASK_TX_UNDERFLOW_Msk 0x40UL 244 #define I2S_INTR_MASK_TX_WD_Pos 8UL 245 #define I2S_INTR_MASK_TX_WD_Msk 0x100UL 246 #define I2S_INTR_MASK_RX_TRIGGER_Pos 16UL 247 #define I2S_INTR_MASK_RX_TRIGGER_Msk 0x10000UL 248 #define I2S_INTR_MASK_RX_NOT_EMPTY_Pos 18UL 249 #define I2S_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL 250 #define I2S_INTR_MASK_RX_FULL_Pos 19UL 251 #define I2S_INTR_MASK_RX_FULL_Msk 0x80000UL 252 #define I2S_INTR_MASK_RX_OVERFLOW_Pos 21UL 253 #define I2S_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL 254 #define I2S_INTR_MASK_RX_UNDERFLOW_Pos 22UL 255 #define I2S_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL 256 #define I2S_INTR_MASK_RX_WD_Pos 24UL 257 #define I2S_INTR_MASK_RX_WD_Msk 0x1000000UL 258 /* I2S.INTR_MASKED */ 259 #define I2S_INTR_MASKED_TX_TRIGGER_Pos 0UL 260 #define I2S_INTR_MASKED_TX_TRIGGER_Msk 0x1UL 261 #define I2S_INTR_MASKED_TX_NOT_FULL_Pos 1UL 262 #define I2S_INTR_MASKED_TX_NOT_FULL_Msk 0x2UL 263 #define I2S_INTR_MASKED_TX_EMPTY_Pos 4UL 264 #define I2S_INTR_MASKED_TX_EMPTY_Msk 0x10UL 265 #define I2S_INTR_MASKED_TX_OVERFLOW_Pos 5UL 266 #define I2S_INTR_MASKED_TX_OVERFLOW_Msk 0x20UL 267 #define I2S_INTR_MASKED_TX_UNDERFLOW_Pos 6UL 268 #define I2S_INTR_MASKED_TX_UNDERFLOW_Msk 0x40UL 269 #define I2S_INTR_MASKED_TX_WD_Pos 8UL 270 #define I2S_INTR_MASKED_TX_WD_Msk 0x100UL 271 #define I2S_INTR_MASKED_RX_TRIGGER_Pos 16UL 272 #define I2S_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL 273 #define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL 274 #define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL 275 #define I2S_INTR_MASKED_RX_FULL_Pos 19UL 276 #define I2S_INTR_MASKED_RX_FULL_Msk 0x80000UL 277 #define I2S_INTR_MASKED_RX_OVERFLOW_Pos 21UL 278 #define I2S_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL 279 #define I2S_INTR_MASKED_RX_UNDERFLOW_Pos 22UL 280 #define I2S_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL 281 #define I2S_INTR_MASKED_RX_WD_Pos 24UL 282 #define I2S_INTR_MASKED_RX_WD_Msk 0x1000000UL 283 284 285 #endif /* _CYIP_I2S_H_ */ 286 287 288 /* [] END OF FILE */ 289
