1 /***************************************************************************//** 2 * \file cyip_flashc_v2.h 3 * 4 * \brief 5 * FLASHC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_FLASHC_V2_H_ 28 #define _CYIP_FLASHC_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * FLASHC 34 *******************************************************************************/ 35 36 #define FLASHC_FM_CTL_V2_SECTION_SIZE 0x00001000UL 37 #define FLASHC_V2_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Flash Macro Registers (FLASHC_FM_CTL) 41 */ 42 typedef struct { 43 __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */ 44 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 45 __IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */ 46 __IOM uint32_t BOOKMARK; /*!< 0x0000000C Bookmark register - keeps the current FW HV seq */ 47 __IM uint32_t GEOMETRY; /*!< 0x00000010 Regular flash geometry */ 48 __IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000014 Supervisory flash geometry */ 49 __IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */ 50 __IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */ 51 __IM uint32_t RESERVED[2]; 52 __IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wait State control */ 53 __IM uint32_t RESERVED1[2]; 54 __IOM uint32_t TIMER_CLK_CTL; /*!< 0x00000034 Timer prescaler (clk_t to timer clock frequency divider) */ 55 __IOM uint32_t TIMER_CTL; /*!< 0x00000038 Timer control */ 56 __OM uint32_t ACLK_CTL; /*!< 0x0000003C MPCON clock */ 57 __IOM uint32_t INTR; /*!< 0x00000040 Interrupt */ 58 __IOM uint32_t INTR_SET; /*!< 0x00000044 Interrupt set */ 59 __IOM uint32_t INTR_MASK; /*!< 0x00000048 Interrupt mask */ 60 __IM uint32_t INTR_MASKED; /*!< 0x0000004C Interrupt masked */ 61 __IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */ 62 __IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */ 63 __IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI trim bits */ 64 __IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim */ 65 __IOM uint32_t CAL_CTL4; /*!< 0x00000060 Cal Control Vlim, SA, fdiv, reg_act */ 66 __IOM uint32_t CAL_CTL5; /*!< 0x00000064 Cal control */ 67 __IOM uint32_t CAL_CTL6; /*!< 0x00000068 SA trim LP/ULP */ 68 __IOM uint32_t CAL_CTL7; /*!< 0x0000006C Cal control */ 69 __IM uint32_t RESERVED2[4]; 70 __IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */ 71 __IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Control normal sectors 2,3 */ 72 __IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Control normal sectors 4,5 */ 73 __IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Control normal sectors 6,7 */ 74 __IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Control special sectors 0,1 */ 75 __IM uint32_t RESERVED3; 76 __IOM uint32_t RGRANT_DELAY_PRG; /*!< 0x00000098 R-grant delay for program */ 77 __IM uint32_t RESERVED4; 78 __IOM uint32_t PW_SEQ12; /*!< 0x000000A0 HV Pulse Delay for seq 1&2 pre */ 79 __IOM uint32_t PW_SEQ23; /*!< 0x000000A4 HV Pulse Delay for seq2 post & seq3 */ 80 __IOM uint32_t RGRANT_SCALE_ERS; /*!< 0x000000A8 R-grant delay scale for erase */ 81 __IOM uint32_t RGRANT_DELAY_ERS; /*!< 0x000000AC R-grant delay for erase */ 82 __IM uint32_t RESERVED5[467]; 83 __IOM uint32_t FM_PL_WRDATA_ALL; /*!< 0x000007FC Flash macro write page latches all */ 84 __IOM uint32_t FM_PL_DATA[256]; /*!< 0x00000800 Flash macro Page Latches data */ 85 __IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */ 86 } FLASHC_FM_CTL_V2_Type; /*!< Size = 4096 (0x1000) */ 87 88 /** 89 * \brief Flash controller (FLASHC) 90 */ 91 typedef struct { 92 __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */ 93 __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */ 94 __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */ 95 __IM uint32_t RESERVED[165]; 96 __IOM uint32_t ECC_CTL; /*!< 0x000002A0 ECC control */ 97 __IM uint32_t RESERVED1[3]; 98 __IOM uint32_t FM_SRAM_ECC_CTL0; /*!< 0x000002B0 eCT Flash SRAM ECC control 0 */ 99 __IOM uint32_t FM_SRAM_ECC_CTL1; /*!< 0x000002B4 eCT Flash SRAM ECC control 1 */ 100 __IM uint32_t FM_SRAM_ECC_CTL2; /*!< 0x000002B8 eCT Flash SRAM ECC control 2 */ 101 __IOM uint32_t FM_SRAM_ECC_CTL3; /*!< 0x000002BC eCT Flash SRAM ECC control 3 */ 102 __IM uint32_t RESERVED2[80]; 103 __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */ 104 __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */ 105 __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */ 106 __IM uint32_t RESERVED3[13]; 107 __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */ 108 __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */ 109 __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */ 110 __IM uint32_t RESERVED4[5]; 111 __IOM uint32_t CM0_STATUS; /*!< 0x00000460 CM0+ interface status */ 112 __IM uint32_t RESERVED5[7]; 113 __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */ 114 __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */ 115 __IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */ 116 __IM uint32_t RESERVED6[13]; 117 __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */ 118 __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */ 119 __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */ 120 __IM uint32_t RESERVED7[5]; 121 __IOM uint32_t CM4_STATUS; /*!< 0x000004E0 CM4 interface status */ 122 __IM uint32_t RESERVED8[7]; 123 __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */ 124 __IM uint32_t RESERVED9[31]; 125 __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */ 126 __IM uint32_t RESERVED10[31]; 127 __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */ 128 __IM uint32_t RESERVED11[31]; 129 __IOM uint32_t DMAC_BUFF_CTL; /*!< 0x00000680 DMA controller buffer control */ 130 __IM uint32_t RESERVED12[31]; 131 __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */ 132 __IM uint32_t RESERVED13[31]; 133 __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */ 134 __IM uint32_t RESERVED14[14879]; 135 FLASHC_FM_CTL_V2_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */ 136 } FLASHC_V2_Type; /*!< Size = 65536 (0x10000) */ 137 138 139 /* FLASHC_FM_CTL.FM_CTL */ 140 #define FLASHC_FM_CTL_V2_FM_CTL_FM_MODE_Pos 0UL 141 #define FLASHC_FM_CTL_V2_FM_CTL_FM_MODE_Msk 0xFUL 142 #define FLASHC_FM_CTL_V2_FM_CTL_FM_SEQ_Pos 8UL 143 #define FLASHC_FM_CTL_V2_FM_CTL_FM_SEQ_Msk 0x300UL 144 #define FLASHC_FM_CTL_V2_FM_CTL_DAA_MUX_SEL_Pos 16UL 145 #define FLASHC_FM_CTL_V2_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL 146 #define FLASHC_FM_CTL_V2_FM_CTL_IF_SEL_Pos 24UL 147 #define FLASHC_FM_CTL_V2_FM_CTL_IF_SEL_Msk 0x1000000UL 148 #define FLASHC_FM_CTL_V2_FM_CTL_WR_EN_Pos 25UL 149 #define FLASHC_FM_CTL_V2_FM_CTL_WR_EN_Msk 0x2000000UL 150 /* FLASHC_FM_CTL.STATUS */ 151 #define FLASHC_FM_CTL_V2_STATUS_TIMER_ENABLED_Pos 0UL 152 #define FLASHC_FM_CTL_V2_STATUS_TIMER_ENABLED_Msk 0x1UL 153 #define FLASHC_FM_CTL_V2_STATUS_HV_REGS_ISOLATED_Pos 1UL 154 #define FLASHC_FM_CTL_V2_STATUS_HV_REGS_ISOLATED_Msk 0x2UL 155 #define FLASHC_FM_CTL_V2_STATUS_ILLEGAL_HVOP_Pos 2UL 156 #define FLASHC_FM_CTL_V2_STATUS_ILLEGAL_HVOP_Msk 0x4UL 157 #define FLASHC_FM_CTL_V2_STATUS_TURBO_N_Pos 3UL 158 #define FLASHC_FM_CTL_V2_STATUS_TURBO_N_Msk 0x8UL 159 #define FLASHC_FM_CTL_V2_STATUS_WR_EN_MON_Pos 4UL 160 #define FLASHC_FM_CTL_V2_STATUS_WR_EN_MON_Msk 0x10UL 161 #define FLASHC_FM_CTL_V2_STATUS_IF_SEL_MON_Pos 5UL 162 #define FLASHC_FM_CTL_V2_STATUS_IF_SEL_MON_Msk 0x20UL 163 #define FLASHC_FM_CTL_V2_STATUS_TIMER_STATUS_Pos 6UL 164 #define FLASHC_FM_CTL_V2_STATUS_TIMER_STATUS_Msk 0x40UL 165 #define FLASHC_FM_CTL_V2_STATUS_R_GRANT_DELAY_STATUS_Pos 7UL 166 #define FLASHC_FM_CTL_V2_STATUS_R_GRANT_DELAY_STATUS_Msk 0x80UL 167 #define FLASHC_FM_CTL_V2_STATUS_FM_BUSY_Pos 8UL 168 #define FLASHC_FM_CTL_V2_STATUS_FM_BUSY_Msk 0x100UL 169 #define FLASHC_FM_CTL_V2_STATUS_FM_READY_Pos 9UL 170 #define FLASHC_FM_CTL_V2_STATUS_FM_READY_Msk 0x200UL 171 #define FLASHC_FM_CTL_V2_STATUS_POS_PUMP_VLO_Pos 10UL 172 #define FLASHC_FM_CTL_V2_STATUS_POS_PUMP_VLO_Msk 0x400UL 173 #define FLASHC_FM_CTL_V2_STATUS_NEG_PUMP_VHI_Pos 11UL 174 #define FLASHC_FM_CTL_V2_STATUS_NEG_PUMP_VHI_Msk 0x800UL 175 #define FLASHC_FM_CTL_V2_STATUS_RWW_Pos 12UL 176 #define FLASHC_FM_CTL_V2_STATUS_RWW_Msk 0x1000UL 177 #define FLASHC_FM_CTL_V2_STATUS_MAX_DOUT_WIDTH_Pos 13UL 178 #define FLASHC_FM_CTL_V2_STATUS_MAX_DOUT_WIDTH_Msk 0x2000UL 179 #define FLASHC_FM_CTL_V2_STATUS_SECTOR0_SR_Pos 14UL 180 #define FLASHC_FM_CTL_V2_STATUS_SECTOR0_SR_Msk 0x4000UL 181 #define FLASHC_FM_CTL_V2_STATUS_RESET_MM_Pos 15UL 182 #define FLASHC_FM_CTL_V2_STATUS_RESET_MM_Msk 0x8000UL 183 #define FLASHC_FM_CTL_V2_STATUS_ROW_ODD_Pos 16UL 184 #define FLASHC_FM_CTL_V2_STATUS_ROW_ODD_Msk 0x10000UL 185 #define FLASHC_FM_CTL_V2_STATUS_ROW_EVEN_Pos 17UL 186 #define FLASHC_FM_CTL_V2_STATUS_ROW_EVEN_Msk 0x20000UL 187 #define FLASHC_FM_CTL_V2_STATUS_HVOP_SUB_SECTOR_N_Pos 18UL 188 #define FLASHC_FM_CTL_V2_STATUS_HVOP_SUB_SECTOR_N_Msk 0x40000UL 189 #define FLASHC_FM_CTL_V2_STATUS_HVOP_SECTOR_Pos 19UL 190 #define FLASHC_FM_CTL_V2_STATUS_HVOP_SECTOR_Msk 0x80000UL 191 #define FLASHC_FM_CTL_V2_STATUS_HVOP_BULK_ALL_Pos 20UL 192 #define FLASHC_FM_CTL_V2_STATUS_HVOP_BULK_ALL_Msk 0x100000UL 193 #define FLASHC_FM_CTL_V2_STATUS_CBUS_RA_MATCH_Pos 21UL 194 #define FLASHC_FM_CTL_V2_STATUS_CBUS_RA_MATCH_Msk 0x200000UL 195 #define FLASHC_FM_CTL_V2_STATUS_CBUS_RED_ROW_EN_Pos 22UL 196 #define FLASHC_FM_CTL_V2_STATUS_CBUS_RED_ROW_EN_Msk 0x400000UL 197 #define FLASHC_FM_CTL_V2_STATUS_RQ_ERROR_Pos 23UL 198 #define FLASHC_FM_CTL_V2_STATUS_RQ_ERROR_Msk 0x800000UL 199 #define FLASHC_FM_CTL_V2_STATUS_PUMP_PDAC_Pos 24UL 200 #define FLASHC_FM_CTL_V2_STATUS_PUMP_PDAC_Msk 0xF000000UL 201 #define FLASHC_FM_CTL_V2_STATUS_PUMP_NDAC_Pos 28UL 202 #define FLASHC_FM_CTL_V2_STATUS_PUMP_NDAC_Msk 0xF0000000UL 203 /* FLASHC_FM_CTL.FM_ADDR */ 204 #define FLASHC_FM_CTL_V2_FM_ADDR_RA_Pos 0UL 205 #define FLASHC_FM_CTL_V2_FM_ADDR_RA_Msk 0xFFFFUL 206 #define FLASHC_FM_CTL_V2_FM_ADDR_BA_Pos 16UL 207 #define FLASHC_FM_CTL_V2_FM_ADDR_BA_Msk 0xFF0000UL 208 #define FLASHC_FM_CTL_V2_FM_ADDR_AXA_Pos 24UL 209 #define FLASHC_FM_CTL_V2_FM_ADDR_AXA_Msk 0x1000000UL 210 /* FLASHC_FM_CTL.BOOKMARK */ 211 #define FLASHC_FM_CTL_V2_BOOKMARK_BOOKMARK_Pos 0UL 212 #define FLASHC_FM_CTL_V2_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL 213 /* FLASHC_FM_CTL.GEOMETRY */ 214 #define FLASHC_FM_CTL_V2_GEOMETRY_ROW_COUNT_Pos 0UL 215 #define FLASHC_FM_CTL_V2_GEOMETRY_ROW_COUNT_Msk 0xFFFFUL 216 #define FLASHC_FM_CTL_V2_GEOMETRY_BANK_COUNT_Pos 16UL 217 #define FLASHC_FM_CTL_V2_GEOMETRY_BANK_COUNT_Msk 0xFF0000UL 218 #define FLASHC_FM_CTL_V2_GEOMETRY_WORD_SIZE_LOG2_Pos 24UL 219 #define FLASHC_FM_CTL_V2_GEOMETRY_WORD_SIZE_LOG2_Msk 0xF000000UL 220 #define FLASHC_FM_CTL_V2_GEOMETRY_PAGE_SIZE_LOG2_Pos 28UL 221 #define FLASHC_FM_CTL_V2_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0000000UL 222 /* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */ 223 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 0UL 224 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFFUL 225 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 16UL 226 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF0000UL 227 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 24UL 228 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xF000000UL 229 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 28UL 230 #define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0000000UL 231 /* FLASHC_FM_CTL.ANA_CTL0 */ 232 #define FLASHC_FM_CTL_V2_ANA_CTL0_MDAC_Pos 0UL 233 #define FLASHC_FM_CTL_V2_ANA_CTL0_MDAC_Msk 0xFFUL 234 #define FLASHC_FM_CTL_V2_ANA_CTL0_CSLDAC_Pos 8UL 235 #define FLASHC_FM_CTL_V2_ANA_CTL0_CSLDAC_Msk 0x700UL 236 #define FLASHC_FM_CTL_V2_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 11UL 237 #define FLASHC_FM_CTL_V2_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x800UL 238 #define FLASHC_FM_CTL_V2_ANA_CTL0_NDAC_MIN_Pos 12UL 239 #define FLASHC_FM_CTL_V2_ANA_CTL0_NDAC_MIN_Msk 0xF000UL 240 #define FLASHC_FM_CTL_V2_ANA_CTL0_PDAC_MIN_Pos 16UL 241 #define FLASHC_FM_CTL_V2_ANA_CTL0_PDAC_MIN_Msk 0xF0000UL 242 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ01_Pos 20UL 243 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ01_Msk 0x300000UL 244 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ12_Pos 22UL 245 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ12_Msk 0xC00000UL 246 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ23_Pos 24UL 247 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_SEQ23_Msk 0x3000000UL 248 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ30_Pos 26UL 249 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ30_Msk 0xC000000UL 250 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEON_Pos 28UL 251 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEON_Msk 0x30000000UL 252 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEOFF_Pos 30UL 253 #define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PRG_PEOFF_Msk 0xC0000000UL 254 /* FLASHC_FM_CTL.ANA_CTL1 */ 255 #define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_MAX_Pos 0UL 256 #define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_MAX_Msk 0xFUL 257 #define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_STEP_Pos 4UL 258 #define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_STEP_Msk 0xF0UL 259 #define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_MAX_Pos 8UL 260 #define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_MAX_Msk 0xF00UL 261 #define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_STEP_Pos 12UL 262 #define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_STEP_Msk 0xF000UL 263 #define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_STEP_TIME_Pos 16UL 264 #define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_STEP_TIME_Msk 0xFF0000UL 265 #define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_ZERO_TIME_Pos 24UL 266 #define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_ZERO_TIME_Msk 0xFF000000UL 267 /* FLASHC_FM_CTL.WAIT_CTL */ 268 #define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL 269 #define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL 270 #define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL 271 #define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL 272 #define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL 273 #define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL 274 #define FLASHC_FM_CTL_V2_WAIT_CTL_FM_RWW_MODE_Pos 24UL 275 #define FLASHC_FM_CTL_V2_WAIT_CTL_FM_RWW_MODE_Msk 0x3000000UL 276 #define FLASHC_FM_CTL_V2_WAIT_CTL_LV_SPARE_1_Pos 26UL 277 #define FLASHC_FM_CTL_V2_WAIT_CTL_LV_SPARE_1_Msk 0x4000000UL 278 #define FLASHC_FM_CTL_V2_WAIT_CTL_DRMM_Pos 27UL 279 #define FLASHC_FM_CTL_V2_WAIT_CTL_DRMM_Msk 0x8000000UL 280 #define FLASHC_FM_CTL_V2_WAIT_CTL_MBA_Pos 28UL 281 #define FLASHC_FM_CTL_V2_WAIT_CTL_MBA_Msk 0x10000000UL 282 #define FLASHC_FM_CTL_V2_WAIT_CTL_PL_SOFT_SET_EN_Pos 29UL 283 #define FLASHC_FM_CTL_V2_WAIT_CTL_PL_SOFT_SET_EN_Msk 0x20000000UL 284 /* FLASHC_FM_CTL.TIMER_CLK_CTL */ 285 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Pos 0UL 286 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL 287 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEON_Pos 8UL 288 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEON_Msk 0xFF00UL 289 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEOFF_Pos 16UL 290 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_PEOFF_Msk 0xFF0000UL 291 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_SEQ01_Pos 24UL 292 #define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PRG_SEQ01_Msk 0xFF000000UL 293 /* FLASHC_FM_CTL.TIMER_CTL */ 294 #define FLASHC_FM_CTL_V2_TIMER_CTL_PERIOD_Pos 0UL 295 #define FLASHC_FM_CTL_V2_TIMER_CTL_PERIOD_Msk 0x7FFFUL 296 #define FLASHC_FM_CTL_V2_TIMER_CTL_SCALE_Pos 15UL 297 #define FLASHC_FM_CTL_V2_TIMER_CTL_SCALE_Msk 0x8000UL 298 #define FLASHC_FM_CTL_V2_TIMER_CTL_AUTO_SEQUENCE_Pos 24UL 299 #define FLASHC_FM_CTL_V2_TIMER_CTL_AUTO_SEQUENCE_Msk 0x1000000UL 300 #define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_Pos 25UL 301 #define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_Msk 0x2000000UL 302 #define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_CSL_Pos 26UL 303 #define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL 304 #define FLASHC_FM_CTL_V2_TIMER_CTL_PUMP_EN_Pos 29UL 305 #define FLASHC_FM_CTL_V2_TIMER_CTL_PUMP_EN_Msk 0x20000000UL 306 #define FLASHC_FM_CTL_V2_TIMER_CTL_ACLK_EN_Pos 30UL 307 #define FLASHC_FM_CTL_V2_TIMER_CTL_ACLK_EN_Msk 0x40000000UL 308 #define FLASHC_FM_CTL_V2_TIMER_CTL_TIMER_EN_Pos 31UL 309 #define FLASHC_FM_CTL_V2_TIMER_CTL_TIMER_EN_Msk 0x80000000UL 310 /* FLASHC_FM_CTL.ACLK_CTL */ 311 #define FLASHC_FM_CTL_V2_ACLK_CTL_ACLK_GEN_Pos 0UL 312 #define FLASHC_FM_CTL_V2_ACLK_CTL_ACLK_GEN_Msk 0x1UL 313 /* FLASHC_FM_CTL.INTR */ 314 #define FLASHC_FM_CTL_V2_INTR_TIMER_EXPIRED_Pos 0UL 315 #define FLASHC_FM_CTL_V2_INTR_TIMER_EXPIRED_Msk 0x1UL 316 /* FLASHC_FM_CTL.INTR_SET */ 317 #define FLASHC_FM_CTL_V2_INTR_SET_TIMER_EXPIRED_Pos 0UL 318 #define FLASHC_FM_CTL_V2_INTR_SET_TIMER_EXPIRED_Msk 0x1UL 319 /* FLASHC_FM_CTL.INTR_MASK */ 320 #define FLASHC_FM_CTL_V2_INTR_MASK_TIMER_EXPIRED_Pos 0UL 321 #define FLASHC_FM_CTL_V2_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL 322 /* FLASHC_FM_CTL.INTR_MASKED */ 323 #define FLASHC_FM_CTL_V2_INTR_MASKED_TIMER_EXPIRED_Pos 0UL 324 #define FLASHC_FM_CTL_V2_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL 325 /* FLASHC_FM_CTL.CAL_CTL0 */ 326 #define FLASHC_FM_CTL_V2_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL 327 #define FLASHC_FM_CTL_V2_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL 328 #define FLASHC_FM_CTL_V2_CAL_CTL0_CDAC_LO_HV_Pos 5UL 329 #define FLASHC_FM_CTL_V2_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL 330 #define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL 331 #define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL 332 #define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL 333 #define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL 334 #define FLASHC_FM_CTL_V2_CAL_CTL0_ICREF_TC_TRIM_LO_HV_Pos 16UL 335 #define FLASHC_FM_CTL_V2_CAL_CTL0_ICREF_TC_TRIM_LO_HV_Msk 0x70000UL 336 #define FLASHC_FM_CTL_V2_CAL_CTL0_IPREF_TRIMA_LO_HV_Pos 19UL 337 #define FLASHC_FM_CTL_V2_CAL_CTL0_IPREF_TRIMA_LO_HV_Msk 0x80000UL 338 /* FLASHC_FM_CTL.CAL_CTL1 */ 339 #define FLASHC_FM_CTL_V2_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL 340 #define FLASHC_FM_CTL_V2_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL 341 #define FLASHC_FM_CTL_V2_CAL_CTL1_CDAC_HI_HV_Pos 5UL 342 #define FLASHC_FM_CTL_V2_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL 343 #define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL 344 #define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL 345 #define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL 346 #define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL 347 #define FLASHC_FM_CTL_V2_CAL_CTL1_ICREF_TC_TRIM_HI_HV_Pos 16UL 348 #define FLASHC_FM_CTL_V2_CAL_CTL1_ICREF_TC_TRIM_HI_HV_Msk 0x70000UL 349 #define FLASHC_FM_CTL_V2_CAL_CTL1_IPREF_TRIMA_HI_HV_Pos 19UL 350 #define FLASHC_FM_CTL_V2_CAL_CTL1_IPREF_TRIMA_HI_HV_Msk 0x80000UL 351 /* FLASHC_FM_CTL.CAL_CTL2 */ 352 #define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL 353 #define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL 354 #define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 5UL 355 #define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x3E0UL 356 #define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_LO_HV_Pos 10UL 357 #define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_LO_HV_Msk 0x7C00UL 358 #define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_HI_HV_Pos 15UL 359 #define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_HI_HV_Msk 0xF8000UL 360 /* FLASHC_FM_CTL.CAL_CTL3 */ 361 #define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_TRIM_HV_Pos 0UL 362 #define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL 363 #define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL 364 #define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL 365 #define FLASHC_FM_CTL_V2_CAL_CTL3_VPROT_ACT_HV_Pos 5UL 366 #define FLASHC_FM_CTL_V2_CAL_CTL3_VPROT_ACT_HV_Msk 0x20UL 367 #define FLASHC_FM_CTL_V2_CAL_CTL3_IPREF_TC_HV_Pos 6UL 368 #define FLASHC_FM_CTL_V2_CAL_CTL3_IPREF_TC_HV_Msk 0x40UL 369 #define FLASHC_FM_CTL_V2_CAL_CTL3_VREF_SEL_HV_Pos 7UL 370 #define FLASHC_FM_CTL_V2_CAL_CTL3_VREF_SEL_HV_Msk 0x80UL 371 #define FLASHC_FM_CTL_V2_CAL_CTL3_IREF_SEL_HV_Pos 8UL 372 #define FLASHC_FM_CTL_V2_CAL_CTL3_IREF_SEL_HV_Msk 0x100UL 373 #define FLASHC_FM_CTL_V2_CAL_CTL3_REG_ACT_HV_Pos 9UL 374 #define FLASHC_FM_CTL_V2_CAL_CTL3_REG_ACT_HV_Msk 0x200UL 375 #define FLASHC_FM_CTL_V2_CAL_CTL3_FDIV_TRIM_HV_Pos 10UL 376 #define FLASHC_FM_CTL_V2_CAL_CTL3_FDIV_TRIM_HV_Msk 0xC00UL 377 #define FLASHC_FM_CTL_V2_CAL_CTL3_VDDHI_HV_Pos 12UL 378 #define FLASHC_FM_CTL_V2_CAL_CTL3_VDDHI_HV_Msk 0x1000UL 379 #define FLASHC_FM_CTL_V2_CAL_CTL3_TURBO_PULSEW_HV_Pos 13UL 380 #define FLASHC_FM_CTL_V2_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x6000UL 381 #define FLASHC_FM_CTL_V2_CAL_CTL3_BGLO_EN_HV_Pos 15UL 382 #define FLASHC_FM_CTL_V2_CAL_CTL3_BGLO_EN_HV_Msk 0x8000UL 383 #define FLASHC_FM_CTL_V2_CAL_CTL3_BGHI_EN_HV_Pos 16UL 384 #define FLASHC_FM_CTL_V2_CAL_CTL3_BGHI_EN_HV_Msk 0x10000UL 385 #define FLASHC_FM_CTL_V2_CAL_CTL3_CL_ISO_DIS_HV_Pos 17UL 386 #define FLASHC_FM_CTL_V2_CAL_CTL3_CL_ISO_DIS_HV_Msk 0x20000UL 387 #define FLASHC_FM_CTL_V2_CAL_CTL3_R_GRANT_EN_HV_Pos 18UL 388 #define FLASHC_FM_CTL_V2_CAL_CTL3_R_GRANT_EN_HV_Msk 0x40000UL 389 #define FLASHC_FM_CTL_V2_CAL_CTL3_LP_ULP_SW_HV_Pos 19UL 390 #define FLASHC_FM_CTL_V2_CAL_CTL3_LP_ULP_SW_HV_Msk 0x80000UL 391 /* FLASHC_FM_CTL.CAL_CTL4 */ 392 #define FLASHC_FM_CTL_V2_CAL_CTL4_VLIM_TRIM_ULP_HV_Pos 0UL 393 #define FLASHC_FM_CTL_V2_CAL_CTL4_VLIM_TRIM_ULP_HV_Msk 0x3UL 394 #define FLASHC_FM_CTL_V2_CAL_CTL4_IDAC_ULP_HV_Pos 2UL 395 #define FLASHC_FM_CTL_V2_CAL_CTL4_IDAC_ULP_HV_Msk 0x3CUL 396 #define FLASHC_FM_CTL_V2_CAL_CTL4_SDAC_ULP_HV_Pos 6UL 397 #define FLASHC_FM_CTL_V2_CAL_CTL4_SDAC_ULP_HV_Msk 0xC0UL 398 #define FLASHC_FM_CTL_V2_CAL_CTL4_ITIM_ULP_HV_Pos 8UL 399 #define FLASHC_FM_CTL_V2_CAL_CTL4_ITIM_ULP_HV_Msk 0x1F00UL 400 #define FLASHC_FM_CTL_V2_CAL_CTL4_FM_READY_DEL_ULP_HV_Pos 13UL 401 #define FLASHC_FM_CTL_V2_CAL_CTL4_FM_READY_DEL_ULP_HV_Msk 0x6000UL 402 #define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE451_ULP_HV_Pos 15UL 403 #define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE451_ULP_HV_Msk 0x8000UL 404 #define FLASHC_FM_CTL_V2_CAL_CTL4_READY_RESTART_N_HV_Pos 16UL 405 #define FLASHC_FM_CTL_V2_CAL_CTL4_READY_RESTART_N_HV_Msk 0x10000UL 406 #define FLASHC_FM_CTL_V2_CAL_CTL4_VBST_S_DIS_HV_Pos 17UL 407 #define FLASHC_FM_CTL_V2_CAL_CTL4_VBST_S_DIS_HV_Msk 0x20000UL 408 #define FLASHC_FM_CTL_V2_CAL_CTL4_AUTO_HVPULSE_HV_Pos 18UL 409 #define FLASHC_FM_CTL_V2_CAL_CTL4_AUTO_HVPULSE_HV_Msk 0x40000UL 410 #define FLASHC_FM_CTL_V2_CAL_CTL4_UGB_EN_HV_Pos 19UL 411 #define FLASHC_FM_CTL_V2_CAL_CTL4_UGB_EN_HV_Msk 0x80000UL 412 /* FLASHC_FM_CTL.CAL_CTL5 */ 413 #define FLASHC_FM_CTL_V2_CAL_CTL5_VLIM_TRIM_LP_HV_Pos 0UL 414 #define FLASHC_FM_CTL_V2_CAL_CTL5_VLIM_TRIM_LP_HV_Msk 0x3UL 415 #define FLASHC_FM_CTL_V2_CAL_CTL5_IDAC_LP_HV_Pos 2UL 416 #define FLASHC_FM_CTL_V2_CAL_CTL5_IDAC_LP_HV_Msk 0x3CUL 417 #define FLASHC_FM_CTL_V2_CAL_CTL5_SDAC_LP_HV_Pos 6UL 418 #define FLASHC_FM_CTL_V2_CAL_CTL5_SDAC_LP_HV_Msk 0xC0UL 419 #define FLASHC_FM_CTL_V2_CAL_CTL5_ITIM_LP_HV_Pos 8UL 420 #define FLASHC_FM_CTL_V2_CAL_CTL5_ITIM_LP_HV_Msk 0x1F00UL 421 #define FLASHC_FM_CTL_V2_CAL_CTL5_FM_READY_DEL_LP_HV_Pos 13UL 422 #define FLASHC_FM_CTL_V2_CAL_CTL5_FM_READY_DEL_LP_HV_Msk 0x6000UL 423 #define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE451_LP_HV_Pos 15UL 424 #define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE451_LP_HV_Msk 0x8000UL 425 #define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE52_HV_Pos 16UL 426 #define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE52_HV_Msk 0x30000UL 427 #define FLASHC_FM_CTL_V2_CAL_CTL5_AMUX_SEL_HV_Pos 18UL 428 #define FLASHC_FM_CTL_V2_CAL_CTL5_AMUX_SEL_HV_Msk 0xC0000UL 429 /* FLASHC_FM_CTL.CAL_CTL6 */ 430 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Pos 0UL 431 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Msk 0x1UL 432 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Pos 1UL 433 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Msk 0xEUL 434 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Pos 4UL 435 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Msk 0x70UL 436 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Pos 7UL 437 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Msk 0x180UL 438 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_ULP_HV_Pos 9UL 439 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_ULP_HV_Msk 0x200UL 440 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Pos 10UL 441 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Msk 0x400UL 442 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Pos 11UL 443 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Msk 0x3800UL 444 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Pos 14UL 445 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Msk 0x1C000UL 446 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Pos 17UL 447 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Msk 0x60000UL 448 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_LP_HV_Pos 19UL 449 #define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_LP_HV_Msk 0x80000UL 450 /* FLASHC_FM_CTL.CAL_CTL7 */ 451 #define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_CLK_SEL_HV_Pos 0UL 452 #define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_CLK_SEL_HV_Msk 0x3UL 453 #define FLASHC_FM_CTL_V2_CAL_CTL7_FM_ACTIVE_HV_Pos 2UL 454 #define FLASHC_FM_CTL_V2_CAL_CTL7_FM_ACTIVE_HV_Msk 0x4UL 455 #define FLASHC_FM_CTL_V2_CAL_CTL7_TURBO_EXT_HV_Pos 3UL 456 #define FLASHC_FM_CTL_V2_CAL_CTL7_TURBO_EXT_HV_Msk 0x8UL 457 #define FLASHC_FM_CTL_V2_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Pos 4UL 458 #define FLASHC_FM_CTL_V2_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Msk 0x10UL 459 #define FLASHC_FM_CTL_V2_CAL_CTL7_FM_READY_DIS_HV_Pos 5UL 460 #define FLASHC_FM_CTL_V2_CAL_CTL7_FM_READY_DIS_HV_Msk 0x20UL 461 #define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_EN_ALL_HV_Pos 6UL 462 #define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_EN_ALL_HV_Msk 0x40UL 463 #define FLASHC_FM_CTL_V2_CAL_CTL7_DISABLE_LOAD_ONCE_HV_Pos 7UL 464 #define FLASHC_FM_CTL_V2_CAL_CTL7_DISABLE_LOAD_ONCE_HV_Msk 0x80UL 465 #define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_HV_Pos 8UL 466 #define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_HV_Msk 0x300UL 467 #define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_ULP_HV_Pos 10UL 468 #define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_ULP_HV_Msk 0x7C00UL 469 #define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_LP_HV_Pos 15UL 470 #define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_LP_HV_Msk 0xF8000UL 471 /* FLASHC_FM_CTL.RED_CTL01 */ 472 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_0_Pos 0UL 473 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_0_Msk 0xFFUL 474 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_0_Pos 8UL 475 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_0_Msk 0x100UL 476 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_1_Pos 16UL 477 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL 478 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_1_Pos 24UL 479 #define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_1_Msk 0x1000000UL 480 /* FLASHC_FM_CTL.RED_CTL23 */ 481 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_2_Pos 0UL 482 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_2_Msk 0xFFUL 483 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_2_Pos 8UL 484 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_2_Msk 0x100UL 485 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_3_Pos 16UL 486 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL 487 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_3_Pos 24UL 488 #define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_3_Msk 0x1000000UL 489 /* FLASHC_FM_CTL.RED_CTL45 */ 490 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_4_Pos 0UL 491 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_4_Msk 0xFFUL 492 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_4_Pos 8UL 493 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_4_Msk 0x100UL 494 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_5_Pos 16UL 495 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_5_Msk 0xFF0000UL 496 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_5_Pos 24UL 497 #define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_5_Msk 0x1000000UL 498 /* FLASHC_FM_CTL.RED_CTL67 */ 499 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_6_Pos 0UL 500 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_6_Msk 0xFFUL 501 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_6_Pos 8UL 502 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_6_Msk 0x100UL 503 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_7_Pos 16UL 504 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_7_Msk 0xFF0000UL 505 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_7_Pos 24UL 506 #define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_7_Msk 0x1000000UL 507 /* FLASHC_FM_CTL.RED_CTL_SM01 */ 508 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL 509 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL 510 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM0_Pos 8UL 511 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL 512 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL 513 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL 514 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM1_Pos 24UL 515 #define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL 516 /* FLASHC_FM_CTL.RGRANT_DELAY_PRG */ 517 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ12_Pos 0UL 518 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ12_Msk 0xFFUL 519 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ23_Pos 8UL 520 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_PRG_SEQ23_Msk 0xFF00UL 521 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_SEQ30_Pos 16UL 522 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_SEQ30_Msk 0xFF0000UL 523 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_CLK_Pos 24UL 524 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_RGRANT_DELAY_CLK_Msk 0xF000000UL 525 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_HV_PARAMS_LOADED_Pos 31UL 526 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_PRG_HV_PARAMS_LOADED_Msk 0x80000000UL 527 /* FLASHC_FM_CTL.PW_SEQ12 */ 528 #define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ1_Pos 0UL 529 #define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ1_Msk 0xFFFFUL 530 #define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ2_PRE_Pos 16UL 531 #define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ2_PRE_Msk 0xFFFF0000UL 532 /* FLASHC_FM_CTL.PW_SEQ23 */ 533 #define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ2_POST_Pos 0UL 534 #define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ2_POST_Msk 0xFFFFUL 535 #define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ3_Pos 16UL 536 #define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ3_Msk 0xFFFF0000UL 537 /* FLASHC_FM_CTL.RGRANT_SCALE_ERS */ 538 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ01_Pos 0UL 539 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ01_Msk 0x3UL 540 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ12_Pos 2UL 541 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ12_Msk 0xCUL 542 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ23_Pos 4UL 543 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_SEQ23_Msk 0x30UL 544 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEON_Pos 6UL 545 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEON_Msk 0xC0UL 546 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEOFF_Pos 8UL 547 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_SCALE_ERS_PEOFF_Msk 0x300UL 548 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEON_Pos 16UL 549 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEON_Msk 0xFF0000UL 550 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEOFF_Pos 24UL 551 #define FLASHC_FM_CTL_V2_RGRANT_SCALE_ERS_RGRANT_DELAY_ERS_PEOFF_Msk 0xFF000000UL 552 /* FLASHC_FM_CTL.RGRANT_DELAY_ERS */ 553 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ01_Pos 0UL 554 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ01_Msk 0xFFUL 555 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ12_Pos 8UL 556 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ12_Msk 0xFF00UL 557 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ23_Pos 16UL 558 #define FLASHC_FM_CTL_V2_RGRANT_DELAY_ERS_RGRANT_DELAY_ERS_SEQ23_Msk 0xFF0000UL 559 /* FLASHC_FM_CTL.FM_PL_WRDATA_ALL */ 560 #define FLASHC_FM_CTL_V2_FM_PL_WRDATA_ALL_DATA32_Pos 0UL 561 #define FLASHC_FM_CTL_V2_FM_PL_WRDATA_ALL_DATA32_Msk 0xFFFFFFFFUL 562 /* FLASHC_FM_CTL.FM_PL_DATA */ 563 #define FLASHC_FM_CTL_V2_FM_PL_DATA_DATA32_Pos 0UL 564 #define FLASHC_FM_CTL_V2_FM_PL_DATA_DATA32_Msk 0xFFFFFFFFUL 565 /* FLASHC_FM_CTL.FM_MEM_DATA */ 566 #define FLASHC_FM_CTL_V2_FM_MEM_DATA_DATA32_Pos 0UL 567 #define FLASHC_FM_CTL_V2_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL 568 569 570 /* FLASHC.FLASH_CTL */ 571 #define FLASHC_V2_FLASH_CTL_MAIN_WS_Pos 0UL 572 #define FLASHC_V2_FLASH_CTL_MAIN_WS_Msk 0xFUL 573 #define FLASHC_V2_FLASH_CTL_MAIN_MAP_Pos 8UL 574 #define FLASHC_V2_FLASH_CTL_MAIN_MAP_Msk 0x100UL 575 #define FLASHC_V2_FLASH_CTL_WORK_MAP_Pos 9UL 576 #define FLASHC_V2_FLASH_CTL_WORK_MAP_Msk 0x200UL 577 #define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Pos 12UL 578 #define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Msk 0x1000UL 579 #define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Pos 13UL 580 #define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Msk 0x2000UL 581 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Pos 16UL 582 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Msk 0x10000UL 583 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 17UL 584 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 0x20000UL 585 #define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Pos 18UL 586 #define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Msk 0x40000UL 587 #define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Pos 20UL 588 #define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Msk 0x100000UL 589 #define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Pos 21UL 590 #define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Msk 0x200000UL 591 #define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Pos 22UL 592 #define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Msk 0x400000UL 593 /* FLASHC.FLASH_PWR_CTL */ 594 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Pos 0UL 595 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Msk 0x1UL 596 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL 597 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL 598 /* FLASHC.FLASH_CMD */ 599 #define FLASHC_V2_FLASH_CMD_INV_Pos 0UL 600 #define FLASHC_V2_FLASH_CMD_INV_Msk 0x1UL 601 #define FLASHC_V2_FLASH_CMD_BUFF_INV_Pos 1UL 602 #define FLASHC_V2_FLASH_CMD_BUFF_INV_Msk 0x2UL 603 /* FLASHC.ECC_CTL */ 604 #define FLASHC_V2_ECC_CTL_WORD_ADDR_Pos 0UL 605 #define FLASHC_V2_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL 606 #define FLASHC_V2_ECC_CTL_PARITY_Pos 24UL 607 #define FLASHC_V2_ECC_CTL_PARITY_Msk 0xFF000000UL 608 /* FLASHC.FM_SRAM_ECC_CTL0 */ 609 #define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Pos 0UL 610 #define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Msk 0xFFFFFFFFUL 611 /* FLASHC.FM_SRAM_ECC_CTL1 */ 612 #define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Pos 0UL 613 #define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Msk 0x7FUL 614 /* FLASHC.FM_SRAM_ECC_CTL2 */ 615 #define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Pos 0UL 616 #define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Msk 0xFFFFFFFFUL 617 /* FLASHC.FM_SRAM_ECC_CTL3 */ 618 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Pos 0UL 619 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Msk 0x1UL 620 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Pos 4UL 621 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Msk 0x10UL 622 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Pos 8UL 623 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Msk 0x100UL 624 /* FLASHC.CM0_CA_CTL0 */ 625 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Pos 0UL 626 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Msk 0x1UL 627 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL 628 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL 629 #define FLASHC_V2_CM0_CA_CTL0_WAY_Pos 16UL 630 #define FLASHC_V2_CM0_CA_CTL0_WAY_Msk 0x30000UL 631 #define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Pos 24UL 632 #define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL 633 #define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Pos 30UL 634 #define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL 635 #define FLASHC_V2_CM0_CA_CTL0_CA_EN_Pos 31UL 636 #define FLASHC_V2_CM0_CA_CTL0_CA_EN_Msk 0x80000000UL 637 /* FLASHC.CM0_CA_CTL1 */ 638 #define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Pos 0UL 639 #define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL 640 #define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL 641 #define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 642 /* FLASHC.CM0_CA_CTL2 */ 643 #define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL 644 #define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 645 /* FLASHC.CM0_CA_STATUS0 */ 646 #define FLASHC_V2_CM0_CA_STATUS0_VALID32_Pos 0UL 647 #define FLASHC_V2_CM0_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL 648 /* FLASHC.CM0_CA_STATUS1 */ 649 #define FLASHC_V2_CM0_CA_STATUS1_TAG_Pos 0UL 650 #define FLASHC_V2_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 651 /* FLASHC.CM0_CA_STATUS2 */ 652 #define FLASHC_V2_CM0_CA_STATUS2_LRU_Pos 0UL 653 #define FLASHC_V2_CM0_CA_STATUS2_LRU_Msk 0x3FUL 654 /* FLASHC.CM0_STATUS */ 655 #define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 656 #define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 657 #define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Pos 1UL 658 #define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 659 /* FLASHC.CM4_CA_CTL0 */ 660 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Pos 0UL 661 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Msk 0x1UL 662 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL 663 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL 664 #define FLASHC_V2_CM4_CA_CTL0_WAY_Pos 16UL 665 #define FLASHC_V2_CM4_CA_CTL0_WAY_Msk 0x30000UL 666 #define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Pos 24UL 667 #define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL 668 #define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Pos 30UL 669 #define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL 670 #define FLASHC_V2_CM4_CA_CTL0_CA_EN_Pos 31UL 671 #define FLASHC_V2_CM4_CA_CTL0_CA_EN_Msk 0x80000000UL 672 /* FLASHC.CM4_CA_CTL1 */ 673 #define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Pos 0UL 674 #define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL 675 #define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL 676 #define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 677 /* FLASHC.CM4_CA_CTL2 */ 678 #define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL 679 #define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 680 /* FLASHC.CM4_CA_STATUS0 */ 681 #define FLASHC_V2_CM4_CA_STATUS0_VALID32_Pos 0UL 682 #define FLASHC_V2_CM4_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL 683 /* FLASHC.CM4_CA_STATUS1 */ 684 #define FLASHC_V2_CM4_CA_STATUS1_TAG_Pos 0UL 685 #define FLASHC_V2_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 686 /* FLASHC.CM4_CA_STATUS2 */ 687 #define FLASHC_V2_CM4_CA_STATUS2_LRU_Pos 0UL 688 #define FLASHC_V2_CM4_CA_STATUS2_LRU_Msk 0x3FUL 689 /* FLASHC.CM4_STATUS */ 690 #define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 691 #define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 692 #define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Pos 1UL 693 #define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 694 /* FLASHC.CRYPTO_BUFF_CTL */ 695 #define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL 696 #define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL 697 /* FLASHC.DW0_BUFF_CTL */ 698 #define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Pos 30UL 699 #define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 700 /* FLASHC.DW1_BUFF_CTL */ 701 #define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Pos 30UL 702 #define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 703 /* FLASHC.DMAC_BUFF_CTL */ 704 #define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Pos 30UL 705 #define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Msk 0x40000000UL 706 /* FLASHC.EXT_MS0_BUFF_CTL */ 707 #define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL 708 #define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 709 /* FLASHC.EXT_MS1_BUFF_CTL */ 710 #define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL 711 #define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 712 713 714 #endif /* _CYIP_FLASHC_V2_H_ */ 715 716 717 /* [] END OF FILE */ 718
