1 /***************************************************************************//** 2 * \file cyip_dac.h 3 * 4 * \brief 5 * DAC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_DAC_H_ 28 #define _CYIP_DAC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * DAC 34 *******************************************************************************/ 35 36 #define DAC_SECTION_SIZE 0x00000100UL 37 38 /** 39 * \brief DAC (DAC) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 43 __IOM uint32_t IF_CTL; /*!< 0x00000004 Interface Control */ 44 __IOM uint32_t COUNT; /*!< 0x00000008 Count */ 45 __IM uint32_t RESERVED; 46 __IM uint32_t STATUS; /*!< 0x00000010 Status */ 47 __IM uint32_t RESERVED1[27]; 48 __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000080 TX FIFO control */ 49 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000084 TX FIFO status */ 50 __OM uint32_t TX_FIFO_WR; /*!< 0x00000088 TX FIFO write */ 51 __IM uint32_t RESERVED2[13]; 52 __IOM uint32_t INTR_TX; /*!< 0x000000C0 Interrupt */ 53 __IOM uint32_t INTR_TX_SET; /*!< 0x000000C4 Interrupt set */ 54 __IOM uint32_t INTR_TX_MASK; /*!< 0x000000C8 Interrupt mask */ 55 __IM uint32_t INTR_TX_MASKED; /*!< 0x000000CC Interrupt masked */ 56 } DAC_Type; /*!< Size = 208 (0xD0) */ 57 58 59 /* DAC.CTL */ 60 #define DAC_CTL_ENABLED_Pos 31UL 61 #define DAC_CTL_ENABLED_Msk 0x80000000UL 62 /* DAC.IF_CTL */ 63 #define DAC_IF_CTL_CLOCK_DIV_Pos 0UL 64 #define DAC_IF_CTL_CLOCK_DIV_Msk 0xFFUL 65 #define DAC_IF_CTL_CLOCK_SEL_Pos 8UL 66 #define DAC_IF_CTL_CLOCK_SEL_Msk 0x700UL 67 #define DAC_IF_CTL_FS_SEL_Pos 16UL 68 #define DAC_IF_CTL_FS_SEL_Msk 0x30000UL 69 #define DAC_IF_CTL_LDATA_POLARITY_Pos 24UL 70 #define DAC_IF_CTL_LDATA_POLARITY_Msk 0x1000000UL 71 #define DAC_IF_CTL_RDATA_POLARITY_Pos 25UL 72 #define DAC_IF_CTL_RDATA_POLARITY_Msk 0x2000000UL 73 #define DAC_IF_CTL_LDATA_SEL_Pos 26UL 74 #define DAC_IF_CTL_LDATA_SEL_Msk 0x4000000UL 75 #define DAC_IF_CTL_RDATA_SEL_Pos 27UL 76 #define DAC_IF_CTL_RDATA_SEL_Msk 0x8000000UL 77 #define DAC_IF_CTL_SW_OVERRIDE_FAST_RAMP_EN_Pos 30UL 78 #define DAC_IF_CTL_SW_OVERRIDE_FAST_RAMP_EN_Msk 0x40000000UL 79 #define DAC_IF_CTL_DAC_EN_Pos 31UL 80 #define DAC_IF_CTL_DAC_EN_Msk 0x80000000UL 81 /* DAC.COUNT */ 82 #define DAC_COUNT_COUNT_1MS_Pos 0UL 83 #define DAC_COUNT_COUNT_1MS_Msk 0xFFFFUL 84 #define DAC_COUNT_FAST_RAMP_COUNT_IN_MS_Pos 16UL 85 #define DAC_COUNT_FAST_RAMP_COUNT_IN_MS_Msk 0xFF0000UL 86 #define DAC_COUNT_COMP_RAMP_COUNT_IN_MS_Pos 24UL 87 #define DAC_COUNT_COMP_RAMP_COUNT_IN_MS_Msk 0xFF000000UL 88 /* DAC.STATUS */ 89 #define DAC_STATUS_DAC_BUSY_Pos 0UL 90 #define DAC_STATUS_DAC_BUSY_Msk 0x1UL 91 #define DAC_STATUS_FAST_RAMP_DONE_Pos 16UL 92 #define DAC_STATUS_FAST_RAMP_DONE_Msk 0x10000UL 93 #define DAC_STATUS_COMP_RAMP_DONE_Pos 17UL 94 #define DAC_STATUS_COMP_RAMP_DONE_Msk 0x20000UL 95 /* DAC.TX_FIFO_CTL */ 96 #define DAC_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 97 #define DAC_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x3FUL 98 #define DAC_TX_FIFO_CTL_MUTE_Pos 16UL 99 #define DAC_TX_FIFO_CTL_MUTE_Msk 0x10000UL 100 #define DAC_TX_FIFO_CTL_FREEZE_Pos 17UL 101 #define DAC_TX_FIFO_CTL_FREEZE_Msk 0x20000UL 102 #define DAC_TX_FIFO_CTL_ACTIVE_Pos 18UL 103 #define DAC_TX_FIFO_CTL_ACTIVE_Msk 0x40000UL 104 /* DAC.TX_FIFO_STATUS */ 105 #define DAC_TX_FIFO_STATUS_USED_Pos 0UL 106 #define DAC_TX_FIFO_STATUS_USED_Msk 0x7FUL 107 #define DAC_TX_FIFO_STATUS_RD_PTR_Pos 16UL 108 #define DAC_TX_FIFO_STATUS_RD_PTR_Msk 0x3F0000UL 109 #define DAC_TX_FIFO_STATUS_WR_PTR_Pos 24UL 110 #define DAC_TX_FIFO_STATUS_WR_PTR_Msk 0x3F000000UL 111 /* DAC.TX_FIFO_WR */ 112 #define DAC_TX_FIFO_WR_DATA_Pos 0UL 113 #define DAC_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL 114 /* DAC.INTR_TX */ 115 #define DAC_INTR_TX_FIFO_TRIGGER_Pos 0UL 116 #define DAC_INTR_TX_FIFO_TRIGGER_Msk 0x1UL 117 #define DAC_INTR_TX_FIFO_OVERFLOW_Pos 1UL 118 #define DAC_INTR_TX_FIFO_OVERFLOW_Msk 0x2UL 119 #define DAC_INTR_TX_FIFO_UNDERFLOW_Pos 2UL 120 #define DAC_INTR_TX_FIFO_UNDERFLOW_Msk 0x4UL 121 #define DAC_INTR_TX_FAST_RAMP_COMPLETE_Pos 16UL 122 #define DAC_INTR_TX_FAST_RAMP_COMPLETE_Msk 0x10000UL 123 #define DAC_INTR_TX_RAMP_COMPLETE_Pos 17UL 124 #define DAC_INTR_TX_RAMP_COMPLETE_Msk 0x20000UL 125 /* DAC.INTR_TX_SET */ 126 #define DAC_INTR_TX_SET_FIFO_TRIGGER_Pos 0UL 127 #define DAC_INTR_TX_SET_FIFO_TRIGGER_Msk 0x1UL 128 #define DAC_INTR_TX_SET_FIFO_OVERFLOW_Pos 1UL 129 #define DAC_INTR_TX_SET_FIFO_OVERFLOW_Msk 0x2UL 130 #define DAC_INTR_TX_SET_FIFO_UNDERFLOW_Pos 2UL 131 #define DAC_INTR_TX_SET_FIFO_UNDERFLOW_Msk 0x4UL 132 #define DAC_INTR_TX_SET_FAST_RAMP_COMPLETE_Pos 16UL 133 #define DAC_INTR_TX_SET_FAST_RAMP_COMPLETE_Msk 0x10000UL 134 #define DAC_INTR_TX_SET_RAMP_COMPLETE_Pos 17UL 135 #define DAC_INTR_TX_SET_RAMP_COMPLETE_Msk 0x20000UL 136 /* DAC.INTR_TX_MASK */ 137 #define DAC_INTR_TX_MASK_FIFO_TRIGGER_Pos 0UL 138 #define DAC_INTR_TX_MASK_FIFO_TRIGGER_Msk 0x1UL 139 #define DAC_INTR_TX_MASK_FIFO_OVERFLOW_Pos 1UL 140 #define DAC_INTR_TX_MASK_FIFO_OVERFLOW_Msk 0x2UL 141 #define DAC_INTR_TX_MASK_FIFO_UNDERFLOW_Pos 2UL 142 #define DAC_INTR_TX_MASK_FIFO_UNDERFLOW_Msk 0x4UL 143 #define DAC_INTR_TX_MASK_FAST_RAMP_COMPLETE_Pos 16UL 144 #define DAC_INTR_TX_MASK_FAST_RAMP_COMPLETE_Msk 0x10000UL 145 #define DAC_INTR_TX_MASK_RAMP_COMPLETE_Pos 17UL 146 #define DAC_INTR_TX_MASK_RAMP_COMPLETE_Msk 0x20000UL 147 /* DAC.INTR_TX_MASKED */ 148 #define DAC_INTR_TX_MASKED_FIFO_TRIGGER_Pos 0UL 149 #define DAC_INTR_TX_MASKED_FIFO_TRIGGER_Msk 0x1UL 150 #define DAC_INTR_TX_MASKED_FIFO_OVERFLOW_Pos 1UL 151 #define DAC_INTR_TX_MASKED_FIFO_OVERFLOW_Msk 0x2UL 152 #define DAC_INTR_TX_MASKED_FIFO_UNDERFLOW_Pos 2UL 153 #define DAC_INTR_TX_MASKED_FIFO_UNDERFLOW_Msk 0x4UL 154 #define DAC_INTR_TX_MASKED_FAST_RAMP_COMPLETE_Pos 16UL 155 #define DAC_INTR_TX_MASKED_FAST_RAMP_COMPLETE_Msk 0x10000UL 156 #define DAC_INTR_TX_MASKED_RAMP_COMPLETE_Pos 17UL 157 #define DAC_INTR_TX_MASKED_RAMP_COMPLETE_Msk 0x20000UL 158 159 160 #endif /* _CYIP_DAC_H_ */ 161 162 163 /* [] END OF FILE */ 164
