1 /***************************************************************************//** 2 * \file cyip_cxpi.h 3 * 4 * \brief 5 * CXPI IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CXPI_H_ 28 #define _CYIP_CXPI_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CXPI 34 *******************************************************************************/ 35 36 #define CXPI_CH_SECTION_SIZE 0x00000100UL 37 #define CXPI_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief CXPI channel structure (CXPI_CH) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL0; /*!< 0x00000000 Control 0 */ 44 __IOM uint32_t CTL1; /*!< 0x00000004 Control 1 */ 45 __IOM uint32_t CTL2; /*!< 0x00000008 Control 2 */ 46 __IM uint32_t STATUS; /*!< 0x0000000C Status */ 47 __IOM uint32_t CMD; /*!< 0x00000010 Command */ 48 __IM uint32_t RESERVED[11]; 49 __IOM uint32_t TX_RX_STATUS; /*!< 0x00000040 TX/RX status */ 50 __IM uint32_t RESERVED1[3]; 51 __IOM uint32_t TXPID_FI; /*!< 0x00000050 TXPID and Frame Information */ 52 __IM uint32_t RXPID_FI; /*!< 0x00000054 RXPID and Frame Information */ 53 __IM uint32_t CRC; /*!< 0x00000058 CRC */ 54 __IM uint32_t RESERVED2[9]; 55 __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000080 TX FIFO control */ 56 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000084 TX FIFO status */ 57 __OM uint32_t TX_FIFO_WR; /*!< 0x00000088 TX FIFO write */ 58 __IM uint32_t RESERVED3[5]; 59 __IOM uint32_t RX_FIFO_CTL; /*!< 0x000000A0 RX FIFO control */ 60 __IM uint32_t RX_FIFO_STATUS; /*!< 0x000000A4 RX FIFO status */ 61 __IM uint32_t RX_FIFO_RD; /*!< 0x000000A8 RX FIFO read */ 62 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x000000AC RX FIFO silent read */ 63 __IM uint32_t RESERVED4[4]; 64 __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */ 65 __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */ 66 __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */ 67 __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */ 68 __IM uint32_t RESERVED5[12]; 69 } CXPI_CH_V1_Type; /*!< Size = 256 (0x100) */ 70 71 /** 72 * \brief CXPI (CXPI) 73 */ 74 typedef struct { 75 __IOM uint32_t ERROR_CTL; /*!< 0x00000000 Error control */ 76 __IOM uint32_t TEST_CTL; /*!< 0x00000004 Test control */ 77 __IM uint32_t RESERVED[8190]; 78 CXPI_CH_V1_Type CH[4]; /*!< 0x00008000 CXPI channel structure */ 79 } CXPI_V1_Type; /*!< Size = 33792 (0x8400) */ 80 81 82 /* CXPI_CH.CTL0 */ 83 #define CXPI_CH_CTL0_MODE_Pos 0UL 84 #define CXPI_CH_CTL0_MODE_Msk 0x1UL 85 #define CXPI_CH_CTL0_AUTO_EN_Pos 4UL 86 #define CXPI_CH_CTL0_AUTO_EN_Msk 0x10UL 87 #define CXPI_CH_CTL0_RXPIDZERO_CHECK_EN_Pos 7UL 88 #define CXPI_CH_CTL0_RXPIDZERO_CHECK_EN_Msk 0x80UL 89 #define CXPI_CH_CTL0_FILTER_EN_Pos 8UL 90 #define CXPI_CH_CTL0_FILTER_EN_Msk 0x100UL 91 #define CXPI_CH_CTL0_IFS_Pos 16UL 92 #define CXPI_CH_CTL0_IFS_Msk 0x1F0000UL 93 #define CXPI_CH_CTL0_IBS_Pos 21UL 94 #define CXPI_CH_CTL0_IBS_Msk 0x1E00000UL 95 #define CXPI_CH_CTL0_BIT_ERROR_IGNORE_Pos 27UL 96 #define CXPI_CH_CTL0_BIT_ERROR_IGNORE_Msk 0x8000000UL 97 #define CXPI_CH_CTL0_MASTER_Pos 30UL 98 #define CXPI_CH_CTL0_MASTER_Msk 0x40000000UL 99 #define CXPI_CH_CTL0_ENABLED_Pos 31UL 100 #define CXPI_CH_CTL0_ENABLED_Msk 0x80000000UL 101 /* CXPI_CH.CTL1 */ 102 #define CXPI_CH_CTL1_T_LOW1_Pos 0UL 103 #define CXPI_CH_CTL1_T_LOW1_Msk 0x1FFUL 104 #define CXPI_CH_CTL1_T_LOW0_Pos 12UL 105 #define CXPI_CH_CTL1_T_LOW0_Msk 0x1FF000UL 106 #define CXPI_CH_CTL1_T_OFFSET_Pos 22UL 107 #define CXPI_CH_CTL1_T_OFFSET_Msk 0x7FC00000UL 108 /* CXPI_CH.CTL2 */ 109 #define CXPI_CH_CTL2_RETRY_Pos 0UL 110 #define CXPI_CH_CTL2_RETRY_Msk 0x3UL 111 #define CXPI_CH_CTL2_T_WAKEUP_LENGTH_Pos 8UL 112 #define CXPI_CH_CTL2_T_WAKEUP_LENGTH_Msk 0x3F00UL 113 #define CXPI_CH_CTL2_TIMEOUT_LENGTH_Pos 16UL 114 #define CXPI_CH_CTL2_TIMEOUT_LENGTH_Msk 0xF0000UL 115 #define CXPI_CH_CTL2_TIMEOUT_SEL_Pos 30UL 116 #define CXPI_CH_CTL2_TIMEOUT_SEL_Msk 0xC0000000UL 117 /* CXPI_CH.STATUS */ 118 #define CXPI_CH_STATUS_RETRIES_COUNT_Pos 0UL 119 #define CXPI_CH_STATUS_RETRIES_COUNT_Msk 0x3UL 120 #define CXPI_CH_STATUS_HEADER_RESPONSE_Pos 4UL 121 #define CXPI_CH_STATUS_HEADER_RESPONSE_Msk 0x10UL 122 #define CXPI_CH_STATUS_TX_BUSY_Pos 8UL 123 #define CXPI_CH_STATUS_TX_BUSY_Msk 0x100UL 124 #define CXPI_CH_STATUS_RX_BUSY_Pos 9UL 125 #define CXPI_CH_STATUS_RX_BUSY_Msk 0x200UL 126 #define CXPI_CH_STATUS_TX_DONE_Pos 12UL 127 #define CXPI_CH_STATUS_TX_DONE_Msk 0x1000UL 128 #define CXPI_CH_STATUS_RX_DONE_Pos 13UL 129 #define CXPI_CH_STATUS_RX_DONE_Msk 0x2000UL 130 #define CXPI_CH_STATUS_TIMEOUT_Pos 18UL 131 #define CXPI_CH_STATUS_TIMEOUT_Msk 0x40000UL 132 #define CXPI_CH_STATUS_TX_HEADER_ARB_LOST_Pos 19UL 133 #define CXPI_CH_STATUS_TX_HEADER_ARB_LOST_Msk 0x80000UL 134 #define CXPI_CH_STATUS_TX_BIT_ERROR_Pos 20UL 135 #define CXPI_CH_STATUS_TX_BIT_ERROR_Msk 0x100000UL 136 #define CXPI_CH_STATUS_RX_CRC_ERROR_Pos 21UL 137 #define CXPI_CH_STATUS_RX_CRC_ERROR_Msk 0x200000UL 138 #define CXPI_CH_STATUS_RX_HEADER_PARITY_ERROR_Pos 22UL 139 #define CXPI_CH_STATUS_RX_HEADER_PARITY_ERROR_Msk 0x400000UL 140 #define CXPI_CH_STATUS_RX_DATA_LENGTH_ERROR_Pos 23UL 141 #define CXPI_CH_STATUS_RX_DATA_LENGTH_ERROR_Msk 0x800000UL 142 #define CXPI_CH_STATUS_TX_DATA_LENGTH_ERROR_Pos 24UL 143 #define CXPI_CH_STATUS_TX_DATA_LENGTH_ERROR_Msk 0x1000000UL 144 #define CXPI_CH_STATUS_RX_OVERFLOW_ERROR_Pos 25UL 145 #define CXPI_CH_STATUS_RX_OVERFLOW_ERROR_Msk 0x2000000UL 146 #define CXPI_CH_STATUS_TX_OVERFLOW_ERROR_Pos 26UL 147 #define CXPI_CH_STATUS_TX_OVERFLOW_ERROR_Msk 0x4000000UL 148 #define CXPI_CH_STATUS_RX_UNDERFLOW_ERROR_Pos 27UL 149 #define CXPI_CH_STATUS_RX_UNDERFLOW_ERROR_Msk 0x8000000UL 150 #define CXPI_CH_STATUS_TX_UNDERFLOW_ERROR_Pos 28UL 151 #define CXPI_CH_STATUS_TX_UNDERFLOW_ERROR_Msk 0x10000000UL 152 #define CXPI_CH_STATUS_RX_FRAME_ERROR_Pos 29UL 153 #define CXPI_CH_STATUS_RX_FRAME_ERROR_Msk 0x20000000UL 154 #define CXPI_CH_STATUS_TX_FRAME_ERROR_Pos 30UL 155 #define CXPI_CH_STATUS_TX_FRAME_ERROR_Msk 0x40000000UL 156 /* CXPI_CH.CMD */ 157 #define CXPI_CH_CMD_TX_HEADER_Pos 0UL 158 #define CXPI_CH_CMD_TX_HEADER_Msk 0x1UL 159 #define CXPI_CH_CMD_TX_RESPONSE_Pos 1UL 160 #define CXPI_CH_CMD_TX_RESPONSE_Msk 0x2UL 161 #define CXPI_CH_CMD_SLEEP_Pos 2UL 162 #define CXPI_CH_CMD_SLEEP_Msk 0x4UL 163 #define CXPI_CH_CMD_WAKE_TO_STANDBY_Pos 3UL 164 #define CXPI_CH_CMD_WAKE_TO_STANDBY_Msk 0x8UL 165 #define CXPI_CH_CMD_TX_WAKE_PULSE_Pos 4UL 166 #define CXPI_CH_CMD_TX_WAKE_PULSE_Msk 0x10UL 167 #define CXPI_CH_CMD_IFS_WAIT_Pos 5UL 168 #define CXPI_CH_CMD_IFS_WAIT_Msk 0x20UL 169 #define CXPI_CH_CMD_RX_HEADER_Pos 8UL 170 #define CXPI_CH_CMD_RX_HEADER_Msk 0x100UL 171 #define CXPI_CH_CMD_RX_RESPONSE_Pos 9UL 172 #define CXPI_CH_CMD_RX_RESPONSE_Msk 0x200UL 173 /* CXPI_CH.TX_RX_STATUS */ 174 #define CXPI_CH_TX_RX_STATUS_TX_IN_Pos 16UL 175 #define CXPI_CH_TX_RX_STATUS_TX_IN_Msk 0x10000UL 176 #define CXPI_CH_TX_RX_STATUS_RX_IN_Pos 17UL 177 #define CXPI_CH_TX_RX_STATUS_RX_IN_Msk 0x20000UL 178 #define CXPI_CH_TX_RX_STATUS_TX_OUT_Pos 24UL 179 #define CXPI_CH_TX_RX_STATUS_TX_OUT_Msk 0x1000000UL 180 #define CXPI_CH_TX_RX_STATUS_EN_OUT_Pos 26UL 181 #define CXPI_CH_TX_RX_STATUS_EN_OUT_Msk 0x4000000UL 182 /* CXPI_CH.TXPID_FI */ 183 #define CXPI_CH_TXPID_FI_PID_Pos 0UL 184 #define CXPI_CH_TXPID_FI_PID_Msk 0xFFUL 185 #define CXPI_CH_TXPID_FI_FI_Pos 8UL 186 #define CXPI_CH_TXPID_FI_FI_Msk 0xFF00UL 187 #define CXPI_CH_TXPID_FI_DLCEXT_Pos 16UL 188 #define CXPI_CH_TXPID_FI_DLCEXT_Msk 0xFF0000UL 189 /* CXPI_CH.RXPID_FI */ 190 #define CXPI_CH_RXPID_FI_PID_Pos 0UL 191 #define CXPI_CH_RXPID_FI_PID_Msk 0xFFUL 192 #define CXPI_CH_RXPID_FI_FI_Pos 8UL 193 #define CXPI_CH_RXPID_FI_FI_Msk 0xFF00UL 194 #define CXPI_CH_RXPID_FI_DLCEXT_Pos 16UL 195 #define CXPI_CH_RXPID_FI_DLCEXT_Msk 0xFF0000UL 196 /* CXPI_CH.CRC */ 197 #define CXPI_CH_CRC_RXCRC1_Pos 0UL 198 #define CXPI_CH_CRC_RXCRC1_Msk 0xFFUL 199 #define CXPI_CH_CRC_RXCRC2_Pos 8UL 200 #define CXPI_CH_CRC_RXCRC2_Msk 0xFF00UL 201 #define CXPI_CH_CRC_TXCRC1_Pos 16UL 202 #define CXPI_CH_CRC_TXCRC1_Msk 0xFF0000UL 203 #define CXPI_CH_CRC_TXCRC2_Pos 24UL 204 #define CXPI_CH_CRC_TXCRC2_Msk 0xFF000000UL 205 /* CXPI_CH.TX_FIFO_CTL */ 206 #define CXPI_CH_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 207 #define CXPI_CH_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x1FUL 208 #define CXPI_CH_TX_FIFO_CTL_CLEAR_Pos 16UL 209 #define CXPI_CH_TX_FIFO_CTL_CLEAR_Msk 0x10000UL 210 #define CXPI_CH_TX_FIFO_CTL_FREEZE_Pos 17UL 211 #define CXPI_CH_TX_FIFO_CTL_FREEZE_Msk 0x20000UL 212 /* CXPI_CH.TX_FIFO_STATUS */ 213 #define CXPI_CH_TX_FIFO_STATUS_USED_Pos 0UL 214 #define CXPI_CH_TX_FIFO_STATUS_USED_Msk 0x1FUL 215 #define CXPI_CH_TX_FIFO_STATUS_AVAIL_Pos 16UL 216 #define CXPI_CH_TX_FIFO_STATUS_AVAIL_Msk 0x1F0000UL 217 /* CXPI_CH.TX_FIFO_WR */ 218 #define CXPI_CH_TX_FIFO_WR_DATA_Pos 0UL 219 #define CXPI_CH_TX_FIFO_WR_DATA_Msk 0xFFUL 220 /* CXPI_CH.RX_FIFO_CTL */ 221 #define CXPI_CH_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 222 #define CXPI_CH_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x1FUL 223 #define CXPI_CH_RX_FIFO_CTL_CLEAR_Pos 16UL 224 #define CXPI_CH_RX_FIFO_CTL_CLEAR_Msk 0x10000UL 225 #define CXPI_CH_RX_FIFO_CTL_FREEZE_Pos 17UL 226 #define CXPI_CH_RX_FIFO_CTL_FREEZE_Msk 0x20000UL 227 /* CXPI_CH.RX_FIFO_STATUS */ 228 #define CXPI_CH_RX_FIFO_STATUS_USED_Pos 0UL 229 #define CXPI_CH_RX_FIFO_STATUS_USED_Msk 0x1FUL 230 #define CXPI_CH_RX_FIFO_STATUS_AVAIL_Pos 16UL 231 #define CXPI_CH_RX_FIFO_STATUS_AVAIL_Msk 0x1F0000UL 232 /* CXPI_CH.RX_FIFO_RD */ 233 #define CXPI_CH_RX_FIFO_RD_DATA_Pos 0UL 234 #define CXPI_CH_RX_FIFO_RD_DATA_Msk 0xFFUL 235 /* CXPI_CH.RX_FIFO_RD_SILENT */ 236 #define CXPI_CH_RX_FIFO_RD_SILENT_DATA_Pos 0UL 237 #define CXPI_CH_RX_FIFO_RD_SILENT_DATA_Msk 0xFFUL 238 /* CXPI_CH.INTR */ 239 #define CXPI_CH_INTR_TX_HEADER_DONE_Pos 0UL 240 #define CXPI_CH_INTR_TX_HEADER_DONE_Msk 0x1UL 241 #define CXPI_CH_INTR_TX_RESPONSE_DONE_Pos 1UL 242 #define CXPI_CH_INTR_TX_RESPONSE_DONE_Msk 0x2UL 243 #define CXPI_CH_INTR_TX_WAKEUP_DONE_Pos 3UL 244 #define CXPI_CH_INTR_TX_WAKEUP_DONE_Msk 0x8UL 245 #define CXPI_CH_INTR_TX_FIFO_TRIGGER_Pos 4UL 246 #define CXPI_CH_INTR_TX_FIFO_TRIGGER_Msk 0x10UL 247 #define CXPI_CH_INTR_RX_HEADER_DONE_Pos 8UL 248 #define CXPI_CH_INTR_RX_HEADER_DONE_Msk 0x100UL 249 #define CXPI_CH_INTR_RX_RESPONSE_DONE_Pos 9UL 250 #define CXPI_CH_INTR_RX_RESPONSE_DONE_Msk 0x200UL 251 #define CXPI_CH_INTR_RX_WAKEUP_DETECT_Pos 10UL 252 #define CXPI_CH_INTR_RX_WAKEUP_DETECT_Msk 0x400UL 253 #define CXPI_CH_INTR_RX_FIFO_TRIGGER_Pos 11UL 254 #define CXPI_CH_INTR_RX_FIFO_TRIGGER_Msk 0x800UL 255 #define CXPI_CH_INTR_RX_HEADER_PID_DONE_Pos 12UL 256 #define CXPI_CH_INTR_RX_HEADER_PID_DONE_Msk 0x1000UL 257 #define CXPI_CH_INTR_TXRX_COMPLETE_Pos 13UL 258 #define CXPI_CH_INTR_TXRX_COMPLETE_Msk 0x2000UL 259 #define CXPI_CH_INTR_TIMEOUT_Pos 18UL 260 #define CXPI_CH_INTR_TIMEOUT_Msk 0x40000UL 261 #define CXPI_CH_INTR_TX_HEADER_ARB_LOST_Pos 19UL 262 #define CXPI_CH_INTR_TX_HEADER_ARB_LOST_Msk 0x80000UL 263 #define CXPI_CH_INTR_TX_BIT_ERROR_Pos 20UL 264 #define CXPI_CH_INTR_TX_BIT_ERROR_Msk 0x100000UL 265 #define CXPI_CH_INTR_RX_CRC_ERROR_Pos 21UL 266 #define CXPI_CH_INTR_RX_CRC_ERROR_Msk 0x200000UL 267 #define CXPI_CH_INTR_RX_HEADER_PARITY_ERROR_Pos 22UL 268 #define CXPI_CH_INTR_RX_HEADER_PARITY_ERROR_Msk 0x400000UL 269 #define CXPI_CH_INTR_RX_DATA_LENGTH_ERROR_Pos 23UL 270 #define CXPI_CH_INTR_RX_DATA_LENGTH_ERROR_Msk 0x800000UL 271 #define CXPI_CH_INTR_TX_DATA_LENGTH_ERROR_Pos 24UL 272 #define CXPI_CH_INTR_TX_DATA_LENGTH_ERROR_Msk 0x1000000UL 273 #define CXPI_CH_INTR_RX_OVERFLOW_ERROR_Pos 25UL 274 #define CXPI_CH_INTR_RX_OVERFLOW_ERROR_Msk 0x2000000UL 275 #define CXPI_CH_INTR_TX_OVERFLOW_ERROR_Pos 26UL 276 #define CXPI_CH_INTR_TX_OVERFLOW_ERROR_Msk 0x4000000UL 277 #define CXPI_CH_INTR_RX_UNDERFLOW_ERROR_Pos 27UL 278 #define CXPI_CH_INTR_RX_UNDERFLOW_ERROR_Msk 0x8000000UL 279 #define CXPI_CH_INTR_TX_UNDERFLOW_ERROR_Pos 28UL 280 #define CXPI_CH_INTR_TX_UNDERFLOW_ERROR_Msk 0x10000000UL 281 #define CXPI_CH_INTR_RX_FRAME_ERROR_Pos 29UL 282 #define CXPI_CH_INTR_RX_FRAME_ERROR_Msk 0x20000000UL 283 #define CXPI_CH_INTR_TX_FRAME_ERROR_Pos 30UL 284 #define CXPI_CH_INTR_TX_FRAME_ERROR_Msk 0x40000000UL 285 /* CXPI_CH.INTR_SET */ 286 #define CXPI_CH_INTR_SET_TX_HEADER_DONE_Pos 0UL 287 #define CXPI_CH_INTR_SET_TX_HEADER_DONE_Msk 0x1UL 288 #define CXPI_CH_INTR_SET_TX_RESPONSE_DONE_Pos 1UL 289 #define CXPI_CH_INTR_SET_TX_RESPONSE_DONE_Msk 0x2UL 290 #define CXPI_CH_INTR_SET_TX_WAKEUP_DONE_Pos 3UL 291 #define CXPI_CH_INTR_SET_TX_WAKEUP_DONE_Msk 0x8UL 292 #define CXPI_CH_INTR_SET_TX_FIFO_TRIGGER_Pos 4UL 293 #define CXPI_CH_INTR_SET_TX_FIFO_TRIGGER_Msk 0x10UL 294 #define CXPI_CH_INTR_SET_RX_HEADER_DONE_Pos 8UL 295 #define CXPI_CH_INTR_SET_RX_HEADER_DONE_Msk 0x100UL 296 #define CXPI_CH_INTR_SET_RX_RESPONSE_DONE_Pos 9UL 297 #define CXPI_CH_INTR_SET_RX_RESPONSE_DONE_Msk 0x200UL 298 #define CXPI_CH_INTR_SET_RX_WAKEUP_DETECT_Pos 10UL 299 #define CXPI_CH_INTR_SET_RX_WAKEUP_DETECT_Msk 0x400UL 300 #define CXPI_CH_INTR_SET_RX_FIFO_TRIGGER_Pos 11UL 301 #define CXPI_CH_INTR_SET_RX_FIFO_TRIGGER_Msk 0x800UL 302 #define CXPI_CH_INTR_SET_RX_HEADER_PID_DONE_Pos 12UL 303 #define CXPI_CH_INTR_SET_RX_HEADER_PID_DONE_Msk 0x1000UL 304 #define CXPI_CH_INTR_SET_TXRX_COMPLETE_Pos 13UL 305 #define CXPI_CH_INTR_SET_TXRX_COMPLETE_Msk 0x2000UL 306 #define CXPI_CH_INTR_SET_TIMEOUT_Pos 18UL 307 #define CXPI_CH_INTR_SET_TIMEOUT_Msk 0x40000UL 308 #define CXPI_CH_INTR_SET_TX_HEADER_ARB_LOST_Pos 19UL 309 #define CXPI_CH_INTR_SET_TX_HEADER_ARB_LOST_Msk 0x80000UL 310 #define CXPI_CH_INTR_SET_TX_BIT_ERROR_Pos 20UL 311 #define CXPI_CH_INTR_SET_TX_BIT_ERROR_Msk 0x100000UL 312 #define CXPI_CH_INTR_SET_RX_CRC_ERROR_Pos 21UL 313 #define CXPI_CH_INTR_SET_RX_CRC_ERROR_Msk 0x200000UL 314 #define CXPI_CH_INTR_SET_RX_HEADER_PARITY_ERROR_Pos 22UL 315 #define CXPI_CH_INTR_SET_RX_HEADER_PARITY_ERROR_Msk 0x400000UL 316 #define CXPI_CH_INTR_SET_RX_DATA_LENGTH_ERROR_Pos 23UL 317 #define CXPI_CH_INTR_SET_RX_DATA_LENGTH_ERROR_Msk 0x800000UL 318 #define CXPI_CH_INTR_SET_TX_DATA_LENGTH_ERROR_Pos 24UL 319 #define CXPI_CH_INTR_SET_TX_DATA_LENGTH_ERROR_Msk 0x1000000UL 320 #define CXPI_CH_INTR_SET_RX_OVERFLOW_ERROR_Pos 25UL 321 #define CXPI_CH_INTR_SET_RX_OVERFLOW_ERROR_Msk 0x2000000UL 322 #define CXPI_CH_INTR_SET_TX_OVERFLOW_ERROR_Pos 26UL 323 #define CXPI_CH_INTR_SET_TX_OVERFLOW_ERROR_Msk 0x4000000UL 324 #define CXPI_CH_INTR_SET_RX_UNDERFLOW_ERROR_Pos 27UL 325 #define CXPI_CH_INTR_SET_RX_UNDERFLOW_ERROR_Msk 0x8000000UL 326 #define CXPI_CH_INTR_SET_TX_UNDERFLOW_ERROR_Pos 28UL 327 #define CXPI_CH_INTR_SET_TX_UNDERFLOW_ERROR_Msk 0x10000000UL 328 #define CXPI_CH_INTR_SET_RX_FRAME_ERROR_Pos 29UL 329 #define CXPI_CH_INTR_SET_RX_FRAME_ERROR_Msk 0x20000000UL 330 #define CXPI_CH_INTR_SET_TX_FRAME_ERROR_Pos 30UL 331 #define CXPI_CH_INTR_SET_TX_FRAME_ERROR_Msk 0x40000000UL 332 /* CXPI_CH.INTR_MASK */ 333 #define CXPI_CH_INTR_MASK_TX_HEADER_DONE_Pos 0UL 334 #define CXPI_CH_INTR_MASK_TX_HEADER_DONE_Msk 0x1UL 335 #define CXPI_CH_INTR_MASK_TX_RESPONSE_DONE_Pos 1UL 336 #define CXPI_CH_INTR_MASK_TX_RESPONSE_DONE_Msk 0x2UL 337 #define CXPI_CH_INTR_MASK_TX_WAKEUP_DONE_Pos 3UL 338 #define CXPI_CH_INTR_MASK_TX_WAKEUP_DONE_Msk 0x8UL 339 #define CXPI_CH_INTR_MASK_TX_FIFO_TRIGGER_Pos 4UL 340 #define CXPI_CH_INTR_MASK_TX_FIFO_TRIGGER_Msk 0x10UL 341 #define CXPI_CH_INTR_MASK_RX_HEADER_DONE_Pos 8UL 342 #define CXPI_CH_INTR_MASK_RX_HEADER_DONE_Msk 0x100UL 343 #define CXPI_CH_INTR_MASK_RX_RESPONSE_DONE_Pos 9UL 344 #define CXPI_CH_INTR_MASK_RX_RESPONSE_DONE_Msk 0x200UL 345 #define CXPI_CH_INTR_MASK_RX_WAKEUP_DETECT_Pos 10UL 346 #define CXPI_CH_INTR_MASK_RX_WAKEUP_DETECT_Msk 0x400UL 347 #define CXPI_CH_INTR_MASK_RX_FIFO_TRIGGER_Pos 11UL 348 #define CXPI_CH_INTR_MASK_RX_FIFO_TRIGGER_Msk 0x800UL 349 #define CXPI_CH_INTR_MASK_RX_HEADER_PID_DONE_Pos 12UL 350 #define CXPI_CH_INTR_MASK_RX_HEADER_PID_DONE_Msk 0x1000UL 351 #define CXPI_CH_INTR_MASK_TXRX_COMPLETE_Pos 13UL 352 #define CXPI_CH_INTR_MASK_TXRX_COMPLETE_Msk 0x2000UL 353 #define CXPI_CH_INTR_MASK_TIMEOUT_Pos 18UL 354 #define CXPI_CH_INTR_MASK_TIMEOUT_Msk 0x40000UL 355 #define CXPI_CH_INTR_MASK_TX_HEADER_ARB_LOST_Pos 19UL 356 #define CXPI_CH_INTR_MASK_TX_HEADER_ARB_LOST_Msk 0x80000UL 357 #define CXPI_CH_INTR_MASK_TX_BIT_ERROR_Pos 20UL 358 #define CXPI_CH_INTR_MASK_TX_BIT_ERROR_Msk 0x100000UL 359 #define CXPI_CH_INTR_MASK_RX_CRC_ERROR_Pos 21UL 360 #define CXPI_CH_INTR_MASK_RX_CRC_ERROR_Msk 0x200000UL 361 #define CXPI_CH_INTR_MASK_RX_HEADER_PARITY_ERROR_Pos 22UL 362 #define CXPI_CH_INTR_MASK_RX_HEADER_PARITY_ERROR_Msk 0x400000UL 363 #define CXPI_CH_INTR_MASK_RX_DATA_LENGTH_ERROR_Pos 23UL 364 #define CXPI_CH_INTR_MASK_RX_DATA_LENGTH_ERROR_Msk 0x800000UL 365 #define CXPI_CH_INTR_MASK_TX_DATA_LENGTH_ERROR_Pos 24UL 366 #define CXPI_CH_INTR_MASK_TX_DATA_LENGTH_ERROR_Msk 0x1000000UL 367 #define CXPI_CH_INTR_MASK_RX_OVERFLOW_ERROR_Pos 25UL 368 #define CXPI_CH_INTR_MASK_RX_OVERFLOW_ERROR_Msk 0x2000000UL 369 #define CXPI_CH_INTR_MASK_TX_OVERFLOW_ERROR_Pos 26UL 370 #define CXPI_CH_INTR_MASK_TX_OVERFLOW_ERROR_Msk 0x4000000UL 371 #define CXPI_CH_INTR_MASK_RX_UNDERFLOW_ERROR_Pos 27UL 372 #define CXPI_CH_INTR_MASK_RX_UNDERFLOW_ERROR_Msk 0x8000000UL 373 #define CXPI_CH_INTR_MASK_TX_UNDERFLOW_ERROR_Pos 28UL 374 #define CXPI_CH_INTR_MASK_TX_UNDERFLOW_ERROR_Msk 0x10000000UL 375 #define CXPI_CH_INTR_MASK_RX_FRAME_ERROR_Pos 29UL 376 #define CXPI_CH_INTR_MASK_RX_FRAME_ERROR_Msk 0x20000000UL 377 #define CXPI_CH_INTR_MASK_TX_FRAME_ERROR_Pos 30UL 378 #define CXPI_CH_INTR_MASK_TX_FRAME_ERROR_Msk 0x40000000UL 379 /* CXPI_CH.INTR_MASKED */ 380 #define CXPI_CH_INTR_MASKED_TX_HEADER_DONE_Pos 0UL 381 #define CXPI_CH_INTR_MASKED_TX_HEADER_DONE_Msk 0x1UL 382 #define CXPI_CH_INTR_MASKED_TX_RESPONSE_DONE_Pos 1UL 383 #define CXPI_CH_INTR_MASKED_TX_RESPONSE_DONE_Msk 0x2UL 384 #define CXPI_CH_INTR_MASKED_TX_WAKEUP_DONE_Pos 3UL 385 #define CXPI_CH_INTR_MASKED_TX_WAKEUP_DONE_Msk 0x8UL 386 #define CXPI_CH_INTR_MASKED_TX_FIFO_TRIGGER_Pos 4UL 387 #define CXPI_CH_INTR_MASKED_TX_FIFO_TRIGGER_Msk 0x10UL 388 #define CXPI_CH_INTR_MASKED_RX_HEADER_DONE_Pos 8UL 389 #define CXPI_CH_INTR_MASKED_RX_HEADER_DONE_Msk 0x100UL 390 #define CXPI_CH_INTR_MASKED_RX_RESPONSE_DONE_Pos 9UL 391 #define CXPI_CH_INTR_MASKED_RX_RESPONSE_DONE_Msk 0x200UL 392 #define CXPI_CH_INTR_MASKED_RX_WAKEUP_DETECT_Pos 10UL 393 #define CXPI_CH_INTR_MASKED_RX_WAKEUP_DETECT_Msk 0x400UL 394 #define CXPI_CH_INTR_MASKED_RX_FIFO_TRIGGER_Pos 11UL 395 #define CXPI_CH_INTR_MASKED_RX_FIFO_TRIGGER_Msk 0x800UL 396 #define CXPI_CH_INTR_MASKED_RX_HEADER_PID_DONE_Pos 12UL 397 #define CXPI_CH_INTR_MASKED_RX_HEADER_PID_DONE_Msk 0x1000UL 398 #define CXPI_CH_INTR_MASKED_TXRX_COMPLETE_Pos 13UL 399 #define CXPI_CH_INTR_MASKED_TXRX_COMPLETE_Msk 0x2000UL 400 #define CXPI_CH_INTR_MASKED_TIMEOUT_Pos 18UL 401 #define CXPI_CH_INTR_MASKED_TIMEOUT_Msk 0x40000UL 402 #define CXPI_CH_INTR_MASKED_TX_HEADER_ARB_LOST_Pos 19UL 403 #define CXPI_CH_INTR_MASKED_TX_HEADER_ARB_LOST_Msk 0x80000UL 404 #define CXPI_CH_INTR_MASKED_TX_BIT_ERROR_Pos 20UL 405 #define CXPI_CH_INTR_MASKED_TX_BIT_ERROR_Msk 0x100000UL 406 #define CXPI_CH_INTR_MASKED_RX_CRC_ERROR_Pos 21UL 407 #define CXPI_CH_INTR_MASKED_RX_CRC_ERROR_Msk 0x200000UL 408 #define CXPI_CH_INTR_MASKED_RX_HEADER_PARITY_ERROR_Pos 22UL 409 #define CXPI_CH_INTR_MASKED_RX_HEADER_PARITY_ERROR_Msk 0x400000UL 410 #define CXPI_CH_INTR_MASKED_RX_DATA_LENGTH_ERROR_Pos 23UL 411 #define CXPI_CH_INTR_MASKED_RX_DATA_LENGTH_ERROR_Msk 0x800000UL 412 #define CXPI_CH_INTR_MASKED_TX_DATA_LENGTH_ERROR_Pos 24UL 413 #define CXPI_CH_INTR_MASKED_TX_DATA_LENGTH_ERROR_Msk 0x1000000UL 414 #define CXPI_CH_INTR_MASKED_RX_OVERFLOW_ERROR_Pos 25UL 415 #define CXPI_CH_INTR_MASKED_RX_OVERFLOW_ERROR_Msk 0x2000000UL 416 #define CXPI_CH_INTR_MASKED_TX_OVERFLOW_ERROR_Pos 26UL 417 #define CXPI_CH_INTR_MASKED_TX_OVERFLOW_ERROR_Msk 0x4000000UL 418 #define CXPI_CH_INTR_MASKED_RX_UNDERFLOW_ERROR_Pos 27UL 419 #define CXPI_CH_INTR_MASKED_RX_UNDERFLOW_ERROR_Msk 0x8000000UL 420 #define CXPI_CH_INTR_MASKED_TX_UNDERFLOW_ERROR_Pos 28UL 421 #define CXPI_CH_INTR_MASKED_TX_UNDERFLOW_ERROR_Msk 0x10000000UL 422 #define CXPI_CH_INTR_MASKED_RX_FRAME_ERROR_Pos 29UL 423 #define CXPI_CH_INTR_MASKED_RX_FRAME_ERROR_Msk 0x20000000UL 424 #define CXPI_CH_INTR_MASKED_TX_FRAME_ERROR_Pos 30UL 425 #define CXPI_CH_INTR_MASKED_TX_FRAME_ERROR_Msk 0x40000000UL 426 427 428 /* CXPI.ERROR_CTL */ 429 #define CXPI_ERROR_CTL_CH_IDX_Pos 0UL 430 #define CXPI_ERROR_CTL_CH_IDX_Msk 0x1FUL 431 #define CXPI_ERROR_CTL_TX_CRC_ERROR_Pos 18UL 432 #define CXPI_ERROR_CTL_TX_CRC_ERROR_Msk 0x40000UL 433 #define CXPI_ERROR_CTL_TX_PID_PARITY_ERROR_Pos 19UL 434 #define CXPI_ERROR_CTL_TX_PID_PARITY_ERROR_Msk 0x80000UL 435 #define CXPI_ERROR_CTL_TX_DATA_LENGTH_ERROR_Pos 20UL 436 #define CXPI_ERROR_CTL_TX_DATA_LENGTH_ERROR_Msk 0x100000UL 437 #define CXPI_ERROR_CTL_TX_DATA_STOP_ERROR_Pos 25UL 438 #define CXPI_ERROR_CTL_TX_DATA_STOP_ERROR_Msk 0x2000000UL 439 #define CXPI_ERROR_CTL_ENABLED_Pos 31UL 440 #define CXPI_ERROR_CTL_ENABLED_Msk 0x80000000UL 441 /* CXPI.TEST_CTL */ 442 #define CXPI_TEST_CTL_CH_IDX_Pos 0UL 443 #define CXPI_TEST_CTL_CH_IDX_Msk 0x1FUL 444 #define CXPI_TEST_CTL_MODE_Pos 16UL 445 #define CXPI_TEST_CTL_MODE_Msk 0x10000UL 446 #define CXPI_TEST_CTL_ENABLED_Pos 31UL 447 #define CXPI_TEST_CTL_ENABLED_Msk 0x80000000UL 448 449 450 #endif /* _CYIP_CXPI_H_ */ 451 452 453 /* [] END OF FILE */ 454
