1 /***************************************************************************//** 2 * \file cyhal_xmc7200_320_bga.h 3 * 4 * \brief 5 * XMC7200 device GPIO HAL header for 320-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_XMC7200_320_BGA_H_ 28 #define _CYHAL_XMC7200_320_BGA_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_xmc7200_320_bga XMC7200 320-BGA 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the XMC7200 320-BGA package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint16_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint16_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint16_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 320-BGA package for the XMC7200 series. */ 52 typedef enum { 53 NC = 0xFFFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 61 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 62 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 63 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 64 P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 65 P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 66 P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6), //!< Port 1 Pin 6 67 68 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 69 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 70 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 71 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 72 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 73 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 74 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 75 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 76 77 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 78 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 79 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 80 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 81 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 82 P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 83 P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6), //!< Port 3 Pin 6 84 P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7), //!< Port 3 Pin 7 85 86 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 87 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 88 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 89 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 90 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 91 P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5), //!< Port 4 Pin 5 92 P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6), //!< Port 4 Pin 6 93 94 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 95 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 96 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 97 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 98 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 99 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 100 101 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 102 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 103 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 104 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 105 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 106 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 107 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 108 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 109 110 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 111 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 112 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 113 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 114 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 115 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 116 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 117 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 118 119 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 120 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 121 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 122 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 123 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 124 125 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 126 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 127 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 128 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 129 130 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 131 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 132 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 133 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 134 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 135 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 136 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 137 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 138 139 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 140 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 141 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 142 143 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 144 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 145 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 146 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 147 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 148 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 149 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 150 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 151 152 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 153 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 154 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 155 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 156 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 157 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 158 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 159 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 160 161 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 162 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 163 P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2 164 P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3 165 P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4 166 P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5 167 P14_6 = CYHAL_GET_GPIO(CYHAL_PORT_14, 6), //!< Port 14 Pin 6 168 P14_7 = CYHAL_GET_GPIO(CYHAL_PORT_14, 7), //!< Port 14 Pin 7 169 170 P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0 171 P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1 172 P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2 173 P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3 174 175 P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0), //!< Port 16 Pin 0 176 P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1), //!< Port 16 Pin 1 177 P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2), //!< Port 16 Pin 2 178 P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3), //!< Port 16 Pin 3 179 P16_4 = CYHAL_GET_GPIO(CYHAL_PORT_16, 4), //!< Port 16 Pin 4 180 P16_5 = CYHAL_GET_GPIO(CYHAL_PORT_16, 5), //!< Port 16 Pin 5 181 P16_6 = CYHAL_GET_GPIO(CYHAL_PORT_16, 6), //!< Port 16 Pin 6 182 P16_7 = CYHAL_GET_GPIO(CYHAL_PORT_16, 7), //!< Port 16 Pin 7 183 184 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 185 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 186 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 187 P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3 188 P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4 189 P17_5 = CYHAL_GET_GPIO(CYHAL_PORT_17, 5), //!< Port 17 Pin 5 190 P17_6 = CYHAL_GET_GPIO(CYHAL_PORT_17, 6), //!< Port 17 Pin 6 191 P17_7 = CYHAL_GET_GPIO(CYHAL_PORT_17, 7), //!< Port 17 Pin 7 192 193 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 194 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 195 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 196 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 197 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 198 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 199 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 200 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 201 202 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 203 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 204 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 205 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 206 P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4 207 208 P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0 209 P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1 210 P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2 211 P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3 212 P20_4 = CYHAL_GET_GPIO(CYHAL_PORT_20, 4), //!< Port 20 Pin 4 213 P20_5 = CYHAL_GET_GPIO(CYHAL_PORT_20, 5), //!< Port 20 Pin 5 214 P20_6 = CYHAL_GET_GPIO(CYHAL_PORT_20, 6), //!< Port 20 Pin 6 215 P20_7 = CYHAL_GET_GPIO(CYHAL_PORT_20, 7), //!< Port 20 Pin 7 216 217 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 218 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 219 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 220 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 221 P21_4 = CYHAL_GET_GPIO(CYHAL_PORT_21, 4), //!< Port 21 Pin 4 222 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 223 P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6 224 P21_7 = CYHAL_GET_GPIO(CYHAL_PORT_21, 7), //!< Port 21 Pin 7 225 226 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 227 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 228 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 229 P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4 230 P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5 231 P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6 232 P22_7 = CYHAL_GET_GPIO(CYHAL_PORT_22, 7), //!< Port 22 Pin 7 233 234 P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0 235 P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1 236 P23_2 = CYHAL_GET_GPIO(CYHAL_PORT_23, 2), //!< Port 23 Pin 2 237 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 238 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 239 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 240 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 241 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 242 243 P24_0 = CYHAL_GET_GPIO(CYHAL_PORT_24, 0), //!< Port 24 Pin 0 244 P24_1 = CYHAL_GET_GPIO(CYHAL_PORT_24, 1), //!< Port 24 Pin 1 245 P24_2 = CYHAL_GET_GPIO(CYHAL_PORT_24, 2), //!< Port 24 Pin 2 246 P24_3 = CYHAL_GET_GPIO(CYHAL_PORT_24, 3), //!< Port 24 Pin 3 247 P24_4 = CYHAL_GET_GPIO(CYHAL_PORT_24, 4), //!< Port 24 Pin 4 248 249 P25_0 = CYHAL_GET_GPIO(CYHAL_PORT_25, 0), //!< Port 25 Pin 0 250 P25_1 = CYHAL_GET_GPIO(CYHAL_PORT_25, 1), //!< Port 25 Pin 1 251 P25_2 = CYHAL_GET_GPIO(CYHAL_PORT_25, 2), //!< Port 25 Pin 2 252 P25_3 = CYHAL_GET_GPIO(CYHAL_PORT_25, 3), //!< Port 25 Pin 3 253 P25_4 = CYHAL_GET_GPIO(CYHAL_PORT_25, 4), //!< Port 25 Pin 4 254 P25_5 = CYHAL_GET_GPIO(CYHAL_PORT_25, 5), //!< Port 25 Pin 5 255 P25_6 = CYHAL_GET_GPIO(CYHAL_PORT_25, 6), //!< Port 25 Pin 6 256 P25_7 = CYHAL_GET_GPIO(CYHAL_PORT_25, 7), //!< Port 25 Pin 7 257 258 P26_0 = CYHAL_GET_GPIO(CYHAL_PORT_26, 0), //!< Port 26 Pin 0 259 P26_1 = CYHAL_GET_GPIO(CYHAL_PORT_26, 1), //!< Port 26 Pin 1 260 P26_2 = CYHAL_GET_GPIO(CYHAL_PORT_26, 2), //!< Port 26 Pin 2 261 P26_3 = CYHAL_GET_GPIO(CYHAL_PORT_26, 3), //!< Port 26 Pin 3 262 P26_4 = CYHAL_GET_GPIO(CYHAL_PORT_26, 4), //!< Port 26 Pin 4 263 P26_5 = CYHAL_GET_GPIO(CYHAL_PORT_26, 5), //!< Port 26 Pin 5 264 P26_6 = CYHAL_GET_GPIO(CYHAL_PORT_26, 6), //!< Port 26 Pin 6 265 P26_7 = CYHAL_GET_GPIO(CYHAL_PORT_26, 7), //!< Port 26 Pin 7 266 267 P27_0 = CYHAL_GET_GPIO(CYHAL_PORT_27, 0), //!< Port 27 Pin 0 268 P27_1 = CYHAL_GET_GPIO(CYHAL_PORT_27, 1), //!< Port 27 Pin 1 269 P27_2 = CYHAL_GET_GPIO(CYHAL_PORT_27, 2), //!< Port 27 Pin 2 270 P27_3 = CYHAL_GET_GPIO(CYHAL_PORT_27, 3), //!< Port 27 Pin 3 271 P27_4 = CYHAL_GET_GPIO(CYHAL_PORT_27, 4), //!< Port 27 Pin 4 272 P27_5 = CYHAL_GET_GPIO(CYHAL_PORT_27, 5), //!< Port 27 Pin 5 273 P27_6 = CYHAL_GET_GPIO(CYHAL_PORT_27, 6), //!< Port 27 Pin 6 274 P27_7 = CYHAL_GET_GPIO(CYHAL_PORT_27, 7), //!< Port 27 Pin 7 275 276 P28_0 = CYHAL_GET_GPIO(CYHAL_PORT_28, 0), //!< Port 28 Pin 0 277 P28_1 = CYHAL_GET_GPIO(CYHAL_PORT_28, 1), //!< Port 28 Pin 1 278 P28_2 = CYHAL_GET_GPIO(CYHAL_PORT_28, 2), //!< Port 28 Pin 2 279 P28_3 = CYHAL_GET_GPIO(CYHAL_PORT_28, 3), //!< Port 28 Pin 3 280 P28_4 = CYHAL_GET_GPIO(CYHAL_PORT_28, 4), //!< Port 28 Pin 4 281 P28_5 = CYHAL_GET_GPIO(CYHAL_PORT_28, 5), //!< Port 28 Pin 5 282 P28_6 = CYHAL_GET_GPIO(CYHAL_PORT_28, 6), //!< Port 28 Pin 6 283 P28_7 = CYHAL_GET_GPIO(CYHAL_PORT_28, 7), //!< Port 28 Pin 7 284 285 P29_0 = CYHAL_GET_GPIO(CYHAL_PORT_29, 0), //!< Port 29 Pin 0 286 P29_1 = CYHAL_GET_GPIO(CYHAL_PORT_29, 1), //!< Port 29 Pin 1 287 P29_2 = CYHAL_GET_GPIO(CYHAL_PORT_29, 2), //!< Port 29 Pin 2 288 P29_3 = CYHAL_GET_GPIO(CYHAL_PORT_29, 3), //!< Port 29 Pin 3 289 P29_4 = CYHAL_GET_GPIO(CYHAL_PORT_29, 4), //!< Port 29 Pin 4 290 P29_5 = CYHAL_GET_GPIO(CYHAL_PORT_29, 5), //!< Port 29 Pin 5 291 P29_6 = CYHAL_GET_GPIO(CYHAL_PORT_29, 6), //!< Port 29 Pin 6 292 P29_7 = CYHAL_GET_GPIO(CYHAL_PORT_29, 7), //!< Port 29 Pin 7 293 294 P30_0 = CYHAL_GET_GPIO(CYHAL_PORT_30, 0), //!< Port 30 Pin 0 295 P30_1 = CYHAL_GET_GPIO(CYHAL_PORT_30, 1), //!< Port 30 Pin 1 296 P30_2 = CYHAL_GET_GPIO(CYHAL_PORT_30, 2), //!< Port 30 Pin 2 297 P30_3 = CYHAL_GET_GPIO(CYHAL_PORT_30, 3), //!< Port 30 Pin 3 298 299 P31_0 = CYHAL_GET_GPIO(CYHAL_PORT_31, 0), //!< Port 31 Pin 0 300 P31_1 = CYHAL_GET_GPIO(CYHAL_PORT_31, 1), //!< Port 31 Pin 1 301 P31_2 = CYHAL_GET_GPIO(CYHAL_PORT_31, 2), //!< Port 31 Pin 2 302 303 P32_0 = CYHAL_GET_GPIO(CYHAL_PORT_32, 0), //!< Port 32 Pin 0 304 P32_1 = CYHAL_GET_GPIO(CYHAL_PORT_32, 1), //!< Port 32 Pin 1 305 P32_2 = CYHAL_GET_GPIO(CYHAL_PORT_32, 2), //!< Port 32 Pin 2 306 P32_3 = CYHAL_GET_GPIO(CYHAL_PORT_32, 3), //!< Port 32 Pin 3 307 P32_4 = CYHAL_GET_GPIO(CYHAL_PORT_32, 4), //!< Port 32 Pin 4 308 P32_5 = CYHAL_GET_GPIO(CYHAL_PORT_32, 5), //!< Port 32 Pin 5 309 P32_6 = CYHAL_GET_GPIO(CYHAL_PORT_32, 6), //!< Port 32 Pin 6 310 P32_7 = CYHAL_GET_GPIO(CYHAL_PORT_32, 7), //!< Port 32 Pin 7 311 312 P33_0 = CYHAL_GET_GPIO(CYHAL_PORT_33, 0), //!< Port 33 Pin 0 313 P33_1 = CYHAL_GET_GPIO(CYHAL_PORT_33, 1), //!< Port 33 Pin 1 314 P33_2 = CYHAL_GET_GPIO(CYHAL_PORT_33, 2), //!< Port 33 Pin 2 315 P33_3 = CYHAL_GET_GPIO(CYHAL_PORT_33, 3), //!< Port 33 Pin 3 316 P33_4 = CYHAL_GET_GPIO(CYHAL_PORT_33, 4), //!< Port 33 Pin 4 317 P33_5 = CYHAL_GET_GPIO(CYHAL_PORT_33, 5), //!< Port 33 Pin 5 318 P33_6 = CYHAL_GET_GPIO(CYHAL_PORT_33, 6), //!< Port 33 Pin 6 319 P33_7 = CYHAL_GET_GPIO(CYHAL_PORT_33, 7), //!< Port 33 Pin 7 320 321 P34_0 = CYHAL_GET_GPIO(CYHAL_PORT_34, 0), //!< Port 34 Pin 0 322 P34_1 = CYHAL_GET_GPIO(CYHAL_PORT_34, 1), //!< Port 34 Pin 1 323 P34_2 = CYHAL_GET_GPIO(CYHAL_PORT_34, 2), //!< Port 34 Pin 2 324 P34_3 = CYHAL_GET_GPIO(CYHAL_PORT_34, 3), //!< Port 34 Pin 3 325 P34_4 = CYHAL_GET_GPIO(CYHAL_PORT_34, 4), //!< Port 34 Pin 4 326 P34_5 = CYHAL_GET_GPIO(CYHAL_PORT_34, 5), //!< Port 34 Pin 5 327 P34_6 = CYHAL_GET_GPIO(CYHAL_PORT_34, 6), //!< Port 34 Pin 6 328 P34_7 = CYHAL_GET_GPIO(CYHAL_PORT_34, 7), //!< Port 34 Pin 7 329 } cyhal_gpio_xmc7200_320_bga_t; 330 331 /** Create generic name for the series/package specific type. */ 332 typedef cyhal_gpio_xmc7200_320_bga_t cyhal_gpio_t; 333 334 /* Connection type definition */ 335 /** Represents an association between a pin and a resource */ 336 typedef struct 337 { 338 uint8_t block_num; //!< The block number of the resource with this connection 339 uint8_t channel_num; //!< The channel number of the block with this connection 340 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 341 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 342 } cyhal_resource_pin_mapping_t; 343 344 /* Pin connections */ 345 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 346 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 347 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 348 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; 349 /** Indicates that a pin map exists for audioss_mclk*/ 350 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_MCLK (CY_GPIO_DM_STRONG) 351 /** List of valid pin to peripheral connections for the audioss_mclk signal. */ 352 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3]; 353 /** Indicates that a pin map exists for audioss_rx_sck*/ 354 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 355 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 356 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3]; 357 /** Indicates that a pin map exists for audioss_rx_sdi*/ 358 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 359 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 360 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3]; 361 /** Indicates that a pin map exists for audioss_rx_ws*/ 362 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 363 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 364 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3]; 365 /** Indicates that a pin map exists for audioss_tx_sck*/ 366 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 367 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 368 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; 369 /** Indicates that a pin map exists for audioss_tx_sdo*/ 370 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 371 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 372 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3]; 373 /** Indicates that a pin map exists for audioss_tx_ws*/ 374 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 375 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 376 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3]; 377 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 378 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 379 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 380 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[21]; 381 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 382 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 383 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 384 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[21]; 385 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 386 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 387 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 388 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3]; 389 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 390 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 391 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 392 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 393 /** Indicates that a pin map exists for cpuss_fault_out*/ 394 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 395 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 396 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8]; 397 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 398 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 399 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 400 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 401 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 402 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 403 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 404 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 405 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 406 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 407 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 408 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 409 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 410 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 411 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 412 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 413 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 414 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 415 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 416 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 417 /** Indicates that a pin map exists for cpuss_trace_clock*/ 418 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 419 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 420 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 421 /** Indicates that a pin map exists for cpuss_trace_data*/ 422 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 423 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 424 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 425 /** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/ 426 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF) 427 /** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */ 428 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[3]; 429 /** Indicates that a pin map exists for eth_mdc*/ 430 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF) 431 /** List of valid pin to peripheral connections for the eth_mdc signal. */ 432 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[3]; 433 /** Indicates that a pin map exists for eth_mdio*/ 434 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF) 435 /** List of valid pin to peripheral connections for the eth_mdio signal. */ 436 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[3]; 437 /** Indicates that a pin map exists for eth_ref_clk*/ 438 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_DM_HIGHZ) 439 /** List of valid pin to peripheral connections for the eth_ref_clk signal. */ 440 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[3]; 441 /** Indicates that a pin map exists for eth_rx_clk*/ 442 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_DM_HIGHZ) 443 /** List of valid pin to peripheral connections for the eth_rx_clk signal. */ 444 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[3]; 445 /** Indicates that a pin map exists for eth_rx_ctl*/ 446 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_DM_HIGHZ) 447 /** List of valid pin to peripheral connections for the eth_rx_ctl signal. */ 448 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[3]; 449 /** Indicates that a pin map exists for eth_rx_er*/ 450 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_DM_HIGHZ) 451 /** List of valid pin to peripheral connections for the eth_rx_er signal. */ 452 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[2]; 453 /** Indicates that a pin map exists for eth_rxd*/ 454 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_DM_HIGHZ) 455 /** List of valid pin to peripheral connections for the eth_rxd signal. */ 456 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[16]; 457 /** Indicates that a pin map exists for eth_tx_clk*/ 458 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF) 459 /** List of valid pin to peripheral connections for the eth_tx_clk signal. */ 460 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[3]; 461 /** Indicates that a pin map exists for eth_tx_ctl*/ 462 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF) 463 /** List of valid pin to peripheral connections for the eth_tx_ctl signal. */ 464 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[3]; 465 /** Indicates that a pin map exists for eth_tx_er*/ 466 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_ER (CY_GPIO_DM_STRONG) 467 /** List of valid pin to peripheral connections for the eth_tx_er signal. */ 468 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[2]; 469 /** Indicates that a pin map exists for eth_txd*/ 470 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF) 471 /** List of valid pin to peripheral connections for the eth_txd signal. */ 472 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[16]; 473 /** Indicates that a pin map exists for flexray_rxda*/ 474 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDA (CY_GPIO_DM_HIGHZ) 475 /** List of valid pin to peripheral connections for the flexray_rxda signal. */ 476 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1]; 477 /** Indicates that a pin map exists for flexray_rxdb*/ 478 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDB (CY_GPIO_DM_HIGHZ) 479 /** List of valid pin to peripheral connections for the flexray_rxdb signal. */ 480 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1]; 481 /** Indicates that a pin map exists for flexray_txda*/ 482 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDA (CY_GPIO_DM_STRONG) 483 /** List of valid pin to peripheral connections for the flexray_txda signal. */ 484 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1]; 485 /** Indicates that a pin map exists for flexray_txdb*/ 486 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDB (CY_GPIO_DM_STRONG) 487 /** List of valid pin to peripheral connections for the flexray_txdb signal. */ 488 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1]; 489 /** Indicates that a pin map exists for flexray_txena_n*/ 490 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENA_N (CY_GPIO_DM_STRONG) 491 /** List of valid pin to peripheral connections for the flexray_txena_n signal. */ 492 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1]; 493 /** Indicates that a pin map exists for flexray_txenb_n*/ 494 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENB_N (CY_GPIO_DM_STRONG) 495 /** List of valid pin to peripheral connections for the flexray_txenb_n signal. */ 496 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1]; 497 /** Indicates that a pin map exists for lin_lin_en*/ 498 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 499 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 500 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[39]; 501 /** Indicates that a pin map exists for lin_lin_rx*/ 502 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 503 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 504 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[49]; 505 /** Indicates that a pin map exists for lin_lin_tx*/ 506 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 507 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 508 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[49]; 509 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 510 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 511 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 512 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3]; 513 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 514 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 515 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 516 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9]; 517 /** Indicates that a pin map exists for pass_sarmux_pads*/ 518 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 519 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 520 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[96]; 521 /** Indicates that a pin map exists for peri_tr_io_input*/ 522 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 523 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 524 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[48]; 525 /** Indicates that a pin map exists for peri_tr_io_output*/ 526 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 527 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 528 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 529 /** Indicates that a pin map exists for scb_i2c_scl*/ 530 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 531 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 532 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[23]; 533 /** Indicates that a pin map exists for scb_i2c_sda*/ 534 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 535 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 536 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[23]; 537 /** Indicates that a pin map exists for scb_spi_m_clk*/ 538 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 539 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 540 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[25]; 541 /** Indicates that a pin map exists for scb_spi_m_miso*/ 542 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 543 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 544 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[24]; 545 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 546 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 547 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 548 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[24]; 549 /** Indicates that a pin map exists for scb_spi_m_select0*/ 550 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 551 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 552 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[25]; 553 /** Indicates that a pin map exists for scb_spi_m_select1*/ 554 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 555 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 556 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[21]; 557 /** Indicates that a pin map exists for scb_spi_m_select2*/ 558 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 559 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 560 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[20]; 561 /** Indicates that a pin map exists for scb_spi_m_select3*/ 562 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 563 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 564 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; 565 /** Indicates that a pin map exists for scb_spi_s_clk*/ 566 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 567 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 568 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[25]; 569 /** Indicates that a pin map exists for scb_spi_s_miso*/ 570 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 571 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 572 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[24]; 573 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 574 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 575 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 576 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[24]; 577 /** Indicates that a pin map exists for scb_spi_s_select0*/ 578 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 579 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 580 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[25]; 581 /** Indicates that a pin map exists for scb_spi_s_select1*/ 582 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 583 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 584 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[21]; 585 /** Indicates that a pin map exists for scb_spi_s_select2*/ 586 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 587 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 588 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[20]; 589 /** Indicates that a pin map exists for scb_spi_s_select3*/ 590 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 591 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 592 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; 593 /** Indicates that a pin map exists for scb_uart_cts*/ 594 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 595 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 596 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[21]; 597 /** Indicates that a pin map exists for scb_uart_rts*/ 598 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 599 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 600 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[21]; 601 /** Indicates that a pin map exists for scb_uart_rx*/ 602 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 603 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 604 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[21]; 605 /** Indicates that a pin map exists for scb_uart_tx*/ 606 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 607 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 608 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[21]; 609 /** Indicates that a pin map exists for sdhc_card_cmd*/ 610 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 611 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 612 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; 613 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 614 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 615 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 616 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; 617 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 618 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 619 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 620 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[8]; 621 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 622 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 623 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 624 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; 625 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 626 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 627 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 628 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; 629 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 630 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 631 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 632 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; 633 /** Indicates that a pin map exists for sdhc_clk_card*/ 634 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 635 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 636 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; 637 /** Indicates that a pin map exists for smif_spi_clk*/ 638 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 639 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 640 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[2]; 641 /** Indicates that a pin map exists for smif_spi_data0*/ 642 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 643 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 644 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[2]; 645 /** Indicates that a pin map exists for smif_spi_data1*/ 646 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 647 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 648 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[2]; 649 /** Indicates that a pin map exists for smif_spi_data2*/ 650 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 651 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 652 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[2]; 653 /** Indicates that a pin map exists for smif_spi_data3*/ 654 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 655 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 656 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[2]; 657 /** Indicates that a pin map exists for smif_spi_data4*/ 658 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 659 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 660 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[2]; 661 /** Indicates that a pin map exists for smif_spi_data5*/ 662 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 663 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 664 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[2]; 665 /** Indicates that a pin map exists for smif_spi_data6*/ 666 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 667 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 668 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[2]; 669 /** Indicates that a pin map exists for smif_spi_data7*/ 670 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 671 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 672 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[2]; 673 /** Indicates that a pin map exists for smif_spi_rwds*/ 674 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_RWDS (CY_GPIO_DM_STRONG) 675 /** List of valid pin to peripheral connections for the smif_spi_rwds signal. */ 676 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[2]; 677 /** Indicates that a pin map exists for smif_spi_select0*/ 678 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 679 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 680 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[2]; 681 /** Indicates that a pin map exists for smif_spi_select1*/ 682 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 683 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 684 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[2]; 685 /** Indicates that a pin map exists for tcpwm_line*/ 686 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 687 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 688 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[227]; 689 /** Indicates that a pin map exists for tcpwm_line_compl*/ 690 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 691 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 692 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[227]; 693 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 694 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 695 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 696 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[446]; 697 698 #if defined(__cplusplus) 699 } 700 #endif /* __cplusplus */ 701 702 /** \} group_hal_impl_pin_package */ 703 704 #endif /* _CYHAL_XMC7200_320_BGA_H_ */ 705 706 707 /* [] END OF FILE */ 708
