1 /***************************************************************************//** 2 * \file cyhal_xmc7200_320_bga.c 3 * 4 * \brief 5 * XMC7200 device GPIO HAL header for 320-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_XMC7200_320_BGA_H_) 31 #include "pin_packages/cyhal_xmc7200_320_bga.h" 32 33 /* Pin connections */ 34 /* Connections for: audioss_clk_i2s_if */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3] = { 36 {0u, 0u, P12_1, P12_1_AUDIOSS0_CLK_I2S_IF}, 37 {1u, 0u, P13_4, P13_4_AUDIOSS1_CLK_I2S_IF}, 38 {2u, 0u, P15_0, P15_0_AUDIOSS2_CLK_I2S_IF}, 39 }; 40 41 /* Connections for: audioss_mclk */ 42 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3] = { 43 {0u, 0u, P11_0, P11_0_AUDIOSS0_MCLK}, 44 {1u, 0u, P13_0, P13_0_AUDIOSS1_MCLK}, 45 {2u, 0u, P14_0, P14_0_AUDIOSS2_MCLK}, 46 }; 47 48 /* Connections for: audioss_rx_sck */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3] = { 50 {0u, 0u, P12_2, P12_2_AUDIOSS0_RX_SCK}, 51 {1u, 0u, P13_5, P13_5_AUDIOSS1_RX_SCK}, 52 {2u, 0u, P15_1, P15_1_AUDIOSS2_RX_SCK}, 53 }; 54 55 /* Connections for: audioss_rx_sdi */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3] = { 57 {0u, 0u, P12_4, P12_4_AUDIOSS0_RX_SDI}, 58 {1u, 0u, P13_7, P13_7_AUDIOSS1_RX_SDI}, 59 {2u, 0u, P15_3, P15_3_AUDIOSS2_RX_SDI}, 60 }; 61 62 /* Connections for: audioss_rx_ws */ 63 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3] = { 64 {0u, 0u, P12_3, P12_3_AUDIOSS0_RX_WS}, 65 {1u, 0u, P13_6, P13_6_AUDIOSS1_RX_WS}, 66 {2u, 0u, P15_2, P15_2_AUDIOSS2_RX_WS}, 67 }; 68 69 /* Connections for: audioss_tx_sck */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3] = { 71 {0u, 0u, P11_1, P11_1_AUDIOSS0_TX_SCK}, 72 {1u, 0u, P13_1, P13_1_AUDIOSS1_TX_SCK}, 73 {2u, 0u, P14_1, P14_1_AUDIOSS2_TX_SCK}, 74 }; 75 76 /* Connections for: audioss_tx_sdo */ 77 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3] = { 78 {0u, 0u, P12_0, P12_0_AUDIOSS0_TX_SDO}, 79 {1u, 0u, P13_3, P13_3_AUDIOSS1_TX_SDO}, 80 {2u, 0u, P14_5, P14_5_AUDIOSS2_TX_SDO}, 81 }; 82 83 /* Connections for: audioss_tx_ws */ 84 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3] = { 85 {0u, 0u, P11_2, P11_2_AUDIOSS0_TX_WS}, 86 {1u, 0u, P13_2, P13_2_AUDIOSS1_TX_WS}, 87 {2u, 0u, P14_4, P14_4_AUDIOSS2_TX_WS}, 88 }; 89 90 /* Connections for: canfd_ttcan_rx */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[21] = { 92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 93 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 94 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 95 {1u, 2u, P3_7, P3_7_CANFD1_TTCAN_RX2}, 96 {0u, 1u, P4_4, P4_4_CANFD0_TTCAN_RX1}, 97 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 98 {0u, 4u, P7_4, P7_4_CANFD0_TTCAN_RX4}, 99 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 100 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 101 {1u, 1u, P12_5, P12_5_CANFD1_TTCAN_RX1}, 102 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 103 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 104 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 105 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 106 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 107 {1u, 2u, P20_4, P20_4_CANFD1_TTCAN_RX2}, 108 {1u, 4u, P20_7, P20_7_CANFD1_TTCAN_RX4}, 109 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 110 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 111 {1u, 3u, P30_3, P30_3_CANFD1_TTCAN_RX3}, 112 {1u, 4u, P32_7, P32_7_CANFD1_TTCAN_RX4}, 113 }; 114 115 /* Connections for: canfd_ttcan_tx */ 116 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[21] = { 117 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 118 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 119 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 120 {1u, 2u, P3_6, P3_6_CANFD1_TTCAN_TX2}, 121 {0u, 1u, P4_3, P4_3_CANFD0_TTCAN_TX1}, 122 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 123 {0u, 4u, P7_3, P7_3_CANFD0_TTCAN_TX4}, 124 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 125 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 126 {1u, 1u, P12_4, P12_4_CANFD1_TTCAN_TX1}, 127 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 128 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 129 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 130 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 131 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 132 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 133 {1u, 4u, P20_6, P20_6_CANFD1_TTCAN_TX4}, 134 {1u, 1u, P21_5, P21_5_CANFD1_TTCAN_TX1}, 135 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 136 {1u, 3u, P30_2, P30_2_CANFD1_TTCAN_TX3}, 137 {1u, 4u, P32_6, P32_6_CANFD1_TTCAN_TX4}, 138 }; 139 140 /* Connections for: cpuss_cal_sup_nz */ 141 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3] = { 142 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 143 {0u, 0u, P21_7, P21_7_CPUSS_CAL_SUP_NZ}, 144 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 145 }; 146 147 /* Connections for: cpuss_clk_fm_pump */ 148 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 149 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 150 }; 151 152 /* Connections for: cpuss_fault_out */ 153 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8] = { 154 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 155 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 156 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 157 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 158 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 159 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 160 {0u, 2u, P23_2, P23_2_CPUSS_FAULT_OUT2}, 161 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 162 }; 163 164 /* Connections for: cpuss_swj_swclk_tclk */ 165 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 166 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 167 }; 168 169 /* Connections for: cpuss_swj_swdio_tms */ 170 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 171 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 172 }; 173 174 /* Connections for: cpuss_swj_swdoe_tdi */ 175 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 176 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 177 }; 178 179 /* Connections for: cpuss_swj_swo_tdo */ 180 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 181 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 182 }; 183 184 /* Connections for: cpuss_swj_trstn */ 185 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 186 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 187 }; 188 189 /* Connections for: cpuss_trace_clock */ 190 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 191 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 192 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 193 }; 194 195 /* Connections for: cpuss_trace_data */ 196 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 197 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 198 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 199 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 200 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 201 {0u, 0u, P21_5, P21_5_CPUSS_TRACE_DATA0}, 202 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 203 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 204 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 205 }; 206 207 /* Connections for: eth_eth_tsu_timer_cmp_val */ 208 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[3] = { 209 {0u, 0u, P2_3, P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL}, 210 {1u, 0u, P27_7, P27_7_ETH1_ETH_TSU_TIMER_CMP_VAL}, 211 {0u, 0u, P34_7, P34_7_ETH0_ETH_TSU_TIMER_CMP_VAL}, 212 }; 213 214 /* Connections for: eth_mdc */ 215 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[3] = { 216 {0u, 0u, P3_1, P3_1_ETH0_MDC}, 217 {1u, 0u, P27_6, P27_6_ETH1_MDC}, 218 {0u, 0u, P34_6, P34_6_ETH0_MDC}, 219 }; 220 221 /* Connections for: eth_mdio */ 222 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[3] = { 223 {0u, 0u, P3_0, P3_0_ETH0_MDIO}, 224 {1u, 0u, P27_5, P27_5_ETH1_MDIO}, 225 {0u, 0u, P34_5, P34_5_ETH0_MDIO}, 226 }; 227 228 /* Connections for: eth_ref_clk */ 229 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[3] = { 230 {0u, 0u, P18_0, P18_0_ETH0_REF_CLK}, 231 {1u, 0u, P26_0, P26_0_ETH1_REF_CLK}, 232 {0u, 0u, P33_0, P33_0_ETH0_REF_CLK}, 233 }; 234 235 /* Connections for: eth_rx_clk */ 236 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[3] = { 237 {0u, 0u, P23_3, P23_3_ETH0_RX_CLK}, 238 {1u, 0u, P27_4, P27_4_ETH1_RX_CLK}, 239 {0u, 0u, P34_4, P34_4_ETH0_RX_CLK}, 240 }; 241 242 /* Connections for: eth_rx_ctl */ 243 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[3] = { 244 {0u, 0u, P21_5, P21_5_ETH0_RX_CTL}, 245 {1u, 0u, P27_3, P27_3_ETH1_RX_CTL}, 246 {0u, 0u, P34_3, P34_3_ETH0_RX_CTL}, 247 }; 248 249 /* Connections for: eth_rx_er */ 250 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[2] = { 251 {0u, 0u, P2_2, P2_2_ETH0_RX_ER}, 252 {1u, 0u, P34_3, P34_3_ETH1_RX_ER}, 253 }; 254 255 /* Connections for: eth_rxd */ 256 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[16] = { 257 {0u, 0u, P19_0, P19_0_ETH0_RXD0}, 258 {0u, 1u, P19_1, P19_1_ETH0_RXD1}, 259 {0u, 2u, P19_2, P19_2_ETH0_RXD2}, 260 {0u, 3u, P19_3, P19_3_ETH0_RXD3}, 261 {1u, 0u, P26_7, P26_7_ETH1_RXD0}, 262 {1u, 1u, P27_0, P27_0_ETH1_RXD1}, 263 {1u, 2u, P27_1, P27_1_ETH1_RXD2}, 264 {1u, 3u, P27_2, P27_2_ETH1_RXD3}, 265 {0u, 0u, P33_7, P33_7_ETH0_RXD0}, 266 {1u, 4u, P33_7, P33_7_ETH1_RXD4}, 267 {0u, 1u, P34_0, P34_0_ETH0_RXD1}, 268 {1u, 5u, P34_0, P34_0_ETH1_RXD5}, 269 {0u, 2u, P34_1, P34_1_ETH0_RXD2}, 270 {1u, 6u, P34_1, P34_1_ETH1_RXD6}, 271 {0u, 3u, P34_2, P34_2_ETH0_RXD3}, 272 {1u, 7u, P34_2, P34_2_ETH1_RXD7}, 273 }; 274 275 /* Connections for: eth_tx_clk */ 276 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[3] = { 277 {0u, 0u, P18_3, P18_3_ETH0_TX_CLK}, 278 {1u, 0u, P26_2, P26_2_ETH1_TX_CLK}, 279 {0u, 0u, P33_2, P33_2_ETH0_TX_CLK}, 280 }; 281 282 /* Connections for: eth_tx_ctl */ 283 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[3] = { 284 {0u, 0u, P18_1, P18_1_ETH0_TX_CTL}, 285 {1u, 0u, P26_1, P26_1_ETH1_TX_CTL}, 286 {0u, 0u, P33_1, P33_1_ETH0_TX_CTL}, 287 }; 288 289 /* Connections for: eth_tx_er */ 290 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[2] = { 291 {0u, 0u, P18_2, P18_2_ETH0_TX_ER}, 292 {1u, 0u, P33_1, P33_1_ETH1_TX_ER}, 293 }; 294 295 /* Connections for: eth_txd */ 296 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[16] = { 297 {0u, 0u, P18_4, P18_4_ETH0_TXD0}, 298 {0u, 1u, P18_5, P18_5_ETH0_TXD1}, 299 {0u, 2u, P18_6, P18_6_ETH0_TXD2}, 300 {0u, 3u, P18_7, P18_7_ETH0_TXD3}, 301 {1u, 0u, P26_3, P26_3_ETH1_TXD0}, 302 {1u, 1u, P26_4, P26_4_ETH1_TXD1}, 303 {1u, 2u, P26_5, P26_5_ETH1_TXD2}, 304 {1u, 3u, P26_6, P26_6_ETH1_TXD3}, 305 {0u, 0u, P33_3, P33_3_ETH0_TXD0}, 306 {1u, 4u, P33_3, P33_3_ETH1_TXD4}, 307 {0u, 1u, P33_4, P33_4_ETH0_TXD1}, 308 {1u, 5u, P33_4, P33_4_ETH1_TXD5}, 309 {0u, 2u, P33_5, P33_5_ETH0_TXD2}, 310 {1u, 6u, P33_5, P33_5_ETH1_TXD6}, 311 {0u, 3u, P33_6, P33_6_ETH0_TXD3}, 312 {1u, 7u, P33_6, P33_6_ETH1_TXD7}, 313 }; 314 315 /* Connections for: flexray_rxda */ 316 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1] = { 317 {0u, 0u, P10_2, P10_2_FLEXRAY0_RXDA}, 318 }; 319 320 /* Connections for: flexray_rxdb */ 321 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1] = { 322 {0u, 0u, P10_5, P10_5_FLEXRAY0_RXDB}, 323 }; 324 325 /* Connections for: flexray_txda */ 326 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1] = { 327 {0u, 0u, P10_3, P10_3_FLEXRAY0_TXDA}, 328 }; 329 330 /* Connections for: flexray_txdb */ 331 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1] = { 332 {0u, 0u, P10_6, P10_6_FLEXRAY0_TXDB}, 333 }; 334 335 /* Connections for: flexray_txena_n */ 336 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1] = { 337 {0u, 0u, P10_4, P10_4_FLEXRAY0_TXENA_N}, 338 }; 339 340 /* Connections for: flexray_txenb_n */ 341 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1] = { 342 {0u, 0u, P10_7, P10_7_FLEXRAY0_TXENB_N}, 343 }; 344 345 /* Connections for: lin_lin_en */ 346 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[39] = { 347 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 348 {0u, 8u, P1_6, P1_6_LIN0_LIN_EN8}, 349 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 350 {0u, 5u, P2_5, P2_5_LIN0_LIN_EN5}, 351 {0u, 11u, P3_7, P3_7_LIN0_LIN_EN11}, 352 {0u, 1u, P4_2, P4_2_LIN0_LIN_EN1}, 353 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 354 {0u, 2u, P5_5, P5_5_LIN0_LIN_EN2}, 355 {0u, 9u, P6_0, P6_0_LIN0_LIN_EN9}, 356 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 357 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 358 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 359 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 360 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 361 {0u, 16u, P9_0, P9_0_LIN0_LIN_EN16}, 362 {0u, 12u, P9_3, P9_3_LIN0_LIN_EN12}, 363 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 364 {0u, 13u, P10_7, P10_7_LIN0_LIN_EN13}, 365 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 366 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 367 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 368 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 369 {0u, 14u, P14_7, P14_7_LIN0_LIN_EN14}, 370 {0u, 11u, P16_2, P16_2_LIN0_LIN_EN11}, 371 {0u, 11u, P17_2, P17_2_LIN0_LIN_EN11}, 372 {0u, 15u, P17_7, P17_7_LIN0_LIN_EN15}, 373 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 374 {0u, 0u, P21_7, P21_7_LIN0_LIN_EN0}, 375 {0u, 7u, P22_7, P22_7_LIN0_LIN_EN7}, 376 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 377 {0u, 16u, P24_4, P24_4_LIN0_LIN_EN16}, 378 {0u, 17u, P28_3, P28_3_LIN0_LIN_EN17}, 379 {0u, 18u, P28_6, P28_6_LIN0_LIN_EN18}, 380 {0u, 19u, P29_1, P29_1_LIN0_LIN_EN19}, 381 {0u, 16u, P30_3, P30_3_LIN0_LIN_EN16}, 382 {0u, 17u, P31_2, P31_2_LIN0_LIN_EN17}, 383 {0u, 18u, P32_4, P32_4_LIN0_LIN_EN18}, 384 {0u, 10u, P32_6, P32_6_LIN0_LIN_EN10}, 385 {0u, 19u, P32_7, P32_7_LIN0_LIN_EN19}, 386 }; 387 388 /* Connections for: lin_lin_rx */ 389 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[49] = { 390 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 391 {0u, 0u, P1_2, P1_2_LIN0_LIN_RX0}, 392 {0u, 8u, P1_4, P1_4_LIN0_LIN_RX8}, 393 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 394 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 395 {0u, 11u, P2_7, P2_7_LIN0_LIN_RX11}, 396 {0u, 1u, P3_4, P3_4_LIN0_LIN_RX1}, 397 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 398 {0u, 15u, P4_4, P4_4_LIN0_LIN_RX15}, 399 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 400 {0u, 10u, P5_2, P5_2_LIN0_LIN_RX10}, 401 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 402 {0u, 9u, P5_4, P5_4_LIN0_LIN_RX9}, 403 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 404 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 405 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 406 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 407 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 408 {0u, 16u, P8_3, P8_3_LIN0_LIN_RX16}, 409 {0u, 12u, P9_1, P9_1_LIN0_LIN_RX12}, 410 {0u, 7u, P10_0, P10_0_LIN0_LIN_RX7}, 411 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 412 {0u, 13u, P10_5, P10_5_LIN0_LIN_RX13}, 413 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 414 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 415 {0u, 2u, P13_3, P13_3_LIN0_LIN_RX2}, 416 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 417 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 418 {0u, 14u, P14_5, P14_5_LIN0_LIN_RX14}, 419 {0u, 11u, P16_0, P16_0_LIN0_LIN_RX11}, 420 {0u, 11u, P17_0, P17_0_LIN0_LIN_RX11}, 421 {0u, 15u, P17_5, P17_5_LIN0_LIN_RX15}, 422 {0u, 12u, P17_7, P17_7_LIN0_LIN_RX12}, 423 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 424 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 425 {0u, 13u, P21_6, P21_6_LIN0_LIN_RX13}, 426 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 427 {0u, 14u, P22_7, P22_7_LIN0_LIN_RX14}, 428 {0u, 6u, P23_2, P23_2_LIN0_LIN_RX6}, 429 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 430 {0u, 16u, P24_0, P24_0_LIN0_LIN_RX16}, 431 {0u, 17u, P28_1, P28_1_LIN0_LIN_RX17}, 432 {0u, 18u, P28_4, P28_4_LIN0_LIN_RX18}, 433 {0u, 19u, P28_7, P28_7_LIN0_LIN_RX19}, 434 {0u, 16u, P30_1, P30_1_LIN0_LIN_RX16}, 435 {0u, 17u, P31_0, P31_0_LIN0_LIN_RX17}, 436 {0u, 18u, P32_2, P32_2_LIN0_LIN_RX18}, 437 {0u, 10u, P32_4, P32_4_LIN0_LIN_RX10}, 438 {0u, 19u, P32_5, P32_5_LIN0_LIN_RX19}, 439 }; 440 441 /* Connections for: lin_lin_tx */ 442 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[49] = { 443 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 444 {0u, 0u, P1_3, P1_3_LIN0_LIN_TX0}, 445 {0u, 8u, P1_5, P1_5_LIN0_LIN_TX8}, 446 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 447 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 448 {0u, 1u, P3_5, P3_5_LIN0_LIN_TX1}, 449 {0u, 11u, P3_6, P3_6_LIN0_LIN_TX11}, 450 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 451 {0u, 15u, P5_0, P5_0_LIN0_LIN_TX15}, 452 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 453 {0u, 10u, P5_3, P5_3_LIN0_LIN_TX10}, 454 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 455 {0u, 9u, P5_5, P5_5_LIN0_LIN_TX9}, 456 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 457 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 458 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 459 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 460 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 461 {0u, 16u, P8_4, P8_4_LIN0_LIN_TX16}, 462 {0u, 12u, P9_2, P9_2_LIN0_LIN_TX12}, 463 {0u, 7u, P10_1, P10_1_LIN0_LIN_TX7}, 464 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 465 {0u, 13u, P10_6, P10_6_LIN0_LIN_TX13}, 466 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 467 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 468 {0u, 2u, P13_4, P13_4_LIN0_LIN_TX2}, 469 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 470 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 471 {0u, 14u, P14_6, P14_6_LIN0_LIN_TX14}, 472 {0u, 11u, P16_1, P16_1_LIN0_LIN_TX11}, 473 {0u, 11u, P17_1, P17_1_LIN0_LIN_TX11}, 474 {0u, 15u, P17_6, P17_6_LIN0_LIN_TX15}, 475 {0u, 12u, P18_0, P18_0_LIN0_LIN_TX12}, 476 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 477 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 478 {0u, 13u, P21_7, P21_7_LIN0_LIN_TX13}, 479 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 480 {0u, 14u, P23_0, P23_0_LIN0_LIN_TX14}, 481 {0u, 6u, P23_3, P23_3_LIN0_LIN_TX6}, 482 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 483 {0u, 16u, P24_3, P24_3_LIN0_LIN_TX16}, 484 {0u, 17u, P28_2, P28_2_LIN0_LIN_TX17}, 485 {0u, 18u, P28_5, P28_5_LIN0_LIN_TX18}, 486 {0u, 19u, P29_0, P29_0_LIN0_LIN_TX19}, 487 {0u, 16u, P30_2, P30_2_LIN0_LIN_TX16}, 488 {0u, 17u, P31_1, P31_1_LIN0_LIN_TX17}, 489 {0u, 18u, P32_3, P32_3_LIN0_LIN_TX18}, 490 {0u, 10u, P32_5, P32_5_LIN0_LIN_TX10}, 491 {0u, 19u, P32_6, P32_6_LIN0_LIN_TX19}, 492 }; 493 494 /* Connections for: pass_sar_ext_mux_en */ 495 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3] = { 496 {0u, 0u, P4_3, P4_3_PASS0_SAR_EXT_MUX_EN0}, 497 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 498 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 499 }; 500 501 /* Connections for: pass_sar_ext_mux_sel */ 502 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9] = { 503 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 504 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 505 {0u, 2u, P4_2, P4_2_PASS0_SAR_EXT_MUX_SEL2}, 506 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 507 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 508 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 509 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 510 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 511 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 512 }; 513 514 /* Connections for: pass_sarmux_pads */ 515 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[96] = { 516 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 517 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 518 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 519 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 520 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 521 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 522 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 523 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 524 {0u, 16u, P7_0, HSIOM_SEL_GPIO}, 525 {0u, 17u, P7_1, HSIOM_SEL_GPIO}, 526 {0u, 18u, P7_2, HSIOM_SEL_GPIO}, 527 {0u, 19u, P7_3, HSIOM_SEL_GPIO}, 528 {0u, 20u, P7_4, HSIOM_SEL_GPIO}, 529 {0u, 21u, P7_5, HSIOM_SEL_GPIO}, 530 {0u, 22u, P7_6, HSIOM_SEL_GPIO}, 531 {0u, 23u, P7_7, HSIOM_SEL_GPIO}, 532 {0u, 24u, P8_1, HSIOM_SEL_GPIO}, 533 {0u, 25u, P8_2, HSIOM_SEL_GPIO}, 534 {0u, 26u, P8_3, HSIOM_SEL_GPIO}, 535 {0u, 27u, P8_4, HSIOM_SEL_GPIO}, 536 {0u, 28u, P9_0, HSIOM_SEL_GPIO}, 537 {0u, 29u, P9_1, HSIOM_SEL_GPIO}, 538 {0u, 30u, P9_2, HSIOM_SEL_GPIO}, 539 {0u, 31u, P9_3, HSIOM_SEL_GPIO}, 540 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 541 {1u, 1u, P10_5, HSIOM_SEL_GPIO}, 542 {1u, 2u, P10_6, HSIOM_SEL_GPIO}, 543 {1u, 3u, P10_7, HSIOM_SEL_GPIO}, 544 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 545 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 546 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 547 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 548 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 549 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 550 {1u, 10u, P12_6, HSIOM_SEL_GPIO}, 551 {1u, 11u, P12_7, HSIOM_SEL_GPIO}, 552 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 553 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 554 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 555 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 556 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 557 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 558 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 559 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 560 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 561 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 562 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 563 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 564 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 565 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 566 {1u, 26u, P14_6, HSIOM_SEL_GPIO}, 567 {1u, 27u, P14_7, HSIOM_SEL_GPIO}, 568 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 569 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 570 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 571 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 572 {2u, 0u, P16_0, HSIOM_SEL_GPIO}, 573 {2u, 1u, P16_1, HSIOM_SEL_GPIO}, 574 {2u, 2u, P16_2, HSIOM_SEL_GPIO}, 575 {2u, 3u, P16_3, HSIOM_SEL_GPIO}, 576 {2u, 4u, P16_4, HSIOM_SEL_GPIO}, 577 {2u, 5u, P16_5, HSIOM_SEL_GPIO}, 578 {2u, 6u, P16_6, HSIOM_SEL_GPIO}, 579 {2u, 7u, P16_7, HSIOM_SEL_GPIO}, 580 {2u, 8u, P17_0, HSIOM_SEL_GPIO}, 581 {2u, 9u, P17_1, HSIOM_SEL_GPIO}, 582 {2u, 10u, P17_2, HSIOM_SEL_GPIO}, 583 {2u, 11u, P17_3, HSIOM_SEL_GPIO}, 584 {2u, 12u, P17_4, HSIOM_SEL_GPIO}, 585 {2u, 13u, P17_5, HSIOM_SEL_GPIO}, 586 {2u, 14u, P17_6, HSIOM_SEL_GPIO}, 587 {2u, 15u, P17_7, HSIOM_SEL_GPIO}, 588 {2u, 16u, P18_0, HSIOM_SEL_GPIO}, 589 {2u, 17u, P18_1, HSIOM_SEL_GPIO}, 590 {2u, 18u, P18_2, HSIOM_SEL_GPIO}, 591 {2u, 19u, P18_3, HSIOM_SEL_GPIO}, 592 {2u, 20u, P18_4, HSIOM_SEL_GPIO}, 593 {2u, 21u, P18_5, HSIOM_SEL_GPIO}, 594 {2u, 22u, P18_6, HSIOM_SEL_GPIO}, 595 {2u, 23u, P18_7, HSIOM_SEL_GPIO}, 596 {2u, 24u, P19_0, HSIOM_SEL_GPIO}, 597 {2u, 25u, P19_1, HSIOM_SEL_GPIO}, 598 {2u, 26u, P19_2, HSIOM_SEL_GPIO}, 599 {2u, 27u, P19_3, HSIOM_SEL_GPIO}, 600 {2u, 28u, P19_4, HSIOM_SEL_GPIO}, 601 {2u, 29u, P20_0, HSIOM_SEL_GPIO}, 602 {2u, 30u, P20_1, HSIOM_SEL_GPIO}, 603 {2u, 31u, P20_2, HSIOM_SEL_GPIO}, 604 {0u, 8u, P32_0, HSIOM_SEL_GPIO}, 605 {0u, 9u, P32_1, HSIOM_SEL_GPIO}, 606 {0u, 10u, P32_2, HSIOM_SEL_GPIO}, 607 {0u, 11u, P32_3, HSIOM_SEL_GPIO}, 608 {0u, 12u, P32_4, HSIOM_SEL_GPIO}, 609 {0u, 13u, P32_5, HSIOM_SEL_GPIO}, 610 {0u, 14u, P32_6, HSIOM_SEL_GPIO}, 611 {0u, 15u, P32_7, HSIOM_SEL_GPIO}, 612 }; 613 614 /* Connections for: peri_tr_io_input */ 615 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 616 to know the index of the input or output trigger line. Store that in the channel_num field 617 instead. */ 618 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[48] = { 619 {0u, 0u, P1_2, P1_2_PERI_TR_IO_INPUT0}, 620 {0u, 1u, P1_3, P1_3_PERI_TR_IO_INPUT1}, 621 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 622 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 623 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 624 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 625 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 626 {0u, 7u, P2_5, P2_5_PERI_TR_IO_INPUT7}, 627 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 628 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 629 {0u, 12u, P4_2, P4_2_PERI_TR_IO_INPUT12}, 630 {0u, 13u, P4_3, P4_3_PERI_TR_IO_INPUT13}, 631 {0u, 32u, P4_5, P4_5_PERI_TR_IO_INPUT32}, 632 {0u, 33u, P4_6, P4_6_PERI_TR_IO_INPUT33}, 633 {0u, 38u, P5_0, P5_0_PERI_TR_IO_INPUT38}, 634 {0u, 39u, P5_1, P5_1_PERI_TR_IO_INPUT39}, 635 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 636 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 637 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 638 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 639 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 640 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 641 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 642 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 643 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 644 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 645 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 646 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 647 {0u, 24u, P14_6, P14_6_PERI_TR_IO_INPUT24}, 648 {0u, 25u, P14_7, P14_7_PERI_TR_IO_INPUT25}, 649 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 650 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 651 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 652 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 653 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 654 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 655 {0u, 34u, P30_0, P30_0_PERI_TR_IO_INPUT34}, 656 {0u, 35u, P30_1, P30_1_PERI_TR_IO_INPUT35}, 657 {0u, 36u, P30_2, P30_2_PERI_TR_IO_INPUT36}, 658 {0u, 37u, P30_3, P30_3_PERI_TR_IO_INPUT37}, 659 {0u, 40u, P32_0, P32_0_PERI_TR_IO_INPUT40}, 660 {0u, 41u, P32_1, P32_1_PERI_TR_IO_INPUT41}, 661 {0u, 42u, P32_2, P32_2_PERI_TR_IO_INPUT42}, 662 {0u, 43u, P32_3, P32_3_PERI_TR_IO_INPUT43}, 663 {0u, 44u, P32_4, P32_4_PERI_TR_IO_INPUT44}, 664 {0u, 45u, P32_5, P32_5_PERI_TR_IO_INPUT45}, 665 {0u, 46u, P32_6, P32_6_PERI_TR_IO_INPUT46}, 666 {0u, 47u, P32_7, P32_7_PERI_TR_IO_INPUT47}, 667 }; 668 669 /* Connections for: peri_tr_io_output */ 670 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 671 to know the index of the input or output trigger line. Store that in the channel_num field 672 instead. */ 673 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6] = { 674 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 675 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 676 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 677 {0u, 1u, P8_4, P8_4_PERI_TR_IO_OUTPUT1}, 678 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 679 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 680 }; 681 682 /* Connections for: scb_i2c_scl */ 683 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[23] = { 684 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 685 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 686 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 687 {8u, 0u, P1_6, P1_6_SCB8_I2C_SCL}, 688 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 689 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 690 {5u, 0u, P4_2, P4_2_SCB5_I2C_SCL}, 691 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 692 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 693 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 694 {8u, 0u, P12_2, P12_2_SCB8_I2C_SCL}, 695 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 696 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 697 {9u, 0u, P15_2, P15_2_SCB9_I2C_SCL}, 698 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 699 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 700 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 701 {1u, 0u, P20_5, P20_5_SCB1_I2C_SCL}, 702 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 703 {7u, 0u, P23_2, P23_2_SCB7_I2C_SCL}, 704 {10u, 0u, P28_2, P28_2_SCB10_I2C_SCL}, 705 {9u, 0u, P30_0, P30_0_SCB9_I2C_SCL}, 706 {10u, 0u, P32_2, P32_2_SCB10_I2C_SCL}, 707 }; 708 709 /* Connections for: scb_i2c_sda */ 710 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[23] = { 711 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 712 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 713 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 714 {8u, 0u, P1_5, P1_5_SCB8_I2C_SDA}, 715 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 716 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 717 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 718 {9u, 0u, P4_6, P4_6_SCB9_I2C_SDA}, 719 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 720 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 721 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 722 {8u, 0u, P12_1, P12_1_SCB8_I2C_SDA}, 723 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 724 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 725 {9u, 0u, P15_1, P15_1_SCB9_I2C_SDA}, 726 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 727 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 728 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 729 {1u, 0u, P20_4, P20_4_SCB1_I2C_SDA}, 730 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 731 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 732 {10u, 0u, P28_1, P28_1_SCB10_I2C_SDA}, 733 {10u, 0u, P32_1, P32_1_SCB10_I2C_SDA}, 734 }; 735 736 /* Connections for: scb_spi_m_clk */ 737 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[25] = { 738 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 739 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 740 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 741 {8u, 0u, P1_6, P1_6_SCB8_SPI_CLK}, 742 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 743 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 744 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 745 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 746 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 747 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 748 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 749 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 750 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 751 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 752 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 753 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 754 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 755 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 756 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 757 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 758 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 759 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 760 {10u, 0u, P28_2, P28_2_SCB10_SPI_CLK}, 761 {9u, 0u, P30_0, P30_0_SCB9_SPI_CLK}, 762 {10u, 0u, P32_2, P32_2_SCB10_SPI_CLK}, 763 }; 764 765 /* Connections for: scb_spi_m_miso */ 766 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[24] = { 767 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 768 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 769 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 770 {8u, 0u, P1_4, P1_4_SCB8_SPI_MISO}, 771 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 772 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 773 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 774 {9u, 0u, P4_5, P4_5_SCB9_SPI_MISO}, 775 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 776 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 777 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 778 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 779 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 780 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 781 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 782 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 783 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 784 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 785 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 786 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 787 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 788 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 789 {10u, 0u, P28_0, P28_0_SCB10_SPI_MISO}, 790 {10u, 0u, P32_0, P32_0_SCB10_SPI_MISO}, 791 }; 792 793 /* Connections for: scb_spi_m_mosi */ 794 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[24] = { 795 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 796 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 797 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 798 {8u, 0u, P1_5, P1_5_SCB8_SPI_MOSI}, 799 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 800 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 801 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 802 {9u, 0u, P4_6, P4_6_SCB9_SPI_MOSI}, 803 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 804 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 805 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 806 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 807 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 808 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 809 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 810 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 811 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 812 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 813 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 814 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 815 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 816 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 817 {10u, 0u, P28_1, P28_1_SCB10_SPI_MOSI}, 818 {10u, 0u, P32_1, P32_1_SCB10_SPI_MOSI}, 819 }; 820 821 /* Connections for: scb_spi_m_select0 */ 822 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[25] = { 823 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 824 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 825 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 826 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 827 {8u, 0u, P2_6, P2_6_SCB8_SPI_SELECT0}, 828 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 829 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 830 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 831 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 832 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 833 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 834 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 835 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 836 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 837 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 838 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 839 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 840 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 841 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 842 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 843 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 844 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 845 {10u, 0u, P28_3, P28_3_SCB10_SPI_SELECT0}, 846 {9u, 0u, P30_1, P30_1_SCB9_SPI_SELECT0}, 847 {10u, 0u, P32_3, P32_3_SCB10_SPI_SELECT0}, 848 }; 849 850 /* Connections for: scb_spi_m_select1 */ 851 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[21] = { 852 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 853 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 854 {8u, 0u, P2_7, P2_7_SCB8_SPI_SELECT1}, 855 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 856 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 857 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 858 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 859 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 860 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 861 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 862 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 863 {9u, 0u, P16_0, P16_0_SCB9_SPI_SELECT1}, 864 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 865 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 866 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 867 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 868 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 869 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 870 {10u, 0u, P28_4, P28_4_SCB10_SPI_SELECT1}, 871 {9u, 0u, P30_2, P30_2_SCB9_SPI_SELECT1}, 872 {10u, 0u, P32_4, P32_4_SCB10_SPI_SELECT1}, 873 }; 874 875 /* Connections for: scb_spi_m_select2 */ 876 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[20] = { 877 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 878 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 879 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 880 {8u, 0u, P3_6, P3_6_SCB8_SPI_SELECT2}, 881 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 882 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 883 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 884 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 885 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 886 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 887 {9u, 0u, P16_1, P16_1_SCB9_SPI_SELECT2}, 888 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 889 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 890 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 891 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 892 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 893 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 894 {10u, 0u, P28_5, P28_5_SCB10_SPI_SELECT2}, 895 {9u, 0u, P30_3, P30_3_SCB9_SPI_SELECT2}, 896 {10u, 0u, P32_5, P32_5_SCB10_SPI_SELECT2}, 897 }; 898 899 /* Connections for: scb_spi_m_select3 */ 900 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8] = { 901 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 902 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 903 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 904 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 905 {9u, 0u, P16_2, P16_2_SCB9_SPI_SELECT3}, 906 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 907 {10u, 0u, P28_6, P28_6_SCB10_SPI_SELECT3}, 908 {10u, 0u, P32_6, P32_6_SCB10_SPI_SELECT3}, 909 }; 910 911 /* Connections for: scb_spi_s_clk */ 912 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[25] = { 913 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 914 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 915 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 916 {8u, 0u, P1_6, P1_6_SCB8_SPI_CLK}, 917 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 918 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 919 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 920 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 921 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 922 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 923 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 924 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 925 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 926 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 927 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 928 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 929 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 930 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 931 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 932 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 933 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 934 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 935 {10u, 0u, P28_2, P28_2_SCB10_SPI_CLK}, 936 {9u, 0u, P30_0, P30_0_SCB9_SPI_CLK}, 937 {10u, 0u, P32_2, P32_2_SCB10_SPI_CLK}, 938 }; 939 940 /* Connections for: scb_spi_s_miso */ 941 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[24] = { 942 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 943 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 944 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 945 {8u, 0u, P1_4, P1_4_SCB8_SPI_MISO}, 946 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 947 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 948 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 949 {9u, 0u, P4_5, P4_5_SCB9_SPI_MISO}, 950 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 951 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 952 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 953 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 954 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 955 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 956 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 957 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 958 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 959 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 960 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 961 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 962 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 963 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 964 {10u, 0u, P28_0, P28_0_SCB10_SPI_MISO}, 965 {10u, 0u, P32_0, P32_0_SCB10_SPI_MISO}, 966 }; 967 968 /* Connections for: scb_spi_s_mosi */ 969 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[24] = { 970 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 971 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 972 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 973 {8u, 0u, P1_5, P1_5_SCB8_SPI_MOSI}, 974 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 975 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 976 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 977 {9u, 0u, P4_6, P4_6_SCB9_SPI_MOSI}, 978 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 979 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 980 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 981 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 982 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 983 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 984 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 985 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 986 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 987 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 988 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 989 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 990 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 991 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 992 {10u, 0u, P28_1, P28_1_SCB10_SPI_MOSI}, 993 {10u, 0u, P32_1, P32_1_SCB10_SPI_MOSI}, 994 }; 995 996 /* Connections for: scb_spi_s_select0 */ 997 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[25] = { 998 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 999 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 1000 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 1001 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 1002 {8u, 0u, P2_6, P2_6_SCB8_SPI_SELECT0}, 1003 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 1004 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 1005 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 1006 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 1007 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 1008 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 1009 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 1010 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 1011 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 1012 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 1013 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 1014 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 1015 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 1016 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 1017 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 1018 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 1019 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 1020 {10u, 0u, P28_3, P28_3_SCB10_SPI_SELECT0}, 1021 {9u, 0u, P30_1, P30_1_SCB9_SPI_SELECT0}, 1022 {10u, 0u, P32_3, P32_3_SCB10_SPI_SELECT0}, 1023 }; 1024 1025 /* Connections for: scb_spi_s_select1 */ 1026 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[21] = { 1027 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 1028 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 1029 {8u, 0u, P2_7, P2_7_SCB8_SPI_SELECT1}, 1030 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 1031 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 1032 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 1033 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 1034 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 1035 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 1036 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 1037 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 1038 {9u, 0u, P16_0, P16_0_SCB9_SPI_SELECT1}, 1039 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 1040 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 1041 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 1042 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 1043 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 1044 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 1045 {10u, 0u, P28_4, P28_4_SCB10_SPI_SELECT1}, 1046 {9u, 0u, P30_2, P30_2_SCB9_SPI_SELECT1}, 1047 {10u, 0u, P32_4, P32_4_SCB10_SPI_SELECT1}, 1048 }; 1049 1050 /* Connections for: scb_spi_s_select2 */ 1051 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[20] = { 1052 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 1053 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 1054 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 1055 {8u, 0u, P3_6, P3_6_SCB8_SPI_SELECT2}, 1056 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 1057 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 1058 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 1059 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 1060 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 1061 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 1062 {9u, 0u, P16_1, P16_1_SCB9_SPI_SELECT2}, 1063 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 1064 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 1065 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 1066 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 1067 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 1068 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 1069 {10u, 0u, P28_5, P28_5_SCB10_SPI_SELECT2}, 1070 {9u, 0u, P30_3, P30_3_SCB9_SPI_SELECT2}, 1071 {10u, 0u, P32_5, P32_5_SCB10_SPI_SELECT2}, 1072 }; 1073 1074 /* Connections for: scb_spi_s_select3 */ 1075 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8] = { 1076 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 1077 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 1078 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 1079 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 1080 {9u, 0u, P16_2, P16_2_SCB9_SPI_SELECT3}, 1081 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 1082 {10u, 0u, P28_6, P28_6_SCB10_SPI_SELECT3}, 1083 {10u, 0u, P32_6, P32_6_SCB10_SPI_SELECT3}, 1084 }; 1085 1086 /* Connections for: scb_uart_cts */ 1087 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[21] = { 1088 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 1089 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 1090 {8u, 0u, P2_6, P2_6_SCB8_UART_CTS}, 1091 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 1092 {5u, 0u, P4_3, P4_3_SCB5_UART_CTS}, 1093 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 1094 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 1095 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 1096 {8u, 0u, P12_3, P12_3_SCB8_UART_CTS}, 1097 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 1098 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 1099 {9u, 0u, P15_3, P15_3_SCB9_UART_CTS}, 1100 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 1101 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 1102 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 1103 {1u, 0u, P20_6, P20_6_SCB1_UART_CTS}, 1104 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 1105 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 1106 {10u, 0u, P28_3, P28_3_SCB10_UART_CTS}, 1107 {9u, 0u, P30_1, P30_1_SCB9_UART_CTS}, 1108 {10u, 0u, P32_3, P32_3_SCB10_UART_CTS}, 1109 }; 1110 1111 /* Connections for: scb_uart_rts */ 1112 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[21] = { 1113 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 1114 {8u, 0u, P1_6, P1_6_SCB8_UART_RTS}, 1115 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 1116 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 1117 {5u, 0u, P4_2, P4_2_SCB5_UART_RTS}, 1118 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 1119 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 1120 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 1121 {8u, 0u, P12_2, P12_2_SCB8_UART_RTS}, 1122 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 1123 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 1124 {9u, 0u, P15_2, P15_2_SCB9_UART_RTS}, 1125 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 1126 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 1127 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 1128 {1u, 0u, P20_5, P20_5_SCB1_UART_RTS}, 1129 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 1130 {7u, 0u, P23_2, P23_2_SCB7_UART_RTS}, 1131 {10u, 0u, P28_2, P28_2_SCB10_UART_RTS}, 1132 {9u, 0u, P30_0, P30_0_SCB9_UART_RTS}, 1133 {10u, 0u, P32_2, P32_2_SCB10_UART_RTS}, 1134 }; 1135 1136 /* Connections for: scb_uart_rx */ 1137 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[21] = { 1138 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 1139 {8u, 0u, P1_4, P1_4_SCB8_UART_RX}, 1140 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 1141 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 1142 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 1143 {9u, 0u, P4_5, P4_5_SCB9_UART_RX}, 1144 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 1145 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 1146 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 1147 {8u, 0u, P12_0, P12_0_SCB8_UART_RX}, 1148 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 1149 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 1150 {9u, 0u, P15_0, P15_0_SCB9_UART_RX}, 1151 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 1152 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 1153 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 1154 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 1155 {6u, 0u, P21_7, P21_7_SCB6_UART_RX}, 1156 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 1157 {10u, 0u, P28_0, P28_0_SCB10_UART_RX}, 1158 {10u, 0u, P32_0, P32_0_SCB10_UART_RX}, 1159 }; 1160 1161 /* Connections for: scb_uart_tx */ 1162 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[21] = { 1163 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 1164 {8u, 0u, P1_5, P1_5_SCB8_UART_TX}, 1165 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 1166 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 1167 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 1168 {9u, 0u, P4_6, P4_6_SCB9_UART_TX}, 1169 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 1170 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 1171 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 1172 {8u, 0u, P12_1, P12_1_SCB8_UART_TX}, 1173 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 1174 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 1175 {9u, 0u, P15_1, P15_1_SCB9_UART_TX}, 1176 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 1177 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 1178 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 1179 {1u, 0u, P20_4, P20_4_SCB1_UART_TX}, 1180 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 1181 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 1182 {10u, 0u, P28_1, P28_1_SCB10_UART_TX}, 1183 {10u, 0u, P32_1, P32_1_SCB10_UART_TX}, 1184 }; 1185 1186 /* Connections for: sdhc_card_cmd */ 1187 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2] = { 1188 {0u, 0u, P6_3, P6_3_SDHC0_CARD_CMD}, 1189 {0u, 0u, P24_3, P24_3_SDHC0_CARD_CMD}, 1190 }; 1191 1192 /* Connections for: sdhc_card_dat_3to0 */ 1193 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8] = { 1194 {0u, 0u, P7_1, P7_1_SDHC0_CARD_DAT_3TO00}, 1195 {0u, 1u, P7_2, P7_2_SDHC0_CARD_DAT_3TO01}, 1196 {0u, 2u, P7_3, P7_3_SDHC0_CARD_DAT_3TO02}, 1197 {0u, 3u, P7_4, P7_4_SDHC0_CARD_DAT_3TO03}, 1198 {0u, 0u, P25_0, P25_0_SDHC0_CARD_DAT_3TO00}, 1199 {0u, 1u, P25_1, P25_1_SDHC0_CARD_DAT_3TO01}, 1200 {0u, 2u, P25_2, P25_2_SDHC0_CARD_DAT_3TO02}, 1201 {0u, 3u, P25_3, P25_3_SDHC0_CARD_DAT_3TO03}, 1202 }; 1203 1204 /* Connections for: sdhc_card_dat_7to4 */ 1205 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[8] = { 1206 {0u, 0u, P7_5, P7_5_SDHC0_CARD_DAT_7TO40}, 1207 {0u, 1u, P8_0, P8_0_SDHC0_CARD_DAT_7TO41}, 1208 {0u, 2u, P8_1, P8_1_SDHC0_CARD_DAT_7TO42}, 1209 {0u, 3u, P8_2, P8_2_SDHC0_CARD_DAT_7TO43}, 1210 {0u, 0u, P25_4, P25_4_SDHC0_CARD_DAT_7TO40}, 1211 {0u, 1u, P25_5, P25_5_SDHC0_CARD_DAT_7TO41}, 1212 {0u, 2u, P25_6, P25_6_SDHC0_CARD_DAT_7TO42}, 1213 {0u, 3u, P25_7, P25_7_SDHC0_CARD_DAT_7TO43}, 1214 }; 1215 1216 /* Connections for: sdhc_card_detect_n */ 1217 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2] = { 1218 {0u, 0u, P6_5, P6_5_SDHC0_CARD_DETECT_N}, 1219 {0u, 0u, P24_0, P24_0_SDHC0_CARD_DETECT_N}, 1220 }; 1221 1222 /* Connections for: sdhc_card_if_pwr_en */ 1223 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2] = { 1224 {0u, 0u, P7_0, P7_0_SDHC0_CARD_IF_PWR_EN}, 1225 {0u, 0u, P24_4, P24_4_SDHC0_CARD_IF_PWR_EN}, 1226 }; 1227 1228 /* Connections for: sdhc_card_mech_write_prot */ 1229 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2] = { 1230 {0u, 0u, P6_2, P6_2_SDHC0_CARD_MECH_WRITE_PROT}, 1231 {0u, 0u, P24_1, P24_1_SDHC0_CARD_MECH_WRITE_PROT}, 1232 }; 1233 1234 /* Connections for: sdhc_clk_card */ 1235 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2] = { 1236 {0u, 0u, P6_4, P6_4_SDHC0_CLK_CARD}, 1237 {0u, 0u, P24_2, P24_2_SDHC0_CLK_CARD}, 1238 }; 1239 1240 /* Connections for: smif_spi_clk */ 1241 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[2] = { 1242 {0u, 0u, P6_3, P6_3_SMIF0_SPIHB_CLK}, 1243 {0u, 0u, P24_1, P24_1_SMIF0_SPIHB_CLK}, 1244 }; 1245 1246 /* Connections for: smif_spi_data0 */ 1247 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[2] = { 1248 {0u, 0u, P7_1, P7_1_SMIF0_SPIHB_DATA0}, 1249 {0u, 0u, P25_0, P25_0_SMIF0_SPIHB_DATA0}, 1250 }; 1251 1252 /* Connections for: smif_spi_data1 */ 1253 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[2] = { 1254 {0u, 0u, P7_2, P7_2_SMIF0_SPIHB_DATA1}, 1255 {0u, 0u, P25_1, P25_1_SMIF0_SPIHB_DATA1}, 1256 }; 1257 1258 /* Connections for: smif_spi_data2 */ 1259 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[2] = { 1260 {0u, 0u, P7_3, P7_3_SMIF0_SPIHB_DATA2}, 1261 {0u, 0u, P25_2, P25_2_SMIF0_SPIHB_DATA2}, 1262 }; 1263 1264 /* Connections for: smif_spi_data3 */ 1265 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[2] = { 1266 {0u, 0u, P7_4, P7_4_SMIF0_SPIHB_DATA3}, 1267 {0u, 0u, P25_3, P25_3_SMIF0_SPIHB_DATA3}, 1268 }; 1269 1270 /* Connections for: smif_spi_data4 */ 1271 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[2] = { 1272 {0u, 0u, P7_5, P7_5_SMIF0_SPIHB_DATA4}, 1273 {0u, 0u, P25_4, P25_4_SMIF0_SPIHB_DATA4}, 1274 }; 1275 1276 /* Connections for: smif_spi_data5 */ 1277 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[2] = { 1278 {0u, 0u, P8_0, P8_0_SMIF0_SPIHB_DATA5}, 1279 {0u, 0u, P25_5, P25_5_SMIF0_SPIHB_DATA5}, 1280 }; 1281 1282 /* Connections for: smif_spi_data6 */ 1283 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[2] = { 1284 {0u, 0u, P8_1, P8_1_SMIF0_SPIHB_DATA6}, 1285 {0u, 0u, P25_6, P25_6_SMIF0_SPIHB_DATA6}, 1286 }; 1287 1288 /* Connections for: smif_spi_data7 */ 1289 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[2] = { 1290 {0u, 0u, P8_2, P8_2_SMIF0_SPIHB_DATA7}, 1291 {0u, 0u, P25_7, P25_7_SMIF0_SPIHB_DATA7}, 1292 }; 1293 1294 /* Connections for: smif_spi_rwds */ 1295 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[2] = { 1296 {0u, 0u, P6_4, P6_4_SMIF0_SPIHB_RWDS}, 1297 {0u, 0u, P24_2, P24_2_SMIF0_SPIHB_RWDS}, 1298 }; 1299 1300 /* Connections for: smif_spi_select0 */ 1301 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[2] = { 1302 {0u, 0u, P6_5, P6_5_SMIF0_SPIHB_SELECT0}, 1303 {0u, 0u, P24_3, P24_3_SMIF0_SPIHB_SELECT0}, 1304 }; 1305 1306 /* Connections for: smif_spi_select1 */ 1307 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[2] = { 1308 {0u, 0u, P7_0, P7_0_SMIF0_SPIHB_SELECT1}, 1309 {0u, 0u, P24_4, P24_4_SMIF0_SPIHB_SELECT1}, 1310 }; 1311 1312 /* Connections for: tcpwm_line */ 1313 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[227] = { 1314 {2u, 0u, P0_0, P0_0_TCPWM0_LINE512}, 1315 {4u, 18u, P0_0, P0_0_TCPWM1_LINE18}, 1316 {4u, 17u, P0_1, P0_1_TCPWM1_LINE17}, 1317 {4u, 14u, P0_2, P0_2_TCPWM1_LINE14}, 1318 {4u, 13u, P0_3, P0_3_TCPWM1_LINE13}, 1319 {4u, 12u, P1_0, P1_0_TCPWM1_LINE12}, 1320 {6u, 4u, P1_0, P1_0_TCPWM1_LINE516}, 1321 {4u, 11u, P1_1, P1_1_TCPWM1_LINE11}, 1322 {6u, 5u, P1_1, P1_1_TCPWM1_LINE517}, 1323 {4u, 10u, P1_2, P1_2_TCPWM1_LINE10}, 1324 {6u, 6u, P1_2, P1_2_TCPWM1_LINE518}, 1325 {4u, 8u, P1_3, P1_3_TCPWM1_LINE8}, 1326 {6u, 7u, P1_3, P1_3_TCPWM1_LINE519}, 1327 {4u, 71u, P1_4, P1_4_TCPWM1_LINE71}, 1328 {4u, 7u, P2_0, P2_0_TCPWM1_LINE7}, 1329 {4u, 6u, P2_1, P2_1_TCPWM1_LINE6}, 1330 {4u, 5u, P2_2, P2_2_TCPWM1_LINE5}, 1331 {4u, 4u, P2_3, P2_3_TCPWM1_LINE4}, 1332 {4u, 3u, P2_4, P2_4_TCPWM1_LINE3}, 1333 {4u, 2u, P2_5, P2_5_TCPWM1_LINE2}, 1334 {4u, 72u, P2_6, P2_6_TCPWM1_LINE72}, 1335 {4u, 73u, P2_7, P2_7_TCPWM1_LINE73}, 1336 {4u, 1u, P3_0, P3_0_TCPWM1_LINE1}, 1337 {4u, 0u, P3_1, P3_1_TCPWM1_LINE0}, 1338 {5u, 3u, P3_2, P3_2_TCPWM1_LINE259}, 1339 {5u, 2u, P3_3, P3_3_TCPWM1_LINE258}, 1340 {5u, 1u, P3_4, P3_4_TCPWM1_LINE257}, 1341 {5u, 0u, P3_5, P3_5_TCPWM1_LINE256}, 1342 {4u, 74u, P3_6, P3_6_TCPWM1_LINE74}, 1343 {4u, 75u, P3_7, P3_7_TCPWM1_LINE75}, 1344 {4u, 4u, P4_0, P4_0_TCPWM1_LINE4}, 1345 {4u, 5u, P4_1, P4_1_TCPWM1_LINE5}, 1346 {4u, 6u, P4_2, P4_2_TCPWM1_LINE6}, 1347 {4u, 7u, P4_3, P4_3_TCPWM1_LINE7}, 1348 {4u, 8u, P4_4, P4_4_TCPWM1_LINE8}, 1349 {1u, 0u, P5_0, P5_0_TCPWM0_LINE256}, 1350 {4u, 9u, P5_0, P5_0_TCPWM1_LINE9}, 1351 {6u, 10u, P5_0, P5_0_TCPWM1_LINE522}, 1352 {4u, 10u, P5_1, P5_1_TCPWM1_LINE10}, 1353 {4u, 11u, P5_2, P5_2_TCPWM1_LINE11}, 1354 {4u, 12u, P5_3, P5_3_TCPWM1_LINE12}, 1355 {4u, 13u, P5_4, P5_4_TCPWM1_LINE13}, 1356 {6u, 11u, P5_4, P5_4_TCPWM1_LINE523}, 1357 {4u, 14u, P5_5, P5_5_TCPWM1_LINE14}, 1358 {0u, 0u, P6_0, P6_0_TCPWM0_LINE0}, 1359 {5u, 0u, P6_0, P6_0_TCPWM1_LINE256}, 1360 {4u, 0u, P6_1, P6_1_TCPWM1_LINE0}, 1361 {5u, 1u, P6_2, P6_2_TCPWM1_LINE257}, 1362 {6u, 12u, P6_2, P6_2_TCPWM1_LINE524}, 1363 {4u, 1u, P6_3, P6_3_TCPWM1_LINE1}, 1364 {5u, 2u, P6_4, P6_4_TCPWM1_LINE258}, 1365 {4u, 2u, P6_5, P6_5_TCPWM1_LINE2}, 1366 {5u, 3u, P6_6, P6_6_TCPWM1_LINE259}, 1367 {4u, 3u, P6_7, P6_7_TCPWM1_LINE3}, 1368 {0u, 1u, P7_0, P7_0_TCPWM0_LINE1}, 1369 {5u, 4u, P7_0, P7_0_TCPWM1_LINE260}, 1370 {4u, 15u, P7_1, P7_1_TCPWM1_LINE15}, 1371 {5u, 5u, P7_2, P7_2_TCPWM1_LINE261}, 1372 {4u, 16u, P7_3, P7_3_TCPWM1_LINE16}, 1373 {5u, 6u, P7_4, P7_4_TCPWM1_LINE262}, 1374 {2u, 2u, P7_5, P7_5_TCPWM0_LINE514}, 1375 {4u, 17u, P7_5, P7_5_TCPWM1_LINE17}, 1376 {5u, 7u, P7_6, P7_6_TCPWM1_LINE263}, 1377 {4u, 18u, P7_7, P7_7_TCPWM1_LINE18}, 1378 {4u, 19u, P8_0, P8_0_TCPWM1_LINE19}, 1379 {6u, 8u, P8_0, P8_0_TCPWM1_LINE520}, 1380 {4u, 20u, P8_1, P8_1_TCPWM1_LINE20}, 1381 {4u, 21u, P8_2, P8_2_TCPWM1_LINE21}, 1382 {4u, 22u, P8_3, P8_3_TCPWM1_LINE22}, 1383 {4u, 23u, P8_4, P8_4_TCPWM1_LINE23}, 1384 {4u, 24u, P9_0, P9_0_TCPWM1_LINE24}, 1385 {6u, 9u, P9_0, P9_0_TCPWM1_LINE521}, 1386 {4u, 25u, P9_1, P9_1_TCPWM1_LINE25}, 1387 {4u, 26u, P9_2, P9_2_TCPWM1_LINE26}, 1388 {4u, 27u, P9_3, P9_3_TCPWM1_LINE27}, 1389 {4u, 28u, P10_0, P10_0_TCPWM1_LINE28}, 1390 {6u, 10u, P10_0, P10_0_TCPWM1_LINE522}, 1391 {4u, 29u, P10_1, P10_1_TCPWM1_LINE29}, 1392 {4u, 30u, P10_2, P10_2_TCPWM1_LINE30}, 1393 {4u, 31u, P10_3, P10_3_TCPWM1_LINE31}, 1394 {4u, 32u, P10_4, P10_4_TCPWM1_LINE32}, 1395 {6u, 11u, P10_4, P10_4_TCPWM1_LINE523}, 1396 {4u, 33u, P10_5, P10_5_TCPWM1_LINE33}, 1397 {4u, 34u, P10_6, P10_6_TCPWM1_LINE34}, 1398 {4u, 35u, P10_7, P10_7_TCPWM1_LINE35}, 1399 {4u, 61u, P11_0, P11_0_TCPWM1_LINE61}, 1400 {4u, 60u, P11_1, P11_1_TCPWM1_LINE60}, 1401 {4u, 59u, P11_2, P11_2_TCPWM1_LINE59}, 1402 {2u, 1u, P12_0, P12_0_TCPWM0_LINE513}, 1403 {4u, 36u, P12_0, P12_0_TCPWM1_LINE36}, 1404 {4u, 37u, P12_1, P12_1_TCPWM1_LINE37}, 1405 {4u, 38u, P12_2, P12_2_TCPWM1_LINE38}, 1406 {4u, 39u, P12_3, P12_3_TCPWM1_LINE39}, 1407 {4u, 40u, P12_4, P12_4_TCPWM1_LINE40}, 1408 {4u, 41u, P12_5, P12_5_TCPWM1_LINE41}, 1409 {4u, 42u, P12_6, P12_6_TCPWM1_LINE42}, 1410 {4u, 43u, P12_7, P12_7_TCPWM1_LINE43}, 1411 {5u, 8u, P13_0, P13_0_TCPWM1_LINE264}, 1412 {4u, 44u, P13_1, P13_1_TCPWM1_LINE44}, 1413 {0u, 2u, P13_2, P13_2_TCPWM0_LINE2}, 1414 {5u, 9u, P13_2, P13_2_TCPWM1_LINE265}, 1415 {4u, 45u, P13_3, P13_3_TCPWM1_LINE45}, 1416 {5u, 10u, P13_4, P13_4_TCPWM1_LINE266}, 1417 {6u, 4u, P13_4, P13_4_TCPWM1_LINE516}, 1418 {4u, 46u, P13_5, P13_5_TCPWM1_LINE46}, 1419 {5u, 11u, P13_6, P13_6_TCPWM1_LINE267}, 1420 {6u, 5u, P13_6, P13_6_TCPWM1_LINE517}, 1421 {4u, 47u, P13_7, P13_7_TCPWM1_LINE47}, 1422 {1u, 1u, P14_0, P14_0_TCPWM0_LINE257}, 1423 {4u, 48u, P14_0, P14_0_TCPWM1_LINE48}, 1424 {6u, 6u, P14_0, P14_0_TCPWM1_LINE518}, 1425 {4u, 49u, P14_1, P14_1_TCPWM1_LINE49}, 1426 {4u, 50u, P14_2, P14_2_TCPWM1_LINE50}, 1427 {6u, 7u, P14_2, P14_2_TCPWM1_LINE519}, 1428 {4u, 51u, P14_3, P14_3_TCPWM1_LINE51}, 1429 {4u, 52u, P14_4, P14_4_TCPWM1_LINE52}, 1430 {4u, 53u, P14_5, P14_5_TCPWM1_LINE53}, 1431 {4u, 54u, P14_6, P14_6_TCPWM1_LINE54}, 1432 {4u, 55u, P14_7, P14_7_TCPWM1_LINE55}, 1433 {4u, 56u, P15_0, P15_0_TCPWM1_LINE56}, 1434 {4u, 57u, P15_1, P15_1_TCPWM1_LINE57}, 1435 {4u, 58u, P15_2, P15_2_TCPWM1_LINE58}, 1436 {4u, 59u, P15_3, P15_3_TCPWM1_LINE59}, 1437 {4u, 60u, P16_0, P16_0_TCPWM1_LINE60}, 1438 {6u, 0u, P16_0, P16_0_TCPWM1_LINE512}, 1439 {4u, 61u, P16_1, P16_1_TCPWM1_LINE61}, 1440 {4u, 62u, P16_2, P16_2_TCPWM1_LINE62}, 1441 {6u, 1u, P16_2, P16_2_TCPWM1_LINE513}, 1442 {4u, 62u, P16_3, P16_3_TCPWM1_LINE62}, 1443 {4u, 68u, P16_4, P16_4_TCPWM1_LINE68}, 1444 {4u, 67u, P16_5, P16_5_TCPWM1_LINE67}, 1445 {4u, 66u, P16_6, P16_6_TCPWM1_LINE66}, 1446 {4u, 65u, P16_7, P16_7_TCPWM1_LINE65}, 1447 {4u, 61u, P17_0, P17_0_TCPWM1_LINE61}, 1448 {4u, 60u, P17_1, P17_1_TCPWM1_LINE60}, 1449 {4u, 59u, P17_2, P17_2_TCPWM1_LINE59}, 1450 {4u, 58u, P17_3, P17_3_TCPWM1_LINE58}, 1451 {6u, 3u, P17_3, P17_3_TCPWM1_LINE515}, 1452 {4u, 57u, P17_4, P17_4_TCPWM1_LINE57}, 1453 {4u, 56u, P17_5, P17_5_TCPWM1_LINE56}, 1454 {6u, 2u, P17_5, P17_5_TCPWM1_LINE514}, 1455 {5u, 4u, P17_6, P17_6_TCPWM1_LINE260}, 1456 {5u, 5u, P17_7, P17_7_TCPWM1_LINE261}, 1457 {5u, 6u, P18_0, P18_0_TCPWM1_LINE262}, 1458 {6u, 0u, P18_0, P18_0_TCPWM1_LINE512}, 1459 {5u, 7u, P18_1, P18_1_TCPWM1_LINE263}, 1460 {4u, 55u, P18_2, P18_2_TCPWM1_LINE55}, 1461 {6u, 1u, P18_2, P18_2_TCPWM1_LINE513}, 1462 {4u, 54u, P18_3, P18_3_TCPWM1_LINE54}, 1463 {1u, 2u, P18_4, P18_4_TCPWM0_LINE258}, 1464 {4u, 53u, P18_4, P18_4_TCPWM1_LINE53}, 1465 {6u, 2u, P18_4, P18_4_TCPWM1_LINE514}, 1466 {4u, 52u, P18_5, P18_5_TCPWM1_LINE52}, 1467 {4u, 51u, P18_6, P18_6_TCPWM1_LINE51}, 1468 {6u, 3u, P18_6, P18_6_TCPWM1_LINE515}, 1469 {4u, 50u, P18_7, P18_7_TCPWM1_LINE50}, 1470 {5u, 3u, P19_0, P19_0_TCPWM1_LINE259}, 1471 {4u, 26u, P19_1, P19_1_TCPWM1_LINE26}, 1472 {4u, 27u, P19_2, P19_2_TCPWM1_LINE27}, 1473 {4u, 28u, P19_3, P19_3_TCPWM1_LINE28}, 1474 {4u, 29u, P19_4, P19_4_TCPWM1_LINE29}, 1475 {4u, 30u, P20_0, P20_0_TCPWM1_LINE30}, 1476 {4u, 49u, P20_1, P20_1_TCPWM1_LINE49}, 1477 {4u, 48u, P20_2, P20_2_TCPWM1_LINE48}, 1478 {4u, 47u, P20_3, P20_3_TCPWM1_LINE47}, 1479 {4u, 46u, P20_4, P20_4_TCPWM1_LINE46}, 1480 {4u, 45u, P20_5, P20_5_TCPWM1_LINE45}, 1481 {4u, 44u, P20_6, P20_6_TCPWM1_LINE44}, 1482 {4u, 43u, P20_7, P20_7_TCPWM1_LINE43}, 1483 {4u, 42u, P21_0, P21_0_TCPWM1_LINE42}, 1484 {4u, 41u, P21_1, P21_1_TCPWM1_LINE41}, 1485 {4u, 40u, P21_2, P21_2_TCPWM1_LINE40}, 1486 {4u, 39u, P21_3, P21_3_TCPWM1_LINE39}, 1487 {4u, 38u, P21_4, P21_4_TCPWM1_LINE38}, 1488 {4u, 34u, P21_5, P21_5_TCPWM1_LINE34}, 1489 {4u, 37u, P21_5, P21_5_TCPWM1_LINE37}, 1490 {4u, 36u, P21_6, P21_6_TCPWM1_LINE36}, 1491 {4u, 35u, P21_7, P21_7_TCPWM1_LINE35}, 1492 {4u, 33u, P22_1, P22_1_TCPWM1_LINE33}, 1493 {4u, 32u, P22_2, P22_2_TCPWM1_LINE32}, 1494 {4u, 31u, P22_3, P22_3_TCPWM1_LINE31}, 1495 {4u, 30u, P22_4, P22_4_TCPWM1_LINE30}, 1496 {4u, 29u, P22_5, P22_5_TCPWM1_LINE29}, 1497 {6u, 8u, P22_5, P22_5_TCPWM1_LINE520}, 1498 {4u, 28u, P22_6, P22_6_TCPWM1_LINE28}, 1499 {4u, 27u, P22_7, P22_7_TCPWM1_LINE27}, 1500 {5u, 8u, P23_0, P23_0_TCPWM1_LINE264}, 1501 {5u, 9u, P23_1, P23_1_TCPWM1_LINE265}, 1502 {5u, 10u, P23_2, P23_2_TCPWM1_LINE266}, 1503 {5u, 11u, P23_3, P23_3_TCPWM1_LINE267}, 1504 {4u, 25u, P23_4, P23_4_TCPWM1_LINE25}, 1505 {6u, 9u, P23_4, P23_4_TCPWM1_LINE521}, 1506 {4u, 24u, P23_5, P23_5_TCPWM1_LINE24}, 1507 {4u, 23u, P23_6, P23_6_TCPWM1_LINE23}, 1508 {4u, 22u, P23_7, P23_7_TCPWM1_LINE22}, 1509 {4u, 63u, P28_0, P28_0_TCPWM1_LINE63}, 1510 {6u, 12u, P28_0, P28_0_TCPWM1_LINE524}, 1511 {4u, 64u, P28_1, P28_1_TCPWM1_LINE64}, 1512 {4u, 65u, P28_2, P28_2_TCPWM1_LINE65}, 1513 {4u, 66u, P28_3, P28_3_TCPWM1_LINE66}, 1514 {4u, 67u, P28_4, P28_4_TCPWM1_LINE67}, 1515 {4u, 68u, P28_5, P28_5_TCPWM1_LINE68}, 1516 {4u, 69u, P28_6, P28_6_TCPWM1_LINE69}, 1517 {4u, 70u, P28_7, P28_7_TCPWM1_LINE70}, 1518 {4u, 76u, P29_0, P29_0_TCPWM1_LINE76}, 1519 {4u, 77u, P29_1, P29_1_TCPWM1_LINE77}, 1520 {4u, 78u, P29_2, P29_2_TCPWM1_LINE78}, 1521 {4u, 79u, P29_3, P29_3_TCPWM1_LINE79}, 1522 {4u, 80u, P29_4, P29_4_TCPWM1_LINE80}, 1523 {4u, 81u, P29_5, P29_5_TCPWM1_LINE81}, 1524 {4u, 82u, P29_6, P29_6_TCPWM1_LINE82}, 1525 {4u, 83u, P29_7, P29_7_TCPWM1_LINE83}, 1526 {4u, 83u, P30_0, P30_0_TCPWM1_LINE83}, 1527 {4u, 82u, P30_1, P30_1_TCPWM1_LINE82}, 1528 {4u, 81u, P30_2, P30_2_TCPWM1_LINE81}, 1529 {4u, 80u, P30_3, P30_3_TCPWM1_LINE80}, 1530 {4u, 79u, P31_0, P31_0_TCPWM1_LINE79}, 1531 {4u, 78u, P31_1, P31_1_TCPWM1_LINE78}, 1532 {4u, 77u, P31_2, P31_2_TCPWM1_LINE77}, 1533 {4u, 76u, P32_0, P32_0_TCPWM1_LINE76}, 1534 {4u, 75u, P32_1, P32_1_TCPWM1_LINE75}, 1535 {4u, 74u, P32_2, P32_2_TCPWM1_LINE74}, 1536 {4u, 73u, P32_3, P32_3_TCPWM1_LINE73}, 1537 {4u, 72u, P32_4, P32_4_TCPWM1_LINE72}, 1538 {4u, 71u, P32_5, P32_5_TCPWM1_LINE71}, 1539 {4u, 70u, P32_6, P32_6_TCPWM1_LINE70}, 1540 {4u, 69u, P32_7, P32_7_TCPWM1_LINE69}, 1541 }; 1542 1543 /* Connections for: tcpwm_line_compl */ 1544 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[227] = { 1545 {4u, 22u, P0_0, P0_0_TCPWM1_LINE_COMPL22}, 1546 {2u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL512}, 1547 {4u, 18u, P0_1, P0_1_TCPWM1_LINE_COMPL18}, 1548 {4u, 17u, P0_2, P0_2_TCPWM1_LINE_COMPL17}, 1549 {4u, 14u, P0_3, P0_3_TCPWM1_LINE_COMPL14}, 1550 {4u, 13u, P1_0, P1_0_TCPWM1_LINE_COMPL13}, 1551 {4u, 12u, P1_1, P1_1_TCPWM1_LINE_COMPL12}, 1552 {4u, 11u, P1_2, P1_2_TCPWM1_LINE_COMPL11}, 1553 {4u, 10u, P1_3, P1_3_TCPWM1_LINE_COMPL10}, 1554 {4u, 70u, P1_4, P1_4_TCPWM1_LINE_COMPL70}, 1555 {4u, 8u, P2_0, P2_0_TCPWM1_LINE_COMPL8}, 1556 {4u, 7u, P2_1, P2_1_TCPWM1_LINE_COMPL7}, 1557 {4u, 6u, P2_2, P2_2_TCPWM1_LINE_COMPL6}, 1558 {4u, 5u, P2_3, P2_3_TCPWM1_LINE_COMPL5}, 1559 {4u, 4u, P2_4, P2_4_TCPWM1_LINE_COMPL4}, 1560 {6u, 4u, P2_4, P2_4_TCPWM1_LINE_COMPL516}, 1561 {4u, 3u, P2_5, P2_5_TCPWM1_LINE_COMPL3}, 1562 {6u, 5u, P2_5, P2_5_TCPWM1_LINE_COMPL517}, 1563 {4u, 71u, P2_6, P2_6_TCPWM1_LINE_COMPL71}, 1564 {4u, 72u, P2_7, P2_7_TCPWM1_LINE_COMPL72}, 1565 {4u, 2u, P3_0, P3_0_TCPWM1_LINE_COMPL2}, 1566 {6u, 6u, P3_0, P3_0_TCPWM1_LINE_COMPL518}, 1567 {4u, 1u, P3_1, P3_1_TCPWM1_LINE_COMPL1}, 1568 {6u, 7u, P3_1, P3_1_TCPWM1_LINE_COMPL519}, 1569 {4u, 0u, P3_2, P3_2_TCPWM1_LINE_COMPL0}, 1570 {5u, 3u, P3_3, P3_3_TCPWM1_LINE_COMPL259}, 1571 {5u, 2u, P3_4, P3_4_TCPWM1_LINE_COMPL258}, 1572 {5u, 1u, P3_5, P3_5_TCPWM1_LINE_COMPL257}, 1573 {4u, 73u, P3_6, P3_6_TCPWM1_LINE_COMPL73}, 1574 {4u, 74u, P3_7, P3_7_TCPWM1_LINE_COMPL74}, 1575 {5u, 0u, P4_0, P4_0_TCPWM1_LINE_COMPL256}, 1576 {4u, 4u, P4_1, P4_1_TCPWM1_LINE_COMPL4}, 1577 {4u, 5u, P4_2, P4_2_TCPWM1_LINE_COMPL5}, 1578 {4u, 6u, P4_3, P4_3_TCPWM1_LINE_COMPL6}, 1579 {4u, 7u, P4_4, P4_4_TCPWM1_LINE_COMPL7}, 1580 {4u, 8u, P5_0, P5_0_TCPWM1_LINE_COMPL8}, 1581 {1u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL256}, 1582 {4u, 9u, P5_1, P5_1_TCPWM1_LINE_COMPL9}, 1583 {6u, 10u, P5_1, P5_1_TCPWM1_LINE_COMPL522}, 1584 {4u, 10u, P5_2, P5_2_TCPWM1_LINE_COMPL10}, 1585 {4u, 11u, P5_3, P5_3_TCPWM1_LINE_COMPL11}, 1586 {4u, 12u, P5_4, P5_4_TCPWM1_LINE_COMPL12}, 1587 {4u, 13u, P5_5, P5_5_TCPWM1_LINE_COMPL13}, 1588 {6u, 11u, P5_5, P5_5_TCPWM1_LINE_COMPL523}, 1589 {4u, 14u, P6_0, P6_0_TCPWM1_LINE_COMPL14}, 1590 {5u, 0u, P6_1, P6_1_TCPWM1_LINE_COMPL256}, 1591 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 1592 {4u, 0u, P6_2, P6_2_TCPWM1_LINE_COMPL0}, 1593 {5u, 1u, P6_3, P6_3_TCPWM1_LINE_COMPL257}, 1594 {6u, 12u, P6_3, P6_3_TCPWM1_LINE_COMPL524}, 1595 {4u, 1u, P6_4, P6_4_TCPWM1_LINE_COMPL1}, 1596 {5u, 2u, P6_5, P6_5_TCPWM1_LINE_COMPL258}, 1597 {4u, 2u, P6_6, P6_6_TCPWM1_LINE_COMPL2}, 1598 {5u, 3u, P6_7, P6_7_TCPWM1_LINE_COMPL259}, 1599 {4u, 3u, P7_0, P7_0_TCPWM1_LINE_COMPL3}, 1600 {5u, 4u, P7_1, P7_1_TCPWM1_LINE_COMPL260}, 1601 {0u, 1u, P7_2, P7_2_TCPWM0_LINE_COMPL1}, 1602 {4u, 15u, P7_2, P7_2_TCPWM1_LINE_COMPL15}, 1603 {5u, 5u, P7_3, P7_3_TCPWM1_LINE_COMPL261}, 1604 {4u, 16u, P7_4, P7_4_TCPWM1_LINE_COMPL16}, 1605 {5u, 6u, P7_5, P7_5_TCPWM1_LINE_COMPL262}, 1606 {4u, 17u, P7_6, P7_6_TCPWM1_LINE_COMPL17}, 1607 {5u, 7u, P7_7, P7_7_TCPWM1_LINE_COMPL263}, 1608 {2u, 2u, P8_0, P8_0_TCPWM0_LINE_COMPL514}, 1609 {4u, 18u, P8_0, P8_0_TCPWM1_LINE_COMPL18}, 1610 {4u, 19u, P8_1, P8_1_TCPWM1_LINE_COMPL19}, 1611 {6u, 8u, P8_1, P8_1_TCPWM1_LINE_COMPL520}, 1612 {4u, 20u, P8_2, P8_2_TCPWM1_LINE_COMPL20}, 1613 {4u, 21u, P8_3, P8_3_TCPWM1_LINE_COMPL21}, 1614 {4u, 22u, P8_4, P8_4_TCPWM1_LINE_COMPL22}, 1615 {4u, 23u, P9_0, P9_0_TCPWM1_LINE_COMPL23}, 1616 {4u, 24u, P9_1, P9_1_TCPWM1_LINE_COMPL24}, 1617 {6u, 9u, P9_1, P9_1_TCPWM1_LINE_COMPL521}, 1618 {4u, 25u, P9_2, P9_2_TCPWM1_LINE_COMPL25}, 1619 {4u, 26u, P9_3, P9_3_TCPWM1_LINE_COMPL26}, 1620 {4u, 27u, P10_0, P10_0_TCPWM1_LINE_COMPL27}, 1621 {4u, 28u, P10_1, P10_1_TCPWM1_LINE_COMPL28}, 1622 {6u, 10u, P10_1, P10_1_TCPWM1_LINE_COMPL522}, 1623 {4u, 29u, P10_2, P10_2_TCPWM1_LINE_COMPL29}, 1624 {4u, 30u, P10_3, P10_3_TCPWM1_LINE_COMPL30}, 1625 {4u, 31u, P10_4, P10_4_TCPWM1_LINE_COMPL31}, 1626 {4u, 32u, P10_5, P10_5_TCPWM1_LINE_COMPL32}, 1627 {6u, 11u, P10_5, P10_5_TCPWM1_LINE_COMPL523}, 1628 {4u, 33u, P10_6, P10_6_TCPWM1_LINE_COMPL33}, 1629 {4u, 34u, P10_7, P10_7_TCPWM1_LINE_COMPL34}, 1630 {4u, 62u, P11_0, P11_0_TCPWM1_LINE_COMPL62}, 1631 {4u, 61u, P11_1, P11_1_TCPWM1_LINE_COMPL61}, 1632 {4u, 60u, P11_2, P11_2_TCPWM1_LINE_COMPL60}, 1633 {4u, 35u, P12_0, P12_0_TCPWM1_LINE_COMPL35}, 1634 {2u, 1u, P12_1, P12_1_TCPWM0_LINE_COMPL513}, 1635 {4u, 36u, P12_1, P12_1_TCPWM1_LINE_COMPL36}, 1636 {4u, 37u, P12_2, P12_2_TCPWM1_LINE_COMPL37}, 1637 {4u, 38u, P12_3, P12_3_TCPWM1_LINE_COMPL38}, 1638 {4u, 39u, P12_4, P12_4_TCPWM1_LINE_COMPL39}, 1639 {4u, 40u, P12_5, P12_5_TCPWM1_LINE_COMPL40}, 1640 {4u, 41u, P12_6, P12_6_TCPWM1_LINE_COMPL41}, 1641 {4u, 42u, P12_7, P12_7_TCPWM1_LINE_COMPL42}, 1642 {4u, 43u, P13_0, P13_0_TCPWM1_LINE_COMPL43}, 1643 {0u, 2u, P13_1, P13_1_TCPWM0_LINE_COMPL2}, 1644 {5u, 8u, P13_1, P13_1_TCPWM1_LINE_COMPL264}, 1645 {4u, 44u, P13_2, P13_2_TCPWM1_LINE_COMPL44}, 1646 {5u, 9u, P13_3, P13_3_TCPWM1_LINE_COMPL265}, 1647 {4u, 45u, P13_4, P13_4_TCPWM1_LINE_COMPL45}, 1648 {5u, 10u, P13_5, P13_5_TCPWM1_LINE_COMPL266}, 1649 {6u, 4u, P13_5, P13_5_TCPWM1_LINE_COMPL516}, 1650 {4u, 46u, P13_6, P13_6_TCPWM1_LINE_COMPL46}, 1651 {5u, 11u, P13_7, P13_7_TCPWM1_LINE_COMPL267}, 1652 {6u, 5u, P13_7, P13_7_TCPWM1_LINE_COMPL517}, 1653 {4u, 47u, P14_0, P14_0_TCPWM1_LINE_COMPL47}, 1654 {1u, 1u, P14_1, P14_1_TCPWM0_LINE_COMPL257}, 1655 {4u, 48u, P14_1, P14_1_TCPWM1_LINE_COMPL48}, 1656 {6u, 6u, P14_1, P14_1_TCPWM1_LINE_COMPL518}, 1657 {4u, 49u, P14_2, P14_2_TCPWM1_LINE_COMPL49}, 1658 {4u, 50u, P14_3, P14_3_TCPWM1_LINE_COMPL50}, 1659 {6u, 7u, P14_3, P14_3_TCPWM1_LINE_COMPL519}, 1660 {4u, 51u, P14_4, P14_4_TCPWM1_LINE_COMPL51}, 1661 {4u, 52u, P14_5, P14_5_TCPWM1_LINE_COMPL52}, 1662 {4u, 53u, P14_6, P14_6_TCPWM1_LINE_COMPL53}, 1663 {4u, 54u, P14_7, P14_7_TCPWM1_LINE_COMPL54}, 1664 {4u, 55u, P15_0, P15_0_TCPWM1_LINE_COMPL55}, 1665 {4u, 56u, P15_1, P15_1_TCPWM1_LINE_COMPL56}, 1666 {4u, 57u, P15_2, P15_2_TCPWM1_LINE_COMPL57}, 1667 {4u, 58u, P15_3, P15_3_TCPWM1_LINE_COMPL58}, 1668 {4u, 59u, P16_0, P16_0_TCPWM1_LINE_COMPL59}, 1669 {4u, 60u, P16_1, P16_1_TCPWM1_LINE_COMPL60}, 1670 {6u, 0u, P16_1, P16_1_TCPWM1_LINE_COMPL512}, 1671 {4u, 61u, P16_2, P16_2_TCPWM1_LINE_COMPL61}, 1672 {4u, 62u, P16_3, P16_3_TCPWM1_LINE_COMPL62}, 1673 {6u, 1u, P16_3, P16_3_TCPWM1_LINE_COMPL513}, 1674 {4u, 69u, P16_4, P16_4_TCPWM1_LINE_COMPL69}, 1675 {4u, 68u, P16_5, P16_5_TCPWM1_LINE_COMPL68}, 1676 {4u, 67u, P16_6, P16_6_TCPWM1_LINE_COMPL67}, 1677 {4u, 66u, P16_7, P16_7_TCPWM1_LINE_COMPL66}, 1678 {4u, 62u, P17_0, P17_0_TCPWM1_LINE_COMPL62}, 1679 {4u, 61u, P17_1, P17_1_TCPWM1_LINE_COMPL61}, 1680 {4u, 60u, P17_2, P17_2_TCPWM1_LINE_COMPL60}, 1681 {4u, 59u, P17_3, P17_3_TCPWM1_LINE_COMPL59}, 1682 {4u, 58u, P17_4, P17_4_TCPWM1_LINE_COMPL58}, 1683 {6u, 3u, P17_4, P17_4_TCPWM1_LINE_COMPL515}, 1684 {4u, 57u, P17_5, P17_5_TCPWM1_LINE_COMPL57}, 1685 {4u, 56u, P17_6, P17_6_TCPWM1_LINE_COMPL56}, 1686 {6u, 2u, P17_6, P17_6_TCPWM1_LINE_COMPL514}, 1687 {5u, 4u, P17_7, P17_7_TCPWM1_LINE_COMPL260}, 1688 {5u, 5u, P18_0, P18_0_TCPWM1_LINE_COMPL261}, 1689 {5u, 6u, P18_1, P18_1_TCPWM1_LINE_COMPL262}, 1690 {6u, 0u, P18_1, P18_1_TCPWM1_LINE_COMPL512}, 1691 {5u, 7u, P18_2, P18_2_TCPWM1_LINE_COMPL263}, 1692 {4u, 55u, P18_3, P18_3_TCPWM1_LINE_COMPL55}, 1693 {6u, 1u, P18_3, P18_3_TCPWM1_LINE_COMPL513}, 1694 {4u, 54u, P18_4, P18_4_TCPWM1_LINE_COMPL54}, 1695 {1u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL258}, 1696 {4u, 53u, P18_5, P18_5_TCPWM1_LINE_COMPL53}, 1697 {6u, 2u, P18_5, P18_5_TCPWM1_LINE_COMPL514}, 1698 {4u, 52u, P18_6, P18_6_TCPWM1_LINE_COMPL52}, 1699 {4u, 51u, P18_7, P18_7_TCPWM1_LINE_COMPL51}, 1700 {6u, 3u, P18_7, P18_7_TCPWM1_LINE_COMPL515}, 1701 {4u, 50u, P19_0, P19_0_TCPWM1_LINE_COMPL50}, 1702 {5u, 3u, P19_1, P19_1_TCPWM1_LINE_COMPL259}, 1703 {4u, 26u, P19_2, P19_2_TCPWM1_LINE_COMPL26}, 1704 {4u, 27u, P19_3, P19_3_TCPWM1_LINE_COMPL27}, 1705 {4u, 28u, P19_4, P19_4_TCPWM1_LINE_COMPL28}, 1706 {4u, 29u, P20_0, P20_0_TCPWM1_LINE_COMPL29}, 1707 {4u, 30u, P20_1, P20_1_TCPWM1_LINE_COMPL30}, 1708 {4u, 49u, P20_2, P20_2_TCPWM1_LINE_COMPL49}, 1709 {4u, 48u, P20_3, P20_3_TCPWM1_LINE_COMPL48}, 1710 {4u, 47u, P20_4, P20_4_TCPWM1_LINE_COMPL47}, 1711 {4u, 46u, P20_5, P20_5_TCPWM1_LINE_COMPL46}, 1712 {4u, 45u, P20_6, P20_6_TCPWM1_LINE_COMPL45}, 1713 {4u, 44u, P20_7, P20_7_TCPWM1_LINE_COMPL44}, 1714 {4u, 43u, P21_0, P21_0_TCPWM1_LINE_COMPL43}, 1715 {4u, 42u, P21_1, P21_1_TCPWM1_LINE_COMPL42}, 1716 {4u, 41u, P21_2, P21_2_TCPWM1_LINE_COMPL41}, 1717 {4u, 40u, P21_3, P21_3_TCPWM1_LINE_COMPL40}, 1718 {4u, 39u, P21_4, P21_4_TCPWM1_LINE_COMPL39}, 1719 {4u, 35u, P21_5, P21_5_TCPWM1_LINE_COMPL35}, 1720 {4u, 38u, P21_5, P21_5_TCPWM1_LINE_COMPL38}, 1721 {4u, 37u, P21_6, P21_6_TCPWM1_LINE_COMPL37}, 1722 {4u, 36u, P21_7, P21_7_TCPWM1_LINE_COMPL36}, 1723 {4u, 34u, P22_1, P22_1_TCPWM1_LINE_COMPL34}, 1724 {4u, 33u, P22_2, P22_2_TCPWM1_LINE_COMPL33}, 1725 {4u, 32u, P22_3, P22_3_TCPWM1_LINE_COMPL32}, 1726 {4u, 31u, P22_4, P22_4_TCPWM1_LINE_COMPL31}, 1727 {4u, 30u, P22_5, P22_5_TCPWM1_LINE_COMPL30}, 1728 {4u, 29u, P22_6, P22_6_TCPWM1_LINE_COMPL29}, 1729 {6u, 8u, P22_6, P22_6_TCPWM1_LINE_COMPL520}, 1730 {4u, 28u, P22_7, P22_7_TCPWM1_LINE_COMPL28}, 1731 {4u, 27u, P23_0, P23_0_TCPWM1_LINE_COMPL27}, 1732 {5u, 8u, P23_1, P23_1_TCPWM1_LINE_COMPL264}, 1733 {5u, 9u, P23_2, P23_2_TCPWM1_LINE_COMPL265}, 1734 {5u, 10u, P23_3, P23_3_TCPWM1_LINE_COMPL266}, 1735 {5u, 11u, P23_4, P23_4_TCPWM1_LINE_COMPL267}, 1736 {4u, 25u, P23_5, P23_5_TCPWM1_LINE_COMPL25}, 1737 {6u, 9u, P23_5, P23_5_TCPWM1_LINE_COMPL521}, 1738 {4u, 24u, P23_6, P23_6_TCPWM1_LINE_COMPL24}, 1739 {4u, 23u, P23_7, P23_7_TCPWM1_LINE_COMPL23}, 1740 {4u, 65u, P28_0, P28_0_TCPWM1_LINE_COMPL65}, 1741 {4u, 63u, P28_1, P28_1_TCPWM1_LINE_COMPL63}, 1742 {6u, 12u, P28_1, P28_1_TCPWM1_LINE_COMPL524}, 1743 {4u, 64u, P28_2, P28_2_TCPWM1_LINE_COMPL64}, 1744 {4u, 65u, P28_3, P28_3_TCPWM1_LINE_COMPL65}, 1745 {4u, 66u, P28_4, P28_4_TCPWM1_LINE_COMPL66}, 1746 {4u, 67u, P28_5, P28_5_TCPWM1_LINE_COMPL67}, 1747 {4u, 68u, P28_6, P28_6_TCPWM1_LINE_COMPL68}, 1748 {4u, 69u, P28_7, P28_7_TCPWM1_LINE_COMPL69}, 1749 {4u, 75u, P29_0, P29_0_TCPWM1_LINE_COMPL75}, 1750 {4u, 76u, P29_1, P29_1_TCPWM1_LINE_COMPL76}, 1751 {4u, 77u, P29_2, P29_2_TCPWM1_LINE_COMPL77}, 1752 {4u, 78u, P29_3, P29_3_TCPWM1_LINE_COMPL78}, 1753 {4u, 79u, P29_4, P29_4_TCPWM1_LINE_COMPL79}, 1754 {4u, 80u, P29_5, P29_5_TCPWM1_LINE_COMPL80}, 1755 {4u, 81u, P29_6, P29_6_TCPWM1_LINE_COMPL81}, 1756 {4u, 82u, P29_7, P29_7_TCPWM1_LINE_COMPL82}, 1757 {4u, 83u, P30_0, P30_0_TCPWM1_LINE_COMPL83}, 1758 {4u, 83u, P30_1, P30_1_TCPWM1_LINE_COMPL83}, 1759 {4u, 82u, P30_2, P30_2_TCPWM1_LINE_COMPL82}, 1760 {4u, 81u, P30_3, P30_3_TCPWM1_LINE_COMPL81}, 1761 {4u, 80u, P31_0, P31_0_TCPWM1_LINE_COMPL80}, 1762 {4u, 79u, P31_1, P31_1_TCPWM1_LINE_COMPL79}, 1763 {4u, 78u, P31_2, P31_2_TCPWM1_LINE_COMPL78}, 1764 {4u, 77u, P32_0, P32_0_TCPWM1_LINE_COMPL77}, 1765 {4u, 76u, P32_1, P32_1_TCPWM1_LINE_COMPL76}, 1766 {4u, 75u, P32_2, P32_2_TCPWM1_LINE_COMPL75}, 1767 {4u, 74u, P32_3, P32_3_TCPWM1_LINE_COMPL74}, 1768 {4u, 73u, P32_4, P32_4_TCPWM1_LINE_COMPL73}, 1769 {4u, 72u, P32_5, P32_5_TCPWM1_LINE_COMPL72}, 1770 {4u, 71u, P32_6, P32_6_TCPWM1_LINE_COMPL71}, 1771 {4u, 70u, P32_7, P32_7_TCPWM1_LINE_COMPL70}, 1772 }; 1773 1774 /* Connections for: tcpwm_tr_one_cnt_in */ 1775 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[446] = { 1776 {4u, 54u, P0_0, P0_0_TCPWM1_TR_ONE_CNT_IN54}, 1777 {4u, 67u, P0_0, P0_0_TCPWM1_TR_ONE_CNT_IN67}, 1778 {4u, 51u, P0_1, P0_1_TCPWM1_TR_ONE_CNT_IN51}, 1779 {4u, 55u, P0_1, P0_1_TCPWM1_TR_ONE_CNT_IN55}, 1780 {4u, 42u, P0_2, P0_2_TCPWM1_TR_ONE_CNT_IN42}, 1781 {4u, 52u, P0_2, P0_2_TCPWM1_TR_ONE_CNT_IN52}, 1782 {6u, 0u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN1536}, 1783 {4u, 39u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN39}, 1784 {4u, 43u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN43}, 1785 {6u, 1u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN1537}, 1786 {4u, 36u, P1_0, P1_0_TCPWM1_TR_ONE_CNT_IN36}, 1787 {4u, 40u, P1_0, P1_0_TCPWM1_TR_ONE_CNT_IN40}, 1788 {4u, 33u, P1_1, P1_1_TCPWM1_TR_ONE_CNT_IN33}, 1789 {4u, 37u, P1_1, P1_1_TCPWM1_TR_ONE_CNT_IN37}, 1790 {4u, 30u, P1_2, P1_2_TCPWM1_TR_ONE_CNT_IN30}, 1791 {4u, 34u, P1_2, P1_2_TCPWM1_TR_ONE_CNT_IN34}, 1792 {4u, 24u, P1_3, P1_3_TCPWM1_TR_ONE_CNT_IN24}, 1793 {4u, 31u, P1_3, P1_3_TCPWM1_TR_ONE_CNT_IN31}, 1794 {4u, 211u, P1_4, P1_4_TCPWM1_TR_ONE_CNT_IN211}, 1795 {4u, 213u, P1_4, P1_4_TCPWM1_TR_ONE_CNT_IN213}, 1796 {4u, 21u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN21}, 1797 {4u, 25u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN25}, 1798 {10u, 12u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN1548}, 1799 {4u, 18u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN18}, 1800 {4u, 22u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN22}, 1801 {10u, 15u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN1551}, 1802 {4u, 15u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN15}, 1803 {4u, 19u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN19}, 1804 {10u, 18u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN1554}, 1805 {4u, 12u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN12}, 1806 {4u, 16u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN16}, 1807 {10u, 21u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN1557}, 1808 {4u, 9u, P2_4, P2_4_TCPWM1_TR_ONE_CNT_IN9}, 1809 {4u, 13u, P2_4, P2_4_TCPWM1_TR_ONE_CNT_IN13}, 1810 {4u, 6u, P2_5, P2_5_TCPWM1_TR_ONE_CNT_IN6}, 1811 {4u, 10u, P2_5, P2_5_TCPWM1_TR_ONE_CNT_IN10}, 1812 {4u, 214u, P2_6, P2_6_TCPWM1_TR_ONE_CNT_IN214}, 1813 {4u, 216u, P2_6, P2_6_TCPWM1_TR_ONE_CNT_IN216}, 1814 {4u, 217u, P2_7, P2_7_TCPWM1_TR_ONE_CNT_IN217}, 1815 {4u, 219u, P2_7, P2_7_TCPWM1_TR_ONE_CNT_IN219}, 1816 {4u, 3u, P3_0, P3_0_TCPWM1_TR_ONE_CNT_IN3}, 1817 {4u, 7u, P3_0, P3_0_TCPWM1_TR_ONE_CNT_IN7}, 1818 {4u, 0u, P3_1, P3_1_TCPWM1_TR_ONE_CNT_IN0}, 1819 {4u, 4u, P3_1, P3_1_TCPWM1_TR_ONE_CNT_IN4}, 1820 {4u, 1u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN1}, 1821 {7u, 9u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN777}, 1822 {10u, 13u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN1549}, 1823 {7u, 6u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN774}, 1824 {7u, 10u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN778}, 1825 {10u, 16u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN1552}, 1826 {7u, 3u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN771}, 1827 {7u, 7u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN775}, 1828 {10u, 19u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN1555}, 1829 {7u, 0u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN768}, 1830 {7u, 4u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN772}, 1831 {10u, 22u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN1558}, 1832 {4u, 220u, P3_6, P3_6_TCPWM1_TR_ONE_CNT_IN220}, 1833 {4u, 222u, P3_6, P3_6_TCPWM1_TR_ONE_CNT_IN222}, 1834 {4u, 223u, P3_7, P3_7_TCPWM1_TR_ONE_CNT_IN223}, 1835 {4u, 225u, P3_7, P3_7_TCPWM1_TR_ONE_CNT_IN225}, 1836 {4u, 12u, P4_0, P4_0_TCPWM1_TR_ONE_CNT_IN12}, 1837 {7u, 1u, P4_0, P4_0_TCPWM1_TR_ONE_CNT_IN769}, 1838 {4u, 13u, P4_1, P4_1_TCPWM1_TR_ONE_CNT_IN13}, 1839 {4u, 15u, P4_1, P4_1_TCPWM1_TR_ONE_CNT_IN15}, 1840 {4u, 16u, P4_2, P4_2_TCPWM1_TR_ONE_CNT_IN16}, 1841 {4u, 18u, P4_2, P4_2_TCPWM1_TR_ONE_CNT_IN18}, 1842 {4u, 19u, P4_3, P4_3_TCPWM1_TR_ONE_CNT_IN19}, 1843 {4u, 21u, P4_3, P4_3_TCPWM1_TR_ONE_CNT_IN21}, 1844 {4u, 22u, P4_4, P4_4_TCPWM1_TR_ONE_CNT_IN22}, 1845 {4u, 24u, P4_4, P4_4_TCPWM1_TR_ONE_CNT_IN24}, 1846 {4u, 25u, P5_0, P5_0_TCPWM1_TR_ONE_CNT_IN25}, 1847 {4u, 27u, P5_0, P5_0_TCPWM1_TR_ONE_CNT_IN27}, 1848 {4u, 28u, P5_1, P5_1_TCPWM1_TR_ONE_CNT_IN28}, 1849 {4u, 30u, P5_1, P5_1_TCPWM1_TR_ONE_CNT_IN30}, 1850 {3u, 0u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN768}, 1851 {4u, 31u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN31}, 1852 {4u, 33u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN33}, 1853 {10u, 30u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN1566}, 1854 {3u, 1u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN769}, 1855 {4u, 34u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN34}, 1856 {4u, 36u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN36}, 1857 {10u, 31u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN1567}, 1858 {4u, 37u, P5_4, P5_4_TCPWM1_TR_ONE_CNT_IN37}, 1859 {4u, 39u, P5_4, P5_4_TCPWM1_TR_ONE_CNT_IN39}, 1860 {4u, 40u, P5_5, P5_5_TCPWM1_TR_ONE_CNT_IN40}, 1861 {4u, 42u, P5_5, P5_5_TCPWM1_TR_ONE_CNT_IN42}, 1862 {4u, 43u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN43}, 1863 {7u, 0u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN768}, 1864 {10u, 33u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN1569}, 1865 {4u, 0u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN0}, 1866 {7u, 1u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN769}, 1867 {10u, 34u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN1570}, 1868 {4u, 1u, P6_2, P6_2_TCPWM1_TR_ONE_CNT_IN1}, 1869 {7u, 3u, P6_2, P6_2_TCPWM1_TR_ONE_CNT_IN771}, 1870 {4u, 3u, P6_3, P6_3_TCPWM1_TR_ONE_CNT_IN3}, 1871 {7u, 4u, P6_3, P6_3_TCPWM1_TR_ONE_CNT_IN772}, 1872 {0u, 0u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN0}, 1873 {4u, 4u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN4}, 1874 {7u, 6u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN774}, 1875 {10u, 36u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN1572}, 1876 {0u, 1u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN1}, 1877 {4u, 6u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN6}, 1878 {7u, 7u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN775}, 1879 {10u, 37u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN1573}, 1880 {4u, 7u, P6_6, P6_6_TCPWM1_TR_ONE_CNT_IN7}, 1881 {7u, 9u, P6_6, P6_6_TCPWM1_TR_ONE_CNT_IN777}, 1882 {4u, 9u, P6_7, P6_7_TCPWM1_TR_ONE_CNT_IN9}, 1883 {7u, 10u, P6_7, P6_7_TCPWM1_TR_ONE_CNT_IN778}, 1884 {4u, 10u, P7_0, P7_0_TCPWM1_TR_ONE_CNT_IN10}, 1885 {7u, 12u, P7_0, P7_0_TCPWM1_TR_ONE_CNT_IN780}, 1886 {4u, 45u, P7_1, P7_1_TCPWM1_TR_ONE_CNT_IN45}, 1887 {7u, 13u, P7_1, P7_1_TCPWM1_TR_ONE_CNT_IN781}, 1888 {4u, 46u, P7_2, P7_2_TCPWM1_TR_ONE_CNT_IN46}, 1889 {7u, 15u, P7_2, P7_2_TCPWM1_TR_ONE_CNT_IN783}, 1890 {0u, 3u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN3}, 1891 {4u, 48u, P7_3, P7_3_TCPWM1_TR_ONE_CNT_IN48}, 1892 {7u, 16u, P7_3, P7_3_TCPWM1_TR_ONE_CNT_IN784}, 1893 {0u, 4u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN4}, 1894 {4u, 49u, P7_4, P7_4_TCPWM1_TR_ONE_CNT_IN49}, 1895 {7u, 18u, P7_4, P7_4_TCPWM1_TR_ONE_CNT_IN786}, 1896 {4u, 51u, P7_5, P7_5_TCPWM1_TR_ONE_CNT_IN51}, 1897 {7u, 19u, P7_5, P7_5_TCPWM1_TR_ONE_CNT_IN787}, 1898 {4u, 52u, P7_6, P7_6_TCPWM1_TR_ONE_CNT_IN52}, 1899 {7u, 21u, P7_6, P7_6_TCPWM1_TR_ONE_CNT_IN789}, 1900 {4u, 54u, P7_7, P7_7_TCPWM1_TR_ONE_CNT_IN54}, 1901 {7u, 22u, P7_7, P7_7_TCPWM1_TR_ONE_CNT_IN790}, 1902 {4u, 55u, P8_0, P8_0_TCPWM1_TR_ONE_CNT_IN55}, 1903 {4u, 57u, P8_0, P8_0_TCPWM1_TR_ONE_CNT_IN57}, 1904 {4u, 58u, P8_1, P8_1_TCPWM1_TR_ONE_CNT_IN58}, 1905 {4u, 60u, P8_1, P8_1_TCPWM1_TR_ONE_CNT_IN60}, 1906 {6u, 6u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN1542}, 1907 {4u, 61u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN61}, 1908 {4u, 63u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN63}, 1909 {6u, 7u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN1543}, 1910 {10u, 24u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN1560}, 1911 {4u, 64u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN64}, 1912 {4u, 66u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN66}, 1913 {10u, 25u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN1561}, 1914 {4u, 67u, P8_4, P8_4_TCPWM1_TR_ONE_CNT_IN67}, 1915 {4u, 69u, P8_4, P8_4_TCPWM1_TR_ONE_CNT_IN69}, 1916 {4u, 70u, P9_0, P9_0_TCPWM1_TR_ONE_CNT_IN70}, 1917 {4u, 72u, P9_0, P9_0_TCPWM1_TR_ONE_CNT_IN72}, 1918 {4u, 73u, P9_1, P9_1_TCPWM1_TR_ONE_CNT_IN73}, 1919 {4u, 75u, P9_1, P9_1_TCPWM1_TR_ONE_CNT_IN75}, 1920 {4u, 76u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN76}, 1921 {4u, 78u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN78}, 1922 {10u, 27u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN1563}, 1923 {4u, 79u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN79}, 1924 {4u, 81u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN81}, 1925 {10u, 28u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN1564}, 1926 {4u, 82u, P10_0, P10_0_TCPWM1_TR_ONE_CNT_IN82}, 1927 {4u, 84u, P10_0, P10_0_TCPWM1_TR_ONE_CNT_IN84}, 1928 {4u, 85u, P10_1, P10_1_TCPWM1_TR_ONE_CNT_IN85}, 1929 {4u, 87u, P10_1, P10_1_TCPWM1_TR_ONE_CNT_IN87}, 1930 {4u, 88u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN88}, 1931 {4u, 90u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN90}, 1932 {10u, 30u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN1566}, 1933 {4u, 91u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN91}, 1934 {4u, 93u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN93}, 1935 {10u, 31u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN1567}, 1936 {4u, 94u, P10_4, P10_4_TCPWM1_TR_ONE_CNT_IN94}, 1937 {4u, 96u, P10_4, P10_4_TCPWM1_TR_ONE_CNT_IN96}, 1938 {4u, 97u, P10_5, P10_5_TCPWM1_TR_ONE_CNT_IN97}, 1939 {4u, 99u, P10_5, P10_5_TCPWM1_TR_ONE_CNT_IN99}, 1940 {4u, 100u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN100}, 1941 {4u, 102u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN102}, 1942 {10u, 33u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN1569}, 1943 {4u, 103u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN103}, 1944 {4u, 105u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN105}, 1945 {10u, 34u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN1570}, 1946 {4u, 183u, P11_0, P11_0_TCPWM1_TR_ONE_CNT_IN183}, 1947 {4u, 187u, P11_0, P11_0_TCPWM1_TR_ONE_CNT_IN187}, 1948 {4u, 180u, P11_1, P11_1_TCPWM1_TR_ONE_CNT_IN180}, 1949 {4u, 184u, P11_1, P11_1_TCPWM1_TR_ONE_CNT_IN184}, 1950 {4u, 177u, P11_2, P11_2_TCPWM1_TR_ONE_CNT_IN177}, 1951 {4u, 181u, P11_2, P11_2_TCPWM1_TR_ONE_CNT_IN181}, 1952 {4u, 106u, P12_0, P12_0_TCPWM1_TR_ONE_CNT_IN106}, 1953 {4u, 108u, P12_0, P12_0_TCPWM1_TR_ONE_CNT_IN108}, 1954 {4u, 109u, P12_1, P12_1_TCPWM1_TR_ONE_CNT_IN109}, 1955 {4u, 111u, P12_1, P12_1_TCPWM1_TR_ONE_CNT_IN111}, 1956 {4u, 112u, P12_2, P12_2_TCPWM1_TR_ONE_CNT_IN112}, 1957 {4u, 114u, P12_2, P12_2_TCPWM1_TR_ONE_CNT_IN114}, 1958 {6u, 3u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN1539}, 1959 {4u, 115u, P12_3, P12_3_TCPWM1_TR_ONE_CNT_IN115}, 1960 {4u, 117u, P12_3, P12_3_TCPWM1_TR_ONE_CNT_IN117}, 1961 {6u, 4u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN1540}, 1962 {0u, 7u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN7}, 1963 {4u, 118u, P12_4, P12_4_TCPWM1_TR_ONE_CNT_IN118}, 1964 {4u, 120u, P12_4, P12_4_TCPWM1_TR_ONE_CNT_IN120}, 1965 {4u, 121u, P12_5, P12_5_TCPWM1_TR_ONE_CNT_IN121}, 1966 {4u, 123u, P12_5, P12_5_TCPWM1_TR_ONE_CNT_IN123}, 1967 {4u, 124u, P12_6, P12_6_TCPWM1_TR_ONE_CNT_IN124}, 1968 {4u, 126u, P12_6, P12_6_TCPWM1_TR_ONE_CNT_IN126}, 1969 {4u, 127u, P12_7, P12_7_TCPWM1_TR_ONE_CNT_IN127}, 1970 {4u, 129u, P12_7, P12_7_TCPWM1_TR_ONE_CNT_IN129}, 1971 {0u, 6u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN6}, 1972 {4u, 130u, P13_0, P13_0_TCPWM1_TR_ONE_CNT_IN130}, 1973 {7u, 24u, P13_0, P13_0_TCPWM1_TR_ONE_CNT_IN792}, 1974 {4u, 132u, P13_1, P13_1_TCPWM1_TR_ONE_CNT_IN132}, 1975 {7u, 25u, P13_1, P13_1_TCPWM1_TR_ONE_CNT_IN793}, 1976 {4u, 133u, P13_2, P13_2_TCPWM1_TR_ONE_CNT_IN133}, 1977 {7u, 27u, P13_2, P13_2_TCPWM1_TR_ONE_CNT_IN795}, 1978 {4u, 135u, P13_3, P13_3_TCPWM1_TR_ONE_CNT_IN135}, 1979 {7u, 28u, P13_3, P13_3_TCPWM1_TR_ONE_CNT_IN796}, 1980 {4u, 136u, P13_4, P13_4_TCPWM1_TR_ONE_CNT_IN136}, 1981 {7u, 30u, P13_4, P13_4_TCPWM1_TR_ONE_CNT_IN798}, 1982 {4u, 138u, P13_5, P13_5_TCPWM1_TR_ONE_CNT_IN138}, 1983 {7u, 31u, P13_5, P13_5_TCPWM1_TR_ONE_CNT_IN799}, 1984 {4u, 139u, P13_6, P13_6_TCPWM1_TR_ONE_CNT_IN139}, 1985 {7u, 33u, P13_6, P13_6_TCPWM1_TR_ONE_CNT_IN801}, 1986 {4u, 141u, P13_7, P13_7_TCPWM1_TR_ONE_CNT_IN141}, 1987 {7u, 34u, P13_7, P13_7_TCPWM1_TR_ONE_CNT_IN802}, 1988 {4u, 142u, P14_0, P14_0_TCPWM1_TR_ONE_CNT_IN142}, 1989 {4u, 144u, P14_0, P14_0_TCPWM1_TR_ONE_CNT_IN144}, 1990 {4u, 145u, P14_1, P14_1_TCPWM1_TR_ONE_CNT_IN145}, 1991 {4u, 147u, P14_1, P14_1_TCPWM1_TR_ONE_CNT_IN147}, 1992 {3u, 3u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN771}, 1993 {4u, 148u, P14_2, P14_2_TCPWM1_TR_ONE_CNT_IN148}, 1994 {4u, 150u, P14_2, P14_2_TCPWM1_TR_ONE_CNT_IN150}, 1995 {3u, 4u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN772}, 1996 {4u, 151u, P14_3, P14_3_TCPWM1_TR_ONE_CNT_IN151}, 1997 {4u, 153u, P14_3, P14_3_TCPWM1_TR_ONE_CNT_IN153}, 1998 {4u, 154u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN154}, 1999 {4u, 156u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN156}, 2000 {10u, 12u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN1548}, 2001 {4u, 157u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN157}, 2002 {4u, 159u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN159}, 2003 {10u, 13u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN1549}, 2004 {4u, 160u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN160}, 2005 {4u, 162u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN162}, 2006 {10u, 15u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN1551}, 2007 {4u, 163u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN163}, 2008 {4u, 165u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN165}, 2009 {10u, 16u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN1552}, 2010 {4u, 166u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN166}, 2011 {4u, 168u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN168}, 2012 {10u, 18u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN1554}, 2013 {4u, 169u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN169}, 2014 {4u, 171u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN171}, 2015 {10u, 19u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN1555}, 2016 {4u, 172u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN172}, 2017 {4u, 174u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN174}, 2018 {10u, 21u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN1557}, 2019 {4u, 175u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN175}, 2020 {4u, 177u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN177}, 2021 {10u, 22u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN1558}, 2022 {4u, 178u, P16_0, P16_0_TCPWM1_TR_ONE_CNT_IN178}, 2023 {4u, 180u, P16_0, P16_0_TCPWM1_TR_ONE_CNT_IN180}, 2024 {4u, 181u, P16_1, P16_1_TCPWM1_TR_ONE_CNT_IN181}, 2025 {4u, 183u, P16_1, P16_1_TCPWM1_TR_ONE_CNT_IN183}, 2026 {4u, 184u, P16_2, P16_2_TCPWM1_TR_ONE_CNT_IN184}, 2027 {4u, 186u, P16_2, P16_2_TCPWM1_TR_ONE_CNT_IN186}, 2028 {4u, 186u, P16_3, P16_3_TCPWM1_TR_ONE_CNT_IN186}, 2029 {4u, 187u, P16_3, P16_3_TCPWM1_TR_ONE_CNT_IN187}, 2030 {4u, 204u, P16_4, P16_4_TCPWM1_TR_ONE_CNT_IN204}, 2031 {4u, 208u, P16_4, P16_4_TCPWM1_TR_ONE_CNT_IN208}, 2032 {4u, 201u, P16_5, P16_5_TCPWM1_TR_ONE_CNT_IN201}, 2033 {4u, 205u, P16_5, P16_5_TCPWM1_TR_ONE_CNT_IN205}, 2034 {4u, 198u, P16_6, P16_6_TCPWM1_TR_ONE_CNT_IN198}, 2035 {4u, 202u, P16_6, P16_6_TCPWM1_TR_ONE_CNT_IN202}, 2036 {4u, 195u, P16_7, P16_7_TCPWM1_TR_ONE_CNT_IN195}, 2037 {4u, 199u, P16_7, P16_7_TCPWM1_TR_ONE_CNT_IN199}, 2038 {4u, 183u, P17_0, P17_0_TCPWM1_TR_ONE_CNT_IN183}, 2039 {4u, 187u, P17_0, P17_0_TCPWM1_TR_ONE_CNT_IN187}, 2040 {4u, 180u, P17_1, P17_1_TCPWM1_TR_ONE_CNT_IN180}, 2041 {4u, 184u, P17_1, P17_1_TCPWM1_TR_ONE_CNT_IN184}, 2042 {4u, 177u, P17_2, P17_2_TCPWM1_TR_ONE_CNT_IN177}, 2043 {4u, 181u, P17_2, P17_2_TCPWM1_TR_ONE_CNT_IN181}, 2044 {4u, 174u, P17_3, P17_3_TCPWM1_TR_ONE_CNT_IN174}, 2045 {4u, 178u, P17_3, P17_3_TCPWM1_TR_ONE_CNT_IN178}, 2046 {4u, 171u, P17_4, P17_4_TCPWM1_TR_ONE_CNT_IN171}, 2047 {4u, 175u, P17_4, P17_4_TCPWM1_TR_ONE_CNT_IN175}, 2048 {4u, 168u, P17_5, P17_5_TCPWM1_TR_ONE_CNT_IN168}, 2049 {4u, 172u, P17_5, P17_5_TCPWM1_TR_ONE_CNT_IN172}, 2050 {4u, 169u, P17_6, P17_6_TCPWM1_TR_ONE_CNT_IN169}, 2051 {7u, 12u, P17_6, P17_6_TCPWM1_TR_ONE_CNT_IN780}, 2052 {7u, 13u, P17_7, P17_7_TCPWM1_TR_ONE_CNT_IN781}, 2053 {7u, 15u, P17_7, P17_7_TCPWM1_TR_ONE_CNT_IN783}, 2054 {7u, 16u, P18_0, P18_0_TCPWM1_TR_ONE_CNT_IN784}, 2055 {7u, 18u, P18_0, P18_0_TCPWM1_TR_ONE_CNT_IN786}, 2056 {7u, 19u, P18_1, P18_1_TCPWM1_TR_ONE_CNT_IN787}, 2057 {7u, 21u, P18_1, P18_1_TCPWM1_TR_ONE_CNT_IN789}, 2058 {4u, 165u, P18_2, P18_2_TCPWM1_TR_ONE_CNT_IN165}, 2059 {7u, 22u, P18_2, P18_2_TCPWM1_TR_ONE_CNT_IN790}, 2060 {4u, 162u, P18_3, P18_3_TCPWM1_TR_ONE_CNT_IN162}, 2061 {4u, 166u, P18_3, P18_3_TCPWM1_TR_ONE_CNT_IN166}, 2062 {4u, 159u, P18_4, P18_4_TCPWM1_TR_ONE_CNT_IN159}, 2063 {4u, 163u, P18_4, P18_4_TCPWM1_TR_ONE_CNT_IN163}, 2064 {4u, 156u, P18_5, P18_5_TCPWM1_TR_ONE_CNT_IN156}, 2065 {4u, 160u, P18_5, P18_5_TCPWM1_TR_ONE_CNT_IN160}, 2066 {3u, 6u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN774}, 2067 {4u, 153u, P18_6, P18_6_TCPWM1_TR_ONE_CNT_IN153}, 2068 {4u, 157u, P18_6, P18_6_TCPWM1_TR_ONE_CNT_IN157}, 2069 {3u, 7u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN775}, 2070 {4u, 150u, P18_7, P18_7_TCPWM1_TR_ONE_CNT_IN150}, 2071 {4u, 154u, P18_7, P18_7_TCPWM1_TR_ONE_CNT_IN154}, 2072 {4u, 151u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN151}, 2073 {7u, 9u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN777}, 2074 {10u, 0u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN1536}, 2075 {4u, 78u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN78}, 2076 {7u, 10u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN778}, 2077 {10u, 1u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN1537}, 2078 {4u, 79u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN79}, 2079 {4u, 81u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN81}, 2080 {10u, 3u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN1539}, 2081 {4u, 82u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN82}, 2082 {4u, 84u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN84}, 2083 {10u, 4u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN1540}, 2084 {4u, 85u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN85}, 2085 {4u, 87u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN87}, 2086 {10u, 6u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN1542}, 2087 {4u, 88u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN88}, 2088 {4u, 90u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN90}, 2089 {10u, 7u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN1543}, 2090 {4u, 91u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN91}, 2091 {4u, 147u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN147}, 2092 {10u, 9u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN1545}, 2093 {4u, 144u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN144}, 2094 {4u, 148u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN148}, 2095 {10u, 10u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN1546}, 2096 {4u, 141u, P20_3, P20_3_TCPWM1_TR_ONE_CNT_IN141}, 2097 {4u, 145u, P20_3, P20_3_TCPWM1_TR_ONE_CNT_IN145}, 2098 {4u, 138u, P20_4, P20_4_TCPWM1_TR_ONE_CNT_IN138}, 2099 {4u, 142u, P20_4, P20_4_TCPWM1_TR_ONE_CNT_IN142}, 2100 {4u, 135u, P20_5, P20_5_TCPWM1_TR_ONE_CNT_IN135}, 2101 {4u, 139u, P20_5, P20_5_TCPWM1_TR_ONE_CNT_IN139}, 2102 {4u, 132u, P20_6, P20_6_TCPWM1_TR_ONE_CNT_IN132}, 2103 {4u, 136u, P20_6, P20_6_TCPWM1_TR_ONE_CNT_IN136}, 2104 {4u, 129u, P20_7, P20_7_TCPWM1_TR_ONE_CNT_IN129}, 2105 {4u, 133u, P20_7, P20_7_TCPWM1_TR_ONE_CNT_IN133}, 2106 {4u, 126u, P21_0, P21_0_TCPWM1_TR_ONE_CNT_IN126}, 2107 {4u, 130u, P21_0, P21_0_TCPWM1_TR_ONE_CNT_IN130}, 2108 {4u, 123u, P21_1, P21_1_TCPWM1_TR_ONE_CNT_IN123}, 2109 {4u, 127u, P21_1, P21_1_TCPWM1_TR_ONE_CNT_IN127}, 2110 {4u, 120u, P21_2, P21_2_TCPWM1_TR_ONE_CNT_IN120}, 2111 {4u, 124u, P21_2, P21_2_TCPWM1_TR_ONE_CNT_IN124}, 2112 {4u, 117u, P21_3, P21_3_TCPWM1_TR_ONE_CNT_IN117}, 2113 {4u, 121u, P21_3, P21_3_TCPWM1_TR_ONE_CNT_IN121}, 2114 {4u, 114u, P21_4, P21_4_TCPWM1_TR_ONE_CNT_IN114}, 2115 {4u, 118u, P21_4, P21_4_TCPWM1_TR_ONE_CNT_IN118}, 2116 {4u, 102u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN102}, 2117 {4u, 106u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN106}, 2118 {4u, 111u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN111}, 2119 {4u, 115u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN115}, 2120 {4u, 108u, P21_6, P21_6_TCPWM1_TR_ONE_CNT_IN108}, 2121 {4u, 112u, P21_6, P21_6_TCPWM1_TR_ONE_CNT_IN112}, 2122 {4u, 105u, P21_7, P21_7_TCPWM1_TR_ONE_CNT_IN105}, 2123 {4u, 109u, P21_7, P21_7_TCPWM1_TR_ONE_CNT_IN109}, 2124 {4u, 99u, P22_1, P22_1_TCPWM1_TR_ONE_CNT_IN99}, 2125 {4u, 103u, P22_1, P22_1_TCPWM1_TR_ONE_CNT_IN103}, 2126 {4u, 96u, P22_2, P22_2_TCPWM1_TR_ONE_CNT_IN96}, 2127 {4u, 100u, P22_2, P22_2_TCPWM1_TR_ONE_CNT_IN100}, 2128 {4u, 93u, P22_3, P22_3_TCPWM1_TR_ONE_CNT_IN93}, 2129 {4u, 97u, P22_3, P22_3_TCPWM1_TR_ONE_CNT_IN97}, 2130 {4u, 90u, P22_4, P22_4_TCPWM1_TR_ONE_CNT_IN90}, 2131 {4u, 94u, P22_4, P22_4_TCPWM1_TR_ONE_CNT_IN94}, 2132 {4u, 87u, P22_5, P22_5_TCPWM1_TR_ONE_CNT_IN87}, 2133 {4u, 91u, P22_5, P22_5_TCPWM1_TR_ONE_CNT_IN91}, 2134 {4u, 84u, P22_6, P22_6_TCPWM1_TR_ONE_CNT_IN84}, 2135 {4u, 88u, P22_6, P22_6_TCPWM1_TR_ONE_CNT_IN88}, 2136 {4u, 81u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN81}, 2137 {4u, 85u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN85}, 2138 {10u, 24u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN1560}, 2139 {4u, 82u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN82}, 2140 {7u, 24u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN792}, 2141 {10u, 25u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN1561}, 2142 {7u, 25u, P23_1, P23_1_TCPWM1_TR_ONE_CNT_IN793}, 2143 {7u, 27u, P23_1, P23_1_TCPWM1_TR_ONE_CNT_IN795}, 2144 {7u, 28u, P23_2, P23_2_TCPWM1_TR_ONE_CNT_IN796}, 2145 {7u, 30u, P23_2, P23_2_TCPWM1_TR_ONE_CNT_IN798}, 2146 {7u, 31u, P23_3, P23_3_TCPWM1_TR_ONE_CNT_IN799}, 2147 {7u, 33u, P23_3, P23_3_TCPWM1_TR_ONE_CNT_IN801}, 2148 {4u, 75u, P23_4, P23_4_TCPWM1_TR_ONE_CNT_IN75}, 2149 {7u, 34u, P23_4, P23_4_TCPWM1_TR_ONE_CNT_IN802}, 2150 {4u, 72u, P23_5, P23_5_TCPWM1_TR_ONE_CNT_IN72}, 2151 {4u, 76u, P23_5, P23_5_TCPWM1_TR_ONE_CNT_IN76}, 2152 {4u, 69u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN69}, 2153 {4u, 73u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN73}, 2154 {10u, 27u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN1563}, 2155 {4u, 66u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN66}, 2156 {4u, 70u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN70}, 2157 {10u, 28u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN1564}, 2158 {4u, 189u, P28_0, P28_0_TCPWM1_TR_ONE_CNT_IN189}, 2159 {4u, 196u, P28_0, P28_0_TCPWM1_TR_ONE_CNT_IN196}, 2160 {4u, 190u, P28_1, P28_1_TCPWM1_TR_ONE_CNT_IN190}, 2161 {4u, 192u, P28_1, P28_1_TCPWM1_TR_ONE_CNT_IN192}, 2162 {4u, 193u, P28_2, P28_2_TCPWM1_TR_ONE_CNT_IN193}, 2163 {4u, 195u, P28_2, P28_2_TCPWM1_TR_ONE_CNT_IN195}, 2164 {10u, 36u, P28_2, P28_2_TCPWM1_TR_ONE_CNT_IN1572}, 2165 {4u, 196u, P28_3, P28_3_TCPWM1_TR_ONE_CNT_IN196}, 2166 {4u, 198u, P28_3, P28_3_TCPWM1_TR_ONE_CNT_IN198}, 2167 {10u, 37u, P28_3, P28_3_TCPWM1_TR_ONE_CNT_IN1573}, 2168 {4u, 199u, P28_4, P28_4_TCPWM1_TR_ONE_CNT_IN199}, 2169 {4u, 201u, P28_4, P28_4_TCPWM1_TR_ONE_CNT_IN201}, 2170 {4u, 202u, P28_5, P28_5_TCPWM1_TR_ONE_CNT_IN202}, 2171 {4u, 204u, P28_5, P28_5_TCPWM1_TR_ONE_CNT_IN204}, 2172 {4u, 205u, P28_6, P28_6_TCPWM1_TR_ONE_CNT_IN205}, 2173 {4u, 207u, P28_6, P28_6_TCPWM1_TR_ONE_CNT_IN207}, 2174 {4u, 208u, P28_7, P28_7_TCPWM1_TR_ONE_CNT_IN208}, 2175 {4u, 210u, P28_7, P28_7_TCPWM1_TR_ONE_CNT_IN210}, 2176 {4u, 226u, P29_0, P29_0_TCPWM1_TR_ONE_CNT_IN226}, 2177 {4u, 228u, P29_0, P29_0_TCPWM1_TR_ONE_CNT_IN228}, 2178 {4u, 229u, P29_1, P29_1_TCPWM1_TR_ONE_CNT_IN229}, 2179 {4u, 231u, P29_1, P29_1_TCPWM1_TR_ONE_CNT_IN231}, 2180 {4u, 232u, P29_2, P29_2_TCPWM1_TR_ONE_CNT_IN232}, 2181 {4u, 234u, P29_2, P29_2_TCPWM1_TR_ONE_CNT_IN234}, 2182 {4u, 235u, P29_3, P29_3_TCPWM1_TR_ONE_CNT_IN235}, 2183 {4u, 237u, P29_3, P29_3_TCPWM1_TR_ONE_CNT_IN237}, 2184 {4u, 238u, P29_4, P29_4_TCPWM1_TR_ONE_CNT_IN238}, 2185 {4u, 240u, P29_4, P29_4_TCPWM1_TR_ONE_CNT_IN240}, 2186 {4u, 241u, P29_5, P29_5_TCPWM1_TR_ONE_CNT_IN241}, 2187 {4u, 243u, P29_5, P29_5_TCPWM1_TR_ONE_CNT_IN243}, 2188 {4u, 244u, P29_6, P29_6_TCPWM1_TR_ONE_CNT_IN244}, 2189 {4u, 246u, P29_6, P29_6_TCPWM1_TR_ONE_CNT_IN246}, 2190 {4u, 247u, P29_7, P29_7_TCPWM1_TR_ONE_CNT_IN247}, 2191 {4u, 249u, P29_7, P29_7_TCPWM1_TR_ONE_CNT_IN249}, 2192 {4u, 249u, P30_0, P30_0_TCPWM1_TR_ONE_CNT_IN249}, 2193 {4u, 250u, P30_0, P30_0_TCPWM1_TR_ONE_CNT_IN250}, 2194 {4u, 246u, P30_1, P30_1_TCPWM1_TR_ONE_CNT_IN246}, 2195 {4u, 250u, P30_1, P30_1_TCPWM1_TR_ONE_CNT_IN250}, 2196 {4u, 243u, P30_2, P30_2_TCPWM1_TR_ONE_CNT_IN243}, 2197 {4u, 247u, P30_2, P30_2_TCPWM1_TR_ONE_CNT_IN247}, 2198 {4u, 240u, P30_3, P30_3_TCPWM1_TR_ONE_CNT_IN240}, 2199 {4u, 244u, P30_3, P30_3_TCPWM1_TR_ONE_CNT_IN244}, 2200 {4u, 237u, P31_0, P31_0_TCPWM1_TR_ONE_CNT_IN237}, 2201 {4u, 241u, P31_0, P31_0_TCPWM1_TR_ONE_CNT_IN241}, 2202 {4u, 234u, P31_1, P31_1_TCPWM1_TR_ONE_CNT_IN234}, 2203 {4u, 238u, P31_1, P31_1_TCPWM1_TR_ONE_CNT_IN238}, 2204 {4u, 231u, P31_2, P31_2_TCPWM1_TR_ONE_CNT_IN231}, 2205 {4u, 235u, P31_2, P31_2_TCPWM1_TR_ONE_CNT_IN235}, 2206 {4u, 228u, P32_0, P32_0_TCPWM1_TR_ONE_CNT_IN228}, 2207 {4u, 232u, P32_0, P32_0_TCPWM1_TR_ONE_CNT_IN232}, 2208 {4u, 225u, P32_1, P32_1_TCPWM1_TR_ONE_CNT_IN225}, 2209 {4u, 229u, P32_1, P32_1_TCPWM1_TR_ONE_CNT_IN229}, 2210 {4u, 222u, P32_2, P32_2_TCPWM1_TR_ONE_CNT_IN222}, 2211 {4u, 226u, P32_2, P32_2_TCPWM1_TR_ONE_CNT_IN226}, 2212 {4u, 219u, P32_3, P32_3_TCPWM1_TR_ONE_CNT_IN219}, 2213 {4u, 223u, P32_3, P32_3_TCPWM1_TR_ONE_CNT_IN223}, 2214 {4u, 216u, P32_4, P32_4_TCPWM1_TR_ONE_CNT_IN216}, 2215 {4u, 220u, P32_4, P32_4_TCPWM1_TR_ONE_CNT_IN220}, 2216 {4u, 213u, P32_5, P32_5_TCPWM1_TR_ONE_CNT_IN213}, 2217 {4u, 217u, P32_5, P32_5_TCPWM1_TR_ONE_CNT_IN217}, 2218 {4u, 210u, P32_6, P32_6_TCPWM1_TR_ONE_CNT_IN210}, 2219 {4u, 214u, P32_6, P32_6_TCPWM1_TR_ONE_CNT_IN214}, 2220 {4u, 207u, P32_7, P32_7_TCPWM1_TR_ONE_CNT_IN207}, 2221 {4u, 211u, P32_7, P32_7_TCPWM1_TR_ONE_CNT_IN211}, 2222 }; 2223 2224 #endif 2225
