1 /***************************************************************************//** 2 * \file cyhal_xmc7200_272_bga.c 3 * 4 * \brief 5 * XMC7200 device GPIO HAL header for 272-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_XMC7200_272_BGA_H_) 31 #include "pin_packages/cyhal_xmc7200_272_bga.h" 32 33 /* Pin connections */ 34 /* Connections for: audioss_clk_i2s_if */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3] = { 36 {0u, 0u, P12_1, P12_1_AUDIOSS0_CLK_I2S_IF}, 37 {1u, 0u, P13_4, P13_4_AUDIOSS1_CLK_I2S_IF}, 38 {2u, 0u, P15_0, P15_0_AUDIOSS2_CLK_I2S_IF}, 39 }; 40 41 /* Connections for: audioss_mclk */ 42 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3] = { 43 {0u, 0u, P11_0, P11_0_AUDIOSS0_MCLK}, 44 {1u, 0u, P13_0, P13_0_AUDIOSS1_MCLK}, 45 {2u, 0u, P14_0, P14_0_AUDIOSS2_MCLK}, 46 }; 47 48 /* Connections for: audioss_rx_sck */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3] = { 50 {0u, 0u, P12_2, P12_2_AUDIOSS0_RX_SCK}, 51 {1u, 0u, P13_5, P13_5_AUDIOSS1_RX_SCK}, 52 {2u, 0u, P15_1, P15_1_AUDIOSS2_RX_SCK}, 53 }; 54 55 /* Connections for: audioss_rx_sdi */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3] = { 57 {0u, 0u, P12_4, P12_4_AUDIOSS0_RX_SDI}, 58 {1u, 0u, P13_7, P13_7_AUDIOSS1_RX_SDI}, 59 {2u, 0u, P15_3, P15_3_AUDIOSS2_RX_SDI}, 60 }; 61 62 /* Connections for: audioss_rx_ws */ 63 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3] = { 64 {0u, 0u, P12_3, P12_3_AUDIOSS0_RX_WS}, 65 {1u, 0u, P13_6, P13_6_AUDIOSS1_RX_WS}, 66 {2u, 0u, P15_2, P15_2_AUDIOSS2_RX_WS}, 67 }; 68 69 /* Connections for: audioss_tx_sck */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3] = { 71 {0u, 0u, P11_1, P11_1_AUDIOSS0_TX_SCK}, 72 {1u, 0u, P13_1, P13_1_AUDIOSS1_TX_SCK}, 73 {2u, 0u, P14_1, P14_1_AUDIOSS2_TX_SCK}, 74 }; 75 76 /* Connections for: audioss_tx_sdo */ 77 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3] = { 78 {0u, 0u, P12_0, P12_0_AUDIOSS0_TX_SDO}, 79 {1u, 0u, P13_3, P13_3_AUDIOSS1_TX_SDO}, 80 {2u, 0u, P14_5, P14_5_AUDIOSS2_TX_SDO}, 81 }; 82 83 /* Connections for: audioss_tx_ws */ 84 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3] = { 85 {0u, 0u, P11_2, P11_2_AUDIOSS0_TX_WS}, 86 {1u, 0u, P13_2, P13_2_AUDIOSS1_TX_WS}, 87 {2u, 0u, P14_4, P14_4_AUDIOSS2_TX_WS}, 88 }; 89 90 /* Connections for: canfd_ttcan_rx */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[21] = { 92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 93 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 94 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 95 {1u, 2u, P3_7, P3_7_CANFD1_TTCAN_RX2}, 96 {0u, 1u, P4_4, P4_4_CANFD0_TTCAN_RX1}, 97 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 98 {0u, 4u, P7_4, P7_4_CANFD0_TTCAN_RX4}, 99 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 100 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 101 {1u, 1u, P12_5, P12_5_CANFD1_TTCAN_RX1}, 102 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 103 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 104 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 105 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 106 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 107 {1u, 2u, P20_4, P20_4_CANFD1_TTCAN_RX2}, 108 {1u, 4u, P20_7, P20_7_CANFD1_TTCAN_RX4}, 109 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 110 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 111 {1u, 3u, P30_3, P30_3_CANFD1_TTCAN_RX3}, 112 {1u, 4u, P32_7, P32_7_CANFD1_TTCAN_RX4}, 113 }; 114 115 /* Connections for: canfd_ttcan_tx */ 116 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[21] = { 117 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 118 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 119 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 120 {1u, 2u, P3_6, P3_6_CANFD1_TTCAN_TX2}, 121 {0u, 1u, P4_3, P4_3_CANFD0_TTCAN_TX1}, 122 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 123 {0u, 4u, P7_3, P7_3_CANFD0_TTCAN_TX4}, 124 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 125 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 126 {1u, 1u, P12_4, P12_4_CANFD1_TTCAN_TX1}, 127 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 128 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 129 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 130 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 131 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 132 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 133 {1u, 4u, P20_6, P20_6_CANFD1_TTCAN_TX4}, 134 {1u, 1u, P21_5, P21_5_CANFD1_TTCAN_TX1}, 135 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 136 {1u, 3u, P30_2, P30_2_CANFD1_TTCAN_TX3}, 137 {1u, 4u, P32_6, P32_6_CANFD1_TTCAN_TX4}, 138 }; 139 140 /* Connections for: cpuss_cal_sup_nz */ 141 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3] = { 142 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 143 {0u, 0u, P21_7, P21_7_CPUSS_CAL_SUP_NZ}, 144 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 145 }; 146 147 /* Connections for: cpuss_clk_fm_pump */ 148 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 149 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 150 }; 151 152 /* Connections for: cpuss_fault_out */ 153 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8] = { 154 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 155 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 156 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 157 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 158 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 159 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 160 {0u, 2u, P23_2, P23_2_CPUSS_FAULT_OUT2}, 161 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 162 }; 163 164 /* Connections for: cpuss_swj_swclk_tclk */ 165 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 166 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 167 }; 168 169 /* Connections for: cpuss_swj_swdio_tms */ 170 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 171 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 172 }; 173 174 /* Connections for: cpuss_swj_swdoe_tdi */ 175 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 176 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 177 }; 178 179 /* Connections for: cpuss_swj_swo_tdo */ 180 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 181 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 182 }; 183 184 /* Connections for: cpuss_swj_trstn */ 185 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 186 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 187 }; 188 189 /* Connections for: cpuss_trace_clock */ 190 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 191 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 192 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 193 }; 194 195 /* Connections for: cpuss_trace_data */ 196 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 197 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 198 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 199 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 200 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 201 {0u, 0u, P21_5, P21_5_CPUSS_TRACE_DATA0}, 202 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 203 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 204 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 205 }; 206 207 /* Connections for: eth_eth_tsu_timer_cmp_val */ 208 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[2] = { 209 {0u, 0u, P2_3, P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL}, 210 {1u, 0u, P27_7, P27_7_ETH1_ETH_TSU_TIMER_CMP_VAL}, 211 }; 212 213 /* Connections for: eth_mdc */ 214 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[2] = { 215 {0u, 0u, P3_1, P3_1_ETH0_MDC}, 216 {1u, 0u, P27_6, P27_6_ETH1_MDC}, 217 }; 218 219 /* Connections for: eth_mdio */ 220 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[2] = { 221 {0u, 0u, P3_0, P3_0_ETH0_MDIO}, 222 {1u, 0u, P27_5, P27_5_ETH1_MDIO}, 223 }; 224 225 /* Connections for: eth_ref_clk */ 226 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[2] = { 227 {0u, 0u, P18_0, P18_0_ETH0_REF_CLK}, 228 {1u, 0u, P26_0, P26_0_ETH1_REF_CLK}, 229 }; 230 231 /* Connections for: eth_rx_clk */ 232 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[2] = { 233 {0u, 0u, P23_3, P23_3_ETH0_RX_CLK}, 234 {1u, 0u, P27_4, P27_4_ETH1_RX_CLK}, 235 }; 236 237 /* Connections for: eth_rx_ctl */ 238 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[2] = { 239 {0u, 0u, P21_5, P21_5_ETH0_RX_CTL}, 240 {1u, 0u, P27_3, P27_3_ETH1_RX_CTL}, 241 }; 242 243 /* Connections for: eth_rx_er */ 244 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1] = { 245 {0u, 0u, P2_2, P2_2_ETH0_RX_ER}, 246 }; 247 248 /* Connections for: eth_rxd */ 249 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[8] = { 250 {0u, 0u, P19_0, P19_0_ETH0_RXD0}, 251 {0u, 1u, P19_1, P19_1_ETH0_RXD1}, 252 {0u, 2u, P19_2, P19_2_ETH0_RXD2}, 253 {0u, 3u, P19_3, P19_3_ETH0_RXD3}, 254 {1u, 0u, P26_7, P26_7_ETH1_RXD0}, 255 {1u, 1u, P27_0, P27_0_ETH1_RXD1}, 256 {1u, 2u, P27_1, P27_1_ETH1_RXD2}, 257 {1u, 3u, P27_2, P27_2_ETH1_RXD3}, 258 }; 259 260 /* Connections for: eth_tx_clk */ 261 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[2] = { 262 {0u, 0u, P18_3, P18_3_ETH0_TX_CLK}, 263 {1u, 0u, P26_2, P26_2_ETH1_TX_CLK}, 264 }; 265 266 /* Connections for: eth_tx_ctl */ 267 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[2] = { 268 {0u, 0u, P18_1, P18_1_ETH0_TX_CTL}, 269 {1u, 0u, P26_1, P26_1_ETH1_TX_CTL}, 270 }; 271 272 /* Connections for: eth_tx_er */ 273 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1] = { 274 {0u, 0u, P18_2, P18_2_ETH0_TX_ER}, 275 }; 276 277 /* Connections for: eth_txd */ 278 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[8] = { 279 {0u, 0u, P18_4, P18_4_ETH0_TXD0}, 280 {0u, 1u, P18_5, P18_5_ETH0_TXD1}, 281 {0u, 2u, P18_6, P18_6_ETH0_TXD2}, 282 {0u, 3u, P18_7, P18_7_ETH0_TXD3}, 283 {1u, 0u, P26_3, P26_3_ETH1_TXD0}, 284 {1u, 1u, P26_4, P26_4_ETH1_TXD1}, 285 {1u, 2u, P26_5, P26_5_ETH1_TXD2}, 286 {1u, 3u, P26_6, P26_6_ETH1_TXD3}, 287 }; 288 289 /* Connections for: flexray_rxda */ 290 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1] = { 291 {0u, 0u, P10_2, P10_2_FLEXRAY0_RXDA}, 292 }; 293 294 /* Connections for: flexray_rxdb */ 295 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1] = { 296 {0u, 0u, P10_5, P10_5_FLEXRAY0_RXDB}, 297 }; 298 299 /* Connections for: flexray_txda */ 300 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1] = { 301 {0u, 0u, P10_3, P10_3_FLEXRAY0_TXDA}, 302 }; 303 304 /* Connections for: flexray_txdb */ 305 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1] = { 306 {0u, 0u, P10_6, P10_6_FLEXRAY0_TXDB}, 307 }; 308 309 /* Connections for: flexray_txena_n */ 310 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1] = { 311 {0u, 0u, P10_4, P10_4_FLEXRAY0_TXENA_N}, 312 }; 313 314 /* Connections for: flexray_txenb_n */ 315 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1] = { 316 {0u, 0u, P10_7, P10_7_FLEXRAY0_TXENB_N}, 317 }; 318 319 /* Connections for: lin_lin_en */ 320 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[38] = { 321 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 322 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 323 {0u, 5u, P2_5, P2_5_LIN0_LIN_EN5}, 324 {0u, 11u, P3_7, P3_7_LIN0_LIN_EN11}, 325 {0u, 1u, P4_2, P4_2_LIN0_LIN_EN1}, 326 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 327 {0u, 2u, P5_5, P5_5_LIN0_LIN_EN2}, 328 {0u, 9u, P6_0, P6_0_LIN0_LIN_EN9}, 329 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 330 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 331 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 332 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 333 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 334 {0u, 16u, P9_0, P9_0_LIN0_LIN_EN16}, 335 {0u, 12u, P9_3, P9_3_LIN0_LIN_EN12}, 336 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 337 {0u, 13u, P10_7, P10_7_LIN0_LIN_EN13}, 338 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 339 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 340 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 341 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 342 {0u, 14u, P14_7, P14_7_LIN0_LIN_EN14}, 343 {0u, 11u, P16_2, P16_2_LIN0_LIN_EN11}, 344 {0u, 11u, P17_2, P17_2_LIN0_LIN_EN11}, 345 {0u, 15u, P17_7, P17_7_LIN0_LIN_EN15}, 346 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 347 {0u, 0u, P21_7, P21_7_LIN0_LIN_EN0}, 348 {0u, 7u, P22_7, P22_7_LIN0_LIN_EN7}, 349 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 350 {0u, 16u, P24_4, P24_4_LIN0_LIN_EN16}, 351 {0u, 17u, P28_3, P28_3_LIN0_LIN_EN17}, 352 {0u, 18u, P28_6, P28_6_LIN0_LIN_EN18}, 353 {0u, 19u, P29_1, P29_1_LIN0_LIN_EN19}, 354 {0u, 16u, P30_3, P30_3_LIN0_LIN_EN16}, 355 {0u, 17u, P31_2, P31_2_LIN0_LIN_EN17}, 356 {0u, 18u, P32_4, P32_4_LIN0_LIN_EN18}, 357 {0u, 10u, P32_6, P32_6_LIN0_LIN_EN10}, 358 {0u, 19u, P32_7, P32_7_LIN0_LIN_EN19}, 359 }; 360 361 /* Connections for: lin_lin_rx */ 362 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[49] = { 363 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 364 {0u, 0u, P1_2, P1_2_LIN0_LIN_RX0}, 365 {0u, 8u, P1_4, P1_4_LIN0_LIN_RX8}, 366 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 367 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 368 {0u, 11u, P2_7, P2_7_LIN0_LIN_RX11}, 369 {0u, 1u, P3_4, P3_4_LIN0_LIN_RX1}, 370 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 371 {0u, 15u, P4_4, P4_4_LIN0_LIN_RX15}, 372 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 373 {0u, 10u, P5_2, P5_2_LIN0_LIN_RX10}, 374 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 375 {0u, 9u, P5_4, P5_4_LIN0_LIN_RX9}, 376 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 377 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 378 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 379 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 380 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 381 {0u, 16u, P8_3, P8_3_LIN0_LIN_RX16}, 382 {0u, 12u, P9_1, P9_1_LIN0_LIN_RX12}, 383 {0u, 7u, P10_0, P10_0_LIN0_LIN_RX7}, 384 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 385 {0u, 13u, P10_5, P10_5_LIN0_LIN_RX13}, 386 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 387 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 388 {0u, 2u, P13_3, P13_3_LIN0_LIN_RX2}, 389 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 390 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 391 {0u, 14u, P14_5, P14_5_LIN0_LIN_RX14}, 392 {0u, 11u, P16_0, P16_0_LIN0_LIN_RX11}, 393 {0u, 11u, P17_0, P17_0_LIN0_LIN_RX11}, 394 {0u, 15u, P17_5, P17_5_LIN0_LIN_RX15}, 395 {0u, 12u, P17_7, P17_7_LIN0_LIN_RX12}, 396 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 397 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 398 {0u, 13u, P21_6, P21_6_LIN0_LIN_RX13}, 399 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 400 {0u, 14u, P22_7, P22_7_LIN0_LIN_RX14}, 401 {0u, 6u, P23_2, P23_2_LIN0_LIN_RX6}, 402 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 403 {0u, 16u, P24_0, P24_0_LIN0_LIN_RX16}, 404 {0u, 17u, P28_1, P28_1_LIN0_LIN_RX17}, 405 {0u, 18u, P28_4, P28_4_LIN0_LIN_RX18}, 406 {0u, 19u, P28_7, P28_7_LIN0_LIN_RX19}, 407 {0u, 16u, P30_1, P30_1_LIN0_LIN_RX16}, 408 {0u, 17u, P31_0, P31_0_LIN0_LIN_RX17}, 409 {0u, 18u, P32_2, P32_2_LIN0_LIN_RX18}, 410 {0u, 10u, P32_4, P32_4_LIN0_LIN_RX10}, 411 {0u, 19u, P32_5, P32_5_LIN0_LIN_RX19}, 412 }; 413 414 /* Connections for: lin_lin_tx */ 415 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[48] = { 416 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 417 {0u, 0u, P1_3, P1_3_LIN0_LIN_TX0}, 418 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 419 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 420 {0u, 1u, P3_5, P3_5_LIN0_LIN_TX1}, 421 {0u, 11u, P3_6, P3_6_LIN0_LIN_TX11}, 422 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 423 {0u, 15u, P5_0, P5_0_LIN0_LIN_TX15}, 424 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 425 {0u, 10u, P5_3, P5_3_LIN0_LIN_TX10}, 426 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 427 {0u, 9u, P5_5, P5_5_LIN0_LIN_TX9}, 428 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 429 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 430 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 431 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 432 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 433 {0u, 16u, P8_4, P8_4_LIN0_LIN_TX16}, 434 {0u, 12u, P9_2, P9_2_LIN0_LIN_TX12}, 435 {0u, 7u, P10_1, P10_1_LIN0_LIN_TX7}, 436 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 437 {0u, 13u, P10_6, P10_6_LIN0_LIN_TX13}, 438 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 439 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 440 {0u, 2u, P13_4, P13_4_LIN0_LIN_TX2}, 441 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 442 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 443 {0u, 14u, P14_6, P14_6_LIN0_LIN_TX14}, 444 {0u, 11u, P16_1, P16_1_LIN0_LIN_TX11}, 445 {0u, 11u, P17_1, P17_1_LIN0_LIN_TX11}, 446 {0u, 15u, P17_6, P17_6_LIN0_LIN_TX15}, 447 {0u, 12u, P18_0, P18_0_LIN0_LIN_TX12}, 448 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 449 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 450 {0u, 13u, P21_7, P21_7_LIN0_LIN_TX13}, 451 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 452 {0u, 14u, P23_0, P23_0_LIN0_LIN_TX14}, 453 {0u, 6u, P23_3, P23_3_LIN0_LIN_TX6}, 454 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 455 {0u, 16u, P24_3, P24_3_LIN0_LIN_TX16}, 456 {0u, 17u, P28_2, P28_2_LIN0_LIN_TX17}, 457 {0u, 18u, P28_5, P28_5_LIN0_LIN_TX18}, 458 {0u, 19u, P29_0, P29_0_LIN0_LIN_TX19}, 459 {0u, 16u, P30_2, P30_2_LIN0_LIN_TX16}, 460 {0u, 17u, P31_1, P31_1_LIN0_LIN_TX17}, 461 {0u, 18u, P32_3, P32_3_LIN0_LIN_TX18}, 462 {0u, 10u, P32_5, P32_5_LIN0_LIN_TX10}, 463 {0u, 19u, P32_6, P32_6_LIN0_LIN_TX19}, 464 }; 465 466 /* Connections for: pass_sar_ext_mux_en */ 467 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3] = { 468 {0u, 0u, P4_3, P4_3_PASS0_SAR_EXT_MUX_EN0}, 469 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 470 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 471 }; 472 473 /* Connections for: pass_sar_ext_mux_sel */ 474 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9] = { 475 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 476 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 477 {0u, 2u, P4_2, P4_2_PASS0_SAR_EXT_MUX_SEL2}, 478 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 479 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 480 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 481 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 482 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 483 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 484 }; 485 486 /* Connections for: pass_sarmux_pads */ 487 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[96] = { 488 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 489 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 490 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 491 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 492 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 493 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 494 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 495 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 496 {0u, 16u, P7_0, HSIOM_SEL_GPIO}, 497 {0u, 17u, P7_1, HSIOM_SEL_GPIO}, 498 {0u, 18u, P7_2, HSIOM_SEL_GPIO}, 499 {0u, 19u, P7_3, HSIOM_SEL_GPIO}, 500 {0u, 20u, P7_4, HSIOM_SEL_GPIO}, 501 {0u, 21u, P7_5, HSIOM_SEL_GPIO}, 502 {0u, 22u, P7_6, HSIOM_SEL_GPIO}, 503 {0u, 23u, P7_7, HSIOM_SEL_GPIO}, 504 {0u, 24u, P8_1, HSIOM_SEL_GPIO}, 505 {0u, 25u, P8_2, HSIOM_SEL_GPIO}, 506 {0u, 26u, P8_3, HSIOM_SEL_GPIO}, 507 {0u, 27u, P8_4, HSIOM_SEL_GPIO}, 508 {0u, 28u, P9_0, HSIOM_SEL_GPIO}, 509 {0u, 29u, P9_1, HSIOM_SEL_GPIO}, 510 {0u, 30u, P9_2, HSIOM_SEL_GPIO}, 511 {0u, 31u, P9_3, HSIOM_SEL_GPIO}, 512 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 513 {1u, 1u, P10_5, HSIOM_SEL_GPIO}, 514 {1u, 2u, P10_6, HSIOM_SEL_GPIO}, 515 {1u, 3u, P10_7, HSIOM_SEL_GPIO}, 516 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 517 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 518 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 519 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 520 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 521 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 522 {1u, 10u, P12_6, HSIOM_SEL_GPIO}, 523 {1u, 11u, P12_7, HSIOM_SEL_GPIO}, 524 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 525 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 526 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 527 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 528 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 529 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 530 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 531 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 532 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 533 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 534 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 535 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 536 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 537 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 538 {1u, 26u, P14_6, HSIOM_SEL_GPIO}, 539 {1u, 27u, P14_7, HSIOM_SEL_GPIO}, 540 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 541 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 542 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 543 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 544 {2u, 0u, P16_0, HSIOM_SEL_GPIO}, 545 {2u, 1u, P16_1, HSIOM_SEL_GPIO}, 546 {2u, 2u, P16_2, HSIOM_SEL_GPIO}, 547 {2u, 3u, P16_3, HSIOM_SEL_GPIO}, 548 {2u, 4u, P16_4, HSIOM_SEL_GPIO}, 549 {2u, 5u, P16_5, HSIOM_SEL_GPIO}, 550 {2u, 6u, P16_6, HSIOM_SEL_GPIO}, 551 {2u, 7u, P16_7, HSIOM_SEL_GPIO}, 552 {2u, 8u, P17_0, HSIOM_SEL_GPIO}, 553 {2u, 9u, P17_1, HSIOM_SEL_GPIO}, 554 {2u, 10u, P17_2, HSIOM_SEL_GPIO}, 555 {2u, 11u, P17_3, HSIOM_SEL_GPIO}, 556 {2u, 12u, P17_4, HSIOM_SEL_GPIO}, 557 {2u, 13u, P17_5, HSIOM_SEL_GPIO}, 558 {2u, 14u, P17_6, HSIOM_SEL_GPIO}, 559 {2u, 15u, P17_7, HSIOM_SEL_GPIO}, 560 {2u, 16u, P18_0, HSIOM_SEL_GPIO}, 561 {2u, 17u, P18_1, HSIOM_SEL_GPIO}, 562 {2u, 18u, P18_2, HSIOM_SEL_GPIO}, 563 {2u, 19u, P18_3, HSIOM_SEL_GPIO}, 564 {2u, 20u, P18_4, HSIOM_SEL_GPIO}, 565 {2u, 21u, P18_5, HSIOM_SEL_GPIO}, 566 {2u, 22u, P18_6, HSIOM_SEL_GPIO}, 567 {2u, 23u, P18_7, HSIOM_SEL_GPIO}, 568 {2u, 24u, P19_0, HSIOM_SEL_GPIO}, 569 {2u, 25u, P19_1, HSIOM_SEL_GPIO}, 570 {2u, 26u, P19_2, HSIOM_SEL_GPIO}, 571 {2u, 27u, P19_3, HSIOM_SEL_GPIO}, 572 {2u, 28u, P19_4, HSIOM_SEL_GPIO}, 573 {2u, 29u, P20_0, HSIOM_SEL_GPIO}, 574 {2u, 30u, P20_1, HSIOM_SEL_GPIO}, 575 {2u, 31u, P20_2, HSIOM_SEL_GPIO}, 576 {0u, 8u, P32_0, HSIOM_SEL_GPIO}, 577 {0u, 9u, P32_1, HSIOM_SEL_GPIO}, 578 {0u, 10u, P32_2, HSIOM_SEL_GPIO}, 579 {0u, 11u, P32_3, HSIOM_SEL_GPIO}, 580 {0u, 12u, P32_4, HSIOM_SEL_GPIO}, 581 {0u, 13u, P32_5, HSIOM_SEL_GPIO}, 582 {0u, 14u, P32_6, HSIOM_SEL_GPIO}, 583 {0u, 15u, P32_7, HSIOM_SEL_GPIO}, 584 }; 585 586 /* Connections for: peri_tr_io_input */ 587 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 588 to know the index of the input or output trigger line. Store that in the channel_num field 589 instead. */ 590 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[46] = { 591 {0u, 0u, P1_2, P1_2_PERI_TR_IO_INPUT0}, 592 {0u, 1u, P1_3, P1_3_PERI_TR_IO_INPUT1}, 593 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 594 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 595 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 596 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 597 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 598 {0u, 7u, P2_5, P2_5_PERI_TR_IO_INPUT7}, 599 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 600 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 601 {0u, 12u, P4_2, P4_2_PERI_TR_IO_INPUT12}, 602 {0u, 13u, P4_3, P4_3_PERI_TR_IO_INPUT13}, 603 {0u, 38u, P5_0, P5_0_PERI_TR_IO_INPUT38}, 604 {0u, 39u, P5_1, P5_1_PERI_TR_IO_INPUT39}, 605 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 606 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 607 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 608 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 609 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 610 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 611 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 612 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 613 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 614 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 615 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 616 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 617 {0u, 24u, P14_6, P14_6_PERI_TR_IO_INPUT24}, 618 {0u, 25u, P14_7, P14_7_PERI_TR_IO_INPUT25}, 619 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 620 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 621 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 622 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 623 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 624 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 625 {0u, 34u, P30_0, P30_0_PERI_TR_IO_INPUT34}, 626 {0u, 35u, P30_1, P30_1_PERI_TR_IO_INPUT35}, 627 {0u, 36u, P30_2, P30_2_PERI_TR_IO_INPUT36}, 628 {0u, 37u, P30_3, P30_3_PERI_TR_IO_INPUT37}, 629 {0u, 40u, P32_0, P32_0_PERI_TR_IO_INPUT40}, 630 {0u, 41u, P32_1, P32_1_PERI_TR_IO_INPUT41}, 631 {0u, 42u, P32_2, P32_2_PERI_TR_IO_INPUT42}, 632 {0u, 43u, P32_3, P32_3_PERI_TR_IO_INPUT43}, 633 {0u, 44u, P32_4, P32_4_PERI_TR_IO_INPUT44}, 634 {0u, 45u, P32_5, P32_5_PERI_TR_IO_INPUT45}, 635 {0u, 46u, P32_6, P32_6_PERI_TR_IO_INPUT46}, 636 {0u, 47u, P32_7, P32_7_PERI_TR_IO_INPUT47}, 637 }; 638 639 /* Connections for: peri_tr_io_output */ 640 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 641 to know the index of the input or output trigger line. Store that in the channel_num field 642 instead. */ 643 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6] = { 644 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 645 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 646 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 647 {0u, 1u, P8_4, P8_4_PERI_TR_IO_OUTPUT1}, 648 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 649 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 650 }; 651 652 /* Connections for: scb_i2c_scl */ 653 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[22] = { 654 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 655 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 656 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 657 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 658 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 659 {5u, 0u, P4_2, P4_2_SCB5_I2C_SCL}, 660 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 661 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 662 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 663 {8u, 0u, P12_2, P12_2_SCB8_I2C_SCL}, 664 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 665 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 666 {9u, 0u, P15_2, P15_2_SCB9_I2C_SCL}, 667 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 668 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 669 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 670 {1u, 0u, P20_5, P20_5_SCB1_I2C_SCL}, 671 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 672 {7u, 0u, P23_2, P23_2_SCB7_I2C_SCL}, 673 {10u, 0u, P28_2, P28_2_SCB10_I2C_SCL}, 674 {9u, 0u, P30_0, P30_0_SCB9_I2C_SCL}, 675 {10u, 0u, P32_2, P32_2_SCB10_I2C_SCL}, 676 }; 677 678 /* Connections for: scb_i2c_sda */ 679 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21] = { 680 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 681 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 682 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 683 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 684 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 685 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 686 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 687 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 688 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 689 {8u, 0u, P12_1, P12_1_SCB8_I2C_SDA}, 690 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 691 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 692 {9u, 0u, P15_1, P15_1_SCB9_I2C_SDA}, 693 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 694 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 695 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 696 {1u, 0u, P20_4, P20_4_SCB1_I2C_SDA}, 697 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 698 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 699 {10u, 0u, P28_1, P28_1_SCB10_I2C_SDA}, 700 {10u, 0u, P32_1, P32_1_SCB10_I2C_SDA}, 701 }; 702 703 /* Connections for: scb_spi_m_clk */ 704 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[24] = { 705 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 706 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 707 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 708 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 709 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 710 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 711 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 712 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 713 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 714 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 715 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 716 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 717 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 718 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 719 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 720 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 721 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 722 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 723 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 724 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 725 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 726 {10u, 0u, P28_2, P28_2_SCB10_SPI_CLK}, 727 {9u, 0u, P30_0, P30_0_SCB9_SPI_CLK}, 728 {10u, 0u, P32_2, P32_2_SCB10_SPI_CLK}, 729 }; 730 731 /* Connections for: scb_spi_m_miso */ 732 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[23] = { 733 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 734 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 735 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 736 {8u, 0u, P1_4, P1_4_SCB8_SPI_MISO}, 737 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 738 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 739 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 740 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 741 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 742 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 743 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 744 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 745 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 746 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 747 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 748 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 749 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 750 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 751 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 752 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 753 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 754 {10u, 0u, P28_0, P28_0_SCB10_SPI_MISO}, 755 {10u, 0u, P32_0, P32_0_SCB10_SPI_MISO}, 756 }; 757 758 /* Connections for: scb_spi_m_mosi */ 759 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[22] = { 760 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 761 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 762 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 763 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 764 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 765 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 766 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 767 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 768 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 769 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 770 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 771 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 772 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 773 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 774 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 775 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 776 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 777 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 778 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 779 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 780 {10u, 0u, P28_1, P28_1_SCB10_SPI_MOSI}, 781 {10u, 0u, P32_1, P32_1_SCB10_SPI_MOSI}, 782 }; 783 784 /* Connections for: scb_spi_m_select0 */ 785 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[25] = { 786 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 787 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 788 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 789 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 790 {8u, 0u, P2_6, P2_6_SCB8_SPI_SELECT0}, 791 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 792 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 793 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 794 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 795 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 796 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 797 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 798 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 799 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 800 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 801 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 802 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 803 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 804 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 805 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 806 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 807 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 808 {10u, 0u, P28_3, P28_3_SCB10_SPI_SELECT0}, 809 {9u, 0u, P30_1, P30_1_SCB9_SPI_SELECT0}, 810 {10u, 0u, P32_3, P32_3_SCB10_SPI_SELECT0}, 811 }; 812 813 /* Connections for: scb_spi_m_select1 */ 814 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[21] = { 815 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 816 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 817 {8u, 0u, P2_7, P2_7_SCB8_SPI_SELECT1}, 818 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 819 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 820 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 821 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 822 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 823 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 824 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 825 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 826 {9u, 0u, P16_0, P16_0_SCB9_SPI_SELECT1}, 827 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 828 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 829 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 830 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 831 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 832 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 833 {10u, 0u, P28_4, P28_4_SCB10_SPI_SELECT1}, 834 {9u, 0u, P30_2, P30_2_SCB9_SPI_SELECT1}, 835 {10u, 0u, P32_4, P32_4_SCB10_SPI_SELECT1}, 836 }; 837 838 /* Connections for: scb_spi_m_select2 */ 839 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[20] = { 840 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 841 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 842 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 843 {8u, 0u, P3_6, P3_6_SCB8_SPI_SELECT2}, 844 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 845 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 846 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 847 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 848 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 849 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 850 {9u, 0u, P16_1, P16_1_SCB9_SPI_SELECT2}, 851 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 852 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 853 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 854 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 855 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 856 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 857 {10u, 0u, P28_5, P28_5_SCB10_SPI_SELECT2}, 858 {9u, 0u, P30_3, P30_3_SCB9_SPI_SELECT2}, 859 {10u, 0u, P32_5, P32_5_SCB10_SPI_SELECT2}, 860 }; 861 862 /* Connections for: scb_spi_m_select3 */ 863 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8] = { 864 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 865 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 866 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 867 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 868 {9u, 0u, P16_2, P16_2_SCB9_SPI_SELECT3}, 869 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 870 {10u, 0u, P28_6, P28_6_SCB10_SPI_SELECT3}, 871 {10u, 0u, P32_6, P32_6_SCB10_SPI_SELECT3}, 872 }; 873 874 /* Connections for: scb_spi_s_clk */ 875 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[24] = { 876 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 877 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 878 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 879 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 880 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 881 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 882 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 883 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 884 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 885 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 886 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 887 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 888 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 889 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 890 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 891 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 892 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 893 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 894 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 895 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 896 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 897 {10u, 0u, P28_2, P28_2_SCB10_SPI_CLK}, 898 {9u, 0u, P30_0, P30_0_SCB9_SPI_CLK}, 899 {10u, 0u, P32_2, P32_2_SCB10_SPI_CLK}, 900 }; 901 902 /* Connections for: scb_spi_s_miso */ 903 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[23] = { 904 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 905 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 906 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 907 {8u, 0u, P1_4, P1_4_SCB8_SPI_MISO}, 908 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 909 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 910 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 911 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 912 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 913 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 914 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 915 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 916 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 917 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 918 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 919 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 920 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 921 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 922 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 923 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 924 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 925 {10u, 0u, P28_0, P28_0_SCB10_SPI_MISO}, 926 {10u, 0u, P32_0, P32_0_SCB10_SPI_MISO}, 927 }; 928 929 /* Connections for: scb_spi_s_mosi */ 930 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[22] = { 931 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 932 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 933 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 934 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 935 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 936 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 937 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 938 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 939 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 940 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 941 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 942 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 943 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 944 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 945 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 946 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 947 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 948 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 949 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 950 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 951 {10u, 0u, P28_1, P28_1_SCB10_SPI_MOSI}, 952 {10u, 0u, P32_1, P32_1_SCB10_SPI_MOSI}, 953 }; 954 955 /* Connections for: scb_spi_s_select0 */ 956 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[25] = { 957 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 958 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 959 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 960 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 961 {8u, 0u, P2_6, P2_6_SCB8_SPI_SELECT0}, 962 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 963 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 964 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 965 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 966 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 967 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 968 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 969 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 970 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 971 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 972 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 973 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 974 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 975 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 976 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 977 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 978 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 979 {10u, 0u, P28_3, P28_3_SCB10_SPI_SELECT0}, 980 {9u, 0u, P30_1, P30_1_SCB9_SPI_SELECT0}, 981 {10u, 0u, P32_3, P32_3_SCB10_SPI_SELECT0}, 982 }; 983 984 /* Connections for: scb_spi_s_select1 */ 985 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[21] = { 986 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 987 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 988 {8u, 0u, P2_7, P2_7_SCB8_SPI_SELECT1}, 989 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 990 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 991 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 992 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 993 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 994 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 995 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 996 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 997 {9u, 0u, P16_0, P16_0_SCB9_SPI_SELECT1}, 998 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 999 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 1000 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 1001 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 1002 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 1003 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 1004 {10u, 0u, P28_4, P28_4_SCB10_SPI_SELECT1}, 1005 {9u, 0u, P30_2, P30_2_SCB9_SPI_SELECT1}, 1006 {10u, 0u, P32_4, P32_4_SCB10_SPI_SELECT1}, 1007 }; 1008 1009 /* Connections for: scb_spi_s_select2 */ 1010 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[20] = { 1011 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 1012 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 1013 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 1014 {8u, 0u, P3_6, P3_6_SCB8_SPI_SELECT2}, 1015 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 1016 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 1017 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 1018 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 1019 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 1020 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 1021 {9u, 0u, P16_1, P16_1_SCB9_SPI_SELECT2}, 1022 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 1023 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 1024 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 1025 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 1026 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 1027 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 1028 {10u, 0u, P28_5, P28_5_SCB10_SPI_SELECT2}, 1029 {9u, 0u, P30_3, P30_3_SCB9_SPI_SELECT2}, 1030 {10u, 0u, P32_5, P32_5_SCB10_SPI_SELECT2}, 1031 }; 1032 1033 /* Connections for: scb_spi_s_select3 */ 1034 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8] = { 1035 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 1036 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 1037 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 1038 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 1039 {9u, 0u, P16_2, P16_2_SCB9_SPI_SELECT3}, 1040 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 1041 {10u, 0u, P28_6, P28_6_SCB10_SPI_SELECT3}, 1042 {10u, 0u, P32_6, P32_6_SCB10_SPI_SELECT3}, 1043 }; 1044 1045 /* Connections for: scb_uart_cts */ 1046 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[21] = { 1047 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 1048 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 1049 {8u, 0u, P2_6, P2_6_SCB8_UART_CTS}, 1050 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 1051 {5u, 0u, P4_3, P4_3_SCB5_UART_CTS}, 1052 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 1053 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 1054 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 1055 {8u, 0u, P12_3, P12_3_SCB8_UART_CTS}, 1056 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 1057 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 1058 {9u, 0u, P15_3, P15_3_SCB9_UART_CTS}, 1059 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 1060 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 1061 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 1062 {1u, 0u, P20_6, P20_6_SCB1_UART_CTS}, 1063 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 1064 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 1065 {10u, 0u, P28_3, P28_3_SCB10_UART_CTS}, 1066 {9u, 0u, P30_1, P30_1_SCB9_UART_CTS}, 1067 {10u, 0u, P32_3, P32_3_SCB10_UART_CTS}, 1068 }; 1069 1070 /* Connections for: scb_uart_rts */ 1071 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[20] = { 1072 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 1073 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 1074 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 1075 {5u, 0u, P4_2, P4_2_SCB5_UART_RTS}, 1076 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 1077 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 1078 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 1079 {8u, 0u, P12_2, P12_2_SCB8_UART_RTS}, 1080 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 1081 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 1082 {9u, 0u, P15_2, P15_2_SCB9_UART_RTS}, 1083 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 1084 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 1085 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 1086 {1u, 0u, P20_5, P20_5_SCB1_UART_RTS}, 1087 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 1088 {7u, 0u, P23_2, P23_2_SCB7_UART_RTS}, 1089 {10u, 0u, P28_2, P28_2_SCB10_UART_RTS}, 1090 {9u, 0u, P30_0, P30_0_SCB9_UART_RTS}, 1091 {10u, 0u, P32_2, P32_2_SCB10_UART_RTS}, 1092 }; 1093 1094 /* Connections for: scb_uart_rx */ 1095 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[20] = { 1096 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 1097 {8u, 0u, P1_4, P1_4_SCB8_UART_RX}, 1098 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 1099 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 1100 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 1101 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 1102 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 1103 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 1104 {8u, 0u, P12_0, P12_0_SCB8_UART_RX}, 1105 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 1106 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 1107 {9u, 0u, P15_0, P15_0_SCB9_UART_RX}, 1108 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 1109 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 1110 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 1111 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 1112 {6u, 0u, P21_7, P21_7_SCB6_UART_RX}, 1113 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 1114 {10u, 0u, P28_0, P28_0_SCB10_UART_RX}, 1115 {10u, 0u, P32_0, P32_0_SCB10_UART_RX}, 1116 }; 1117 1118 /* Connections for: scb_uart_tx */ 1119 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19] = { 1120 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 1121 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 1122 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 1123 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 1124 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 1125 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 1126 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 1127 {8u, 0u, P12_1, P12_1_SCB8_UART_TX}, 1128 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 1129 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 1130 {9u, 0u, P15_1, P15_1_SCB9_UART_TX}, 1131 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 1132 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 1133 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 1134 {1u, 0u, P20_4, P20_4_SCB1_UART_TX}, 1135 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 1136 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 1137 {10u, 0u, P28_1, P28_1_SCB10_UART_TX}, 1138 {10u, 0u, P32_1, P32_1_SCB10_UART_TX}, 1139 }; 1140 1141 /* Connections for: sdhc_card_cmd */ 1142 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2] = { 1143 {0u, 0u, P6_3, P6_3_SDHC0_CARD_CMD}, 1144 {0u, 0u, P24_3, P24_3_SDHC0_CARD_CMD}, 1145 }; 1146 1147 /* Connections for: sdhc_card_dat_3to0 */ 1148 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8] = { 1149 {0u, 0u, P7_1, P7_1_SDHC0_CARD_DAT_3TO00}, 1150 {0u, 1u, P7_2, P7_2_SDHC0_CARD_DAT_3TO01}, 1151 {0u, 2u, P7_3, P7_3_SDHC0_CARD_DAT_3TO02}, 1152 {0u, 3u, P7_4, P7_4_SDHC0_CARD_DAT_3TO03}, 1153 {0u, 0u, P25_0, P25_0_SDHC0_CARD_DAT_3TO00}, 1154 {0u, 1u, P25_1, P25_1_SDHC0_CARD_DAT_3TO01}, 1155 {0u, 2u, P25_2, P25_2_SDHC0_CARD_DAT_3TO02}, 1156 {0u, 3u, P25_3, P25_3_SDHC0_CARD_DAT_3TO03}, 1157 }; 1158 1159 /* Connections for: sdhc_card_dat_7to4 */ 1160 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[8] = { 1161 {0u, 0u, P7_5, P7_5_SDHC0_CARD_DAT_7TO40}, 1162 {0u, 1u, P8_0, P8_0_SDHC0_CARD_DAT_7TO41}, 1163 {0u, 2u, P8_1, P8_1_SDHC0_CARD_DAT_7TO42}, 1164 {0u, 3u, P8_2, P8_2_SDHC0_CARD_DAT_7TO43}, 1165 {0u, 0u, P25_4, P25_4_SDHC0_CARD_DAT_7TO40}, 1166 {0u, 1u, P25_5, P25_5_SDHC0_CARD_DAT_7TO41}, 1167 {0u, 2u, P25_6, P25_6_SDHC0_CARD_DAT_7TO42}, 1168 {0u, 3u, P25_7, P25_7_SDHC0_CARD_DAT_7TO43}, 1169 }; 1170 1171 /* Connections for: sdhc_card_detect_n */ 1172 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2] = { 1173 {0u, 0u, P6_5, P6_5_SDHC0_CARD_DETECT_N}, 1174 {0u, 0u, P24_0, P24_0_SDHC0_CARD_DETECT_N}, 1175 }; 1176 1177 /* Connections for: sdhc_card_if_pwr_en */ 1178 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2] = { 1179 {0u, 0u, P7_0, P7_0_SDHC0_CARD_IF_PWR_EN}, 1180 {0u, 0u, P24_4, P24_4_SDHC0_CARD_IF_PWR_EN}, 1181 }; 1182 1183 /* Connections for: sdhc_card_mech_write_prot */ 1184 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2] = { 1185 {0u, 0u, P6_2, P6_2_SDHC0_CARD_MECH_WRITE_PROT}, 1186 {0u, 0u, P24_1, P24_1_SDHC0_CARD_MECH_WRITE_PROT}, 1187 }; 1188 1189 /* Connections for: sdhc_clk_card */ 1190 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2] = { 1191 {0u, 0u, P6_4, P6_4_SDHC0_CLK_CARD}, 1192 {0u, 0u, P24_2, P24_2_SDHC0_CLK_CARD}, 1193 }; 1194 1195 /* Connections for: smif_spi_clk */ 1196 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[2] = { 1197 {0u, 0u, P6_3, P6_3_SMIF0_SPIHB_CLK}, 1198 {0u, 0u, P24_1, P24_1_SMIF0_SPIHB_CLK}, 1199 }; 1200 1201 /* Connections for: smif_spi_data0 */ 1202 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[2] = { 1203 {0u, 0u, P7_1, P7_1_SMIF0_SPIHB_DATA0}, 1204 {0u, 0u, P25_0, P25_0_SMIF0_SPIHB_DATA0}, 1205 }; 1206 1207 /* Connections for: smif_spi_data1 */ 1208 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[2] = { 1209 {0u, 0u, P7_2, P7_2_SMIF0_SPIHB_DATA1}, 1210 {0u, 0u, P25_1, P25_1_SMIF0_SPIHB_DATA1}, 1211 }; 1212 1213 /* Connections for: smif_spi_data2 */ 1214 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[2] = { 1215 {0u, 0u, P7_3, P7_3_SMIF0_SPIHB_DATA2}, 1216 {0u, 0u, P25_2, P25_2_SMIF0_SPIHB_DATA2}, 1217 }; 1218 1219 /* Connections for: smif_spi_data3 */ 1220 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[2] = { 1221 {0u, 0u, P7_4, P7_4_SMIF0_SPIHB_DATA3}, 1222 {0u, 0u, P25_3, P25_3_SMIF0_SPIHB_DATA3}, 1223 }; 1224 1225 /* Connections for: smif_spi_data4 */ 1226 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[2] = { 1227 {0u, 0u, P7_5, P7_5_SMIF0_SPIHB_DATA4}, 1228 {0u, 0u, P25_4, P25_4_SMIF0_SPIHB_DATA4}, 1229 }; 1230 1231 /* Connections for: smif_spi_data5 */ 1232 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[2] = { 1233 {0u, 0u, P8_0, P8_0_SMIF0_SPIHB_DATA5}, 1234 {0u, 0u, P25_5, P25_5_SMIF0_SPIHB_DATA5}, 1235 }; 1236 1237 /* Connections for: smif_spi_data6 */ 1238 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[2] = { 1239 {0u, 0u, P8_1, P8_1_SMIF0_SPIHB_DATA6}, 1240 {0u, 0u, P25_6, P25_6_SMIF0_SPIHB_DATA6}, 1241 }; 1242 1243 /* Connections for: smif_spi_data7 */ 1244 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[2] = { 1245 {0u, 0u, P8_2, P8_2_SMIF0_SPIHB_DATA7}, 1246 {0u, 0u, P25_7, P25_7_SMIF0_SPIHB_DATA7}, 1247 }; 1248 1249 /* Connections for: smif_spi_rwds */ 1250 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[2] = { 1251 {0u, 0u, P6_4, P6_4_SMIF0_SPIHB_RWDS}, 1252 {0u, 0u, P24_2, P24_2_SMIF0_SPIHB_RWDS}, 1253 }; 1254 1255 /* Connections for: smif_spi_select0 */ 1256 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[2] = { 1257 {0u, 0u, P6_5, P6_5_SMIF0_SPIHB_SELECT0}, 1258 {0u, 0u, P24_3, P24_3_SMIF0_SPIHB_SELECT0}, 1259 }; 1260 1261 /* Connections for: smif_spi_select1 */ 1262 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[2] = { 1263 {0u, 0u, P7_0, P7_0_SMIF0_SPIHB_SELECT1}, 1264 {0u, 0u, P24_4, P24_4_SMIF0_SPIHB_SELECT1}, 1265 }; 1266 1267 /* Connections for: tcpwm_line */ 1268 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[227] = { 1269 {2u, 0u, P0_0, P0_0_TCPWM0_LINE512}, 1270 {4u, 18u, P0_0, P0_0_TCPWM1_LINE18}, 1271 {4u, 17u, P0_1, P0_1_TCPWM1_LINE17}, 1272 {4u, 14u, P0_2, P0_2_TCPWM1_LINE14}, 1273 {4u, 13u, P0_3, P0_3_TCPWM1_LINE13}, 1274 {4u, 12u, P1_0, P1_0_TCPWM1_LINE12}, 1275 {6u, 4u, P1_0, P1_0_TCPWM1_LINE516}, 1276 {4u, 11u, P1_1, P1_1_TCPWM1_LINE11}, 1277 {6u, 5u, P1_1, P1_1_TCPWM1_LINE517}, 1278 {4u, 10u, P1_2, P1_2_TCPWM1_LINE10}, 1279 {6u, 6u, P1_2, P1_2_TCPWM1_LINE518}, 1280 {4u, 8u, P1_3, P1_3_TCPWM1_LINE8}, 1281 {6u, 7u, P1_3, P1_3_TCPWM1_LINE519}, 1282 {4u, 71u, P1_4, P1_4_TCPWM1_LINE71}, 1283 {4u, 7u, P2_0, P2_0_TCPWM1_LINE7}, 1284 {4u, 6u, P2_1, P2_1_TCPWM1_LINE6}, 1285 {4u, 5u, P2_2, P2_2_TCPWM1_LINE5}, 1286 {4u, 4u, P2_3, P2_3_TCPWM1_LINE4}, 1287 {4u, 3u, P2_4, P2_4_TCPWM1_LINE3}, 1288 {4u, 2u, P2_5, P2_5_TCPWM1_LINE2}, 1289 {4u, 72u, P2_6, P2_6_TCPWM1_LINE72}, 1290 {4u, 73u, P2_7, P2_7_TCPWM1_LINE73}, 1291 {4u, 1u, P3_0, P3_0_TCPWM1_LINE1}, 1292 {4u, 0u, P3_1, P3_1_TCPWM1_LINE0}, 1293 {5u, 3u, P3_2, P3_2_TCPWM1_LINE259}, 1294 {5u, 2u, P3_3, P3_3_TCPWM1_LINE258}, 1295 {5u, 1u, P3_4, P3_4_TCPWM1_LINE257}, 1296 {5u, 0u, P3_5, P3_5_TCPWM1_LINE256}, 1297 {4u, 74u, P3_6, P3_6_TCPWM1_LINE74}, 1298 {4u, 75u, P3_7, P3_7_TCPWM1_LINE75}, 1299 {4u, 4u, P4_0, P4_0_TCPWM1_LINE4}, 1300 {4u, 5u, P4_1, P4_1_TCPWM1_LINE5}, 1301 {4u, 6u, P4_2, P4_2_TCPWM1_LINE6}, 1302 {4u, 7u, P4_3, P4_3_TCPWM1_LINE7}, 1303 {4u, 8u, P4_4, P4_4_TCPWM1_LINE8}, 1304 {1u, 0u, P5_0, P5_0_TCPWM0_LINE256}, 1305 {4u, 9u, P5_0, P5_0_TCPWM1_LINE9}, 1306 {6u, 10u, P5_0, P5_0_TCPWM1_LINE522}, 1307 {4u, 10u, P5_1, P5_1_TCPWM1_LINE10}, 1308 {4u, 11u, P5_2, P5_2_TCPWM1_LINE11}, 1309 {4u, 12u, P5_3, P5_3_TCPWM1_LINE12}, 1310 {4u, 13u, P5_4, P5_4_TCPWM1_LINE13}, 1311 {6u, 11u, P5_4, P5_4_TCPWM1_LINE523}, 1312 {4u, 14u, P5_5, P5_5_TCPWM1_LINE14}, 1313 {0u, 0u, P6_0, P6_0_TCPWM0_LINE0}, 1314 {5u, 0u, P6_0, P6_0_TCPWM1_LINE256}, 1315 {4u, 0u, P6_1, P6_1_TCPWM1_LINE0}, 1316 {5u, 1u, P6_2, P6_2_TCPWM1_LINE257}, 1317 {6u, 12u, P6_2, P6_2_TCPWM1_LINE524}, 1318 {4u, 1u, P6_3, P6_3_TCPWM1_LINE1}, 1319 {5u, 2u, P6_4, P6_4_TCPWM1_LINE258}, 1320 {4u, 2u, P6_5, P6_5_TCPWM1_LINE2}, 1321 {5u, 3u, P6_6, P6_6_TCPWM1_LINE259}, 1322 {4u, 3u, P6_7, P6_7_TCPWM1_LINE3}, 1323 {0u, 1u, P7_0, P7_0_TCPWM0_LINE1}, 1324 {5u, 4u, P7_0, P7_0_TCPWM1_LINE260}, 1325 {4u, 15u, P7_1, P7_1_TCPWM1_LINE15}, 1326 {5u, 5u, P7_2, P7_2_TCPWM1_LINE261}, 1327 {4u, 16u, P7_3, P7_3_TCPWM1_LINE16}, 1328 {5u, 6u, P7_4, P7_4_TCPWM1_LINE262}, 1329 {2u, 2u, P7_5, P7_5_TCPWM0_LINE514}, 1330 {4u, 17u, P7_5, P7_5_TCPWM1_LINE17}, 1331 {5u, 7u, P7_6, P7_6_TCPWM1_LINE263}, 1332 {4u, 18u, P7_7, P7_7_TCPWM1_LINE18}, 1333 {4u, 19u, P8_0, P8_0_TCPWM1_LINE19}, 1334 {6u, 8u, P8_0, P8_0_TCPWM1_LINE520}, 1335 {4u, 20u, P8_1, P8_1_TCPWM1_LINE20}, 1336 {4u, 21u, P8_2, P8_2_TCPWM1_LINE21}, 1337 {4u, 22u, P8_3, P8_3_TCPWM1_LINE22}, 1338 {4u, 23u, P8_4, P8_4_TCPWM1_LINE23}, 1339 {4u, 24u, P9_0, P9_0_TCPWM1_LINE24}, 1340 {6u, 9u, P9_0, P9_0_TCPWM1_LINE521}, 1341 {4u, 25u, P9_1, P9_1_TCPWM1_LINE25}, 1342 {4u, 26u, P9_2, P9_2_TCPWM1_LINE26}, 1343 {4u, 27u, P9_3, P9_3_TCPWM1_LINE27}, 1344 {4u, 28u, P10_0, P10_0_TCPWM1_LINE28}, 1345 {6u, 10u, P10_0, P10_0_TCPWM1_LINE522}, 1346 {4u, 29u, P10_1, P10_1_TCPWM1_LINE29}, 1347 {4u, 30u, P10_2, P10_2_TCPWM1_LINE30}, 1348 {4u, 31u, P10_3, P10_3_TCPWM1_LINE31}, 1349 {4u, 32u, P10_4, P10_4_TCPWM1_LINE32}, 1350 {6u, 11u, P10_4, P10_4_TCPWM1_LINE523}, 1351 {4u, 33u, P10_5, P10_5_TCPWM1_LINE33}, 1352 {4u, 34u, P10_6, P10_6_TCPWM1_LINE34}, 1353 {4u, 35u, P10_7, P10_7_TCPWM1_LINE35}, 1354 {4u, 61u, P11_0, P11_0_TCPWM1_LINE61}, 1355 {4u, 60u, P11_1, P11_1_TCPWM1_LINE60}, 1356 {4u, 59u, P11_2, P11_2_TCPWM1_LINE59}, 1357 {2u, 1u, P12_0, P12_0_TCPWM0_LINE513}, 1358 {4u, 36u, P12_0, P12_0_TCPWM1_LINE36}, 1359 {4u, 37u, P12_1, P12_1_TCPWM1_LINE37}, 1360 {4u, 38u, P12_2, P12_2_TCPWM1_LINE38}, 1361 {4u, 39u, P12_3, P12_3_TCPWM1_LINE39}, 1362 {4u, 40u, P12_4, P12_4_TCPWM1_LINE40}, 1363 {4u, 41u, P12_5, P12_5_TCPWM1_LINE41}, 1364 {4u, 42u, P12_6, P12_6_TCPWM1_LINE42}, 1365 {4u, 43u, P12_7, P12_7_TCPWM1_LINE43}, 1366 {5u, 8u, P13_0, P13_0_TCPWM1_LINE264}, 1367 {4u, 44u, P13_1, P13_1_TCPWM1_LINE44}, 1368 {0u, 2u, P13_2, P13_2_TCPWM0_LINE2}, 1369 {5u, 9u, P13_2, P13_2_TCPWM1_LINE265}, 1370 {4u, 45u, P13_3, P13_3_TCPWM1_LINE45}, 1371 {5u, 10u, P13_4, P13_4_TCPWM1_LINE266}, 1372 {6u, 4u, P13_4, P13_4_TCPWM1_LINE516}, 1373 {4u, 46u, P13_5, P13_5_TCPWM1_LINE46}, 1374 {5u, 11u, P13_6, P13_6_TCPWM1_LINE267}, 1375 {6u, 5u, P13_6, P13_6_TCPWM1_LINE517}, 1376 {4u, 47u, P13_7, P13_7_TCPWM1_LINE47}, 1377 {1u, 1u, P14_0, P14_0_TCPWM0_LINE257}, 1378 {4u, 48u, P14_0, P14_0_TCPWM1_LINE48}, 1379 {6u, 6u, P14_0, P14_0_TCPWM1_LINE518}, 1380 {4u, 49u, P14_1, P14_1_TCPWM1_LINE49}, 1381 {4u, 50u, P14_2, P14_2_TCPWM1_LINE50}, 1382 {6u, 7u, P14_2, P14_2_TCPWM1_LINE519}, 1383 {4u, 51u, P14_3, P14_3_TCPWM1_LINE51}, 1384 {4u, 52u, P14_4, P14_4_TCPWM1_LINE52}, 1385 {4u, 53u, P14_5, P14_5_TCPWM1_LINE53}, 1386 {4u, 54u, P14_6, P14_6_TCPWM1_LINE54}, 1387 {4u, 55u, P14_7, P14_7_TCPWM1_LINE55}, 1388 {4u, 56u, P15_0, P15_0_TCPWM1_LINE56}, 1389 {4u, 57u, P15_1, P15_1_TCPWM1_LINE57}, 1390 {4u, 58u, P15_2, P15_2_TCPWM1_LINE58}, 1391 {4u, 59u, P15_3, P15_3_TCPWM1_LINE59}, 1392 {4u, 60u, P16_0, P16_0_TCPWM1_LINE60}, 1393 {6u, 0u, P16_0, P16_0_TCPWM1_LINE512}, 1394 {4u, 61u, P16_1, P16_1_TCPWM1_LINE61}, 1395 {4u, 62u, P16_2, P16_2_TCPWM1_LINE62}, 1396 {6u, 1u, P16_2, P16_2_TCPWM1_LINE513}, 1397 {4u, 62u, P16_3, P16_3_TCPWM1_LINE62}, 1398 {4u, 68u, P16_4, P16_4_TCPWM1_LINE68}, 1399 {4u, 67u, P16_5, P16_5_TCPWM1_LINE67}, 1400 {4u, 66u, P16_6, P16_6_TCPWM1_LINE66}, 1401 {4u, 65u, P16_7, P16_7_TCPWM1_LINE65}, 1402 {4u, 61u, P17_0, P17_0_TCPWM1_LINE61}, 1403 {4u, 60u, P17_1, P17_1_TCPWM1_LINE60}, 1404 {4u, 59u, P17_2, P17_2_TCPWM1_LINE59}, 1405 {4u, 58u, P17_3, P17_3_TCPWM1_LINE58}, 1406 {6u, 3u, P17_3, P17_3_TCPWM1_LINE515}, 1407 {4u, 57u, P17_4, P17_4_TCPWM1_LINE57}, 1408 {4u, 56u, P17_5, P17_5_TCPWM1_LINE56}, 1409 {6u, 2u, P17_5, P17_5_TCPWM1_LINE514}, 1410 {5u, 4u, P17_6, P17_6_TCPWM1_LINE260}, 1411 {5u, 5u, P17_7, P17_7_TCPWM1_LINE261}, 1412 {5u, 6u, P18_0, P18_0_TCPWM1_LINE262}, 1413 {6u, 0u, P18_0, P18_0_TCPWM1_LINE512}, 1414 {5u, 7u, P18_1, P18_1_TCPWM1_LINE263}, 1415 {4u, 55u, P18_2, P18_2_TCPWM1_LINE55}, 1416 {6u, 1u, P18_2, P18_2_TCPWM1_LINE513}, 1417 {4u, 54u, P18_3, P18_3_TCPWM1_LINE54}, 1418 {1u, 2u, P18_4, P18_4_TCPWM0_LINE258}, 1419 {4u, 53u, P18_4, P18_4_TCPWM1_LINE53}, 1420 {6u, 2u, P18_4, P18_4_TCPWM1_LINE514}, 1421 {4u, 52u, P18_5, P18_5_TCPWM1_LINE52}, 1422 {4u, 51u, P18_6, P18_6_TCPWM1_LINE51}, 1423 {6u, 3u, P18_6, P18_6_TCPWM1_LINE515}, 1424 {4u, 50u, P18_7, P18_7_TCPWM1_LINE50}, 1425 {5u, 3u, P19_0, P19_0_TCPWM1_LINE259}, 1426 {4u, 26u, P19_1, P19_1_TCPWM1_LINE26}, 1427 {4u, 27u, P19_2, P19_2_TCPWM1_LINE27}, 1428 {4u, 28u, P19_3, P19_3_TCPWM1_LINE28}, 1429 {4u, 29u, P19_4, P19_4_TCPWM1_LINE29}, 1430 {4u, 30u, P20_0, P20_0_TCPWM1_LINE30}, 1431 {4u, 49u, P20_1, P20_1_TCPWM1_LINE49}, 1432 {4u, 48u, P20_2, P20_2_TCPWM1_LINE48}, 1433 {4u, 47u, P20_3, P20_3_TCPWM1_LINE47}, 1434 {4u, 46u, P20_4, P20_4_TCPWM1_LINE46}, 1435 {4u, 45u, P20_5, P20_5_TCPWM1_LINE45}, 1436 {4u, 44u, P20_6, P20_6_TCPWM1_LINE44}, 1437 {4u, 43u, P20_7, P20_7_TCPWM1_LINE43}, 1438 {4u, 42u, P21_0, P21_0_TCPWM1_LINE42}, 1439 {4u, 41u, P21_1, P21_1_TCPWM1_LINE41}, 1440 {4u, 40u, P21_2, P21_2_TCPWM1_LINE40}, 1441 {4u, 39u, P21_3, P21_3_TCPWM1_LINE39}, 1442 {4u, 38u, P21_4, P21_4_TCPWM1_LINE38}, 1443 {4u, 34u, P21_5, P21_5_TCPWM1_LINE34}, 1444 {4u, 37u, P21_5, P21_5_TCPWM1_LINE37}, 1445 {4u, 36u, P21_6, P21_6_TCPWM1_LINE36}, 1446 {4u, 35u, P21_7, P21_7_TCPWM1_LINE35}, 1447 {4u, 33u, P22_1, P22_1_TCPWM1_LINE33}, 1448 {4u, 32u, P22_2, P22_2_TCPWM1_LINE32}, 1449 {4u, 31u, P22_3, P22_3_TCPWM1_LINE31}, 1450 {4u, 30u, P22_4, P22_4_TCPWM1_LINE30}, 1451 {4u, 29u, P22_5, P22_5_TCPWM1_LINE29}, 1452 {6u, 8u, P22_5, P22_5_TCPWM1_LINE520}, 1453 {4u, 28u, P22_6, P22_6_TCPWM1_LINE28}, 1454 {4u, 27u, P22_7, P22_7_TCPWM1_LINE27}, 1455 {5u, 8u, P23_0, P23_0_TCPWM1_LINE264}, 1456 {5u, 9u, P23_1, P23_1_TCPWM1_LINE265}, 1457 {5u, 10u, P23_2, P23_2_TCPWM1_LINE266}, 1458 {5u, 11u, P23_3, P23_3_TCPWM1_LINE267}, 1459 {4u, 25u, P23_4, P23_4_TCPWM1_LINE25}, 1460 {6u, 9u, P23_4, P23_4_TCPWM1_LINE521}, 1461 {4u, 24u, P23_5, P23_5_TCPWM1_LINE24}, 1462 {4u, 23u, P23_6, P23_6_TCPWM1_LINE23}, 1463 {4u, 22u, P23_7, P23_7_TCPWM1_LINE22}, 1464 {4u, 63u, P28_0, P28_0_TCPWM1_LINE63}, 1465 {6u, 12u, P28_0, P28_0_TCPWM1_LINE524}, 1466 {4u, 64u, P28_1, P28_1_TCPWM1_LINE64}, 1467 {4u, 65u, P28_2, P28_2_TCPWM1_LINE65}, 1468 {4u, 66u, P28_3, P28_3_TCPWM1_LINE66}, 1469 {4u, 67u, P28_4, P28_4_TCPWM1_LINE67}, 1470 {4u, 68u, P28_5, P28_5_TCPWM1_LINE68}, 1471 {4u, 69u, P28_6, P28_6_TCPWM1_LINE69}, 1472 {4u, 70u, P28_7, P28_7_TCPWM1_LINE70}, 1473 {4u, 76u, P29_0, P29_0_TCPWM1_LINE76}, 1474 {4u, 77u, P29_1, P29_1_TCPWM1_LINE77}, 1475 {4u, 78u, P29_2, P29_2_TCPWM1_LINE78}, 1476 {4u, 79u, P29_3, P29_3_TCPWM1_LINE79}, 1477 {4u, 80u, P29_4, P29_4_TCPWM1_LINE80}, 1478 {4u, 81u, P29_5, P29_5_TCPWM1_LINE81}, 1479 {4u, 82u, P29_6, P29_6_TCPWM1_LINE82}, 1480 {4u, 83u, P29_7, P29_7_TCPWM1_LINE83}, 1481 {4u, 83u, P30_0, P30_0_TCPWM1_LINE83}, 1482 {4u, 82u, P30_1, P30_1_TCPWM1_LINE82}, 1483 {4u, 81u, P30_2, P30_2_TCPWM1_LINE81}, 1484 {4u, 80u, P30_3, P30_3_TCPWM1_LINE80}, 1485 {4u, 79u, P31_0, P31_0_TCPWM1_LINE79}, 1486 {4u, 78u, P31_1, P31_1_TCPWM1_LINE78}, 1487 {4u, 77u, P31_2, P31_2_TCPWM1_LINE77}, 1488 {4u, 76u, P32_0, P32_0_TCPWM1_LINE76}, 1489 {4u, 75u, P32_1, P32_1_TCPWM1_LINE75}, 1490 {4u, 74u, P32_2, P32_2_TCPWM1_LINE74}, 1491 {4u, 73u, P32_3, P32_3_TCPWM1_LINE73}, 1492 {4u, 72u, P32_4, P32_4_TCPWM1_LINE72}, 1493 {4u, 71u, P32_5, P32_5_TCPWM1_LINE71}, 1494 {4u, 70u, P32_6, P32_6_TCPWM1_LINE70}, 1495 {4u, 69u, P32_7, P32_7_TCPWM1_LINE69}, 1496 }; 1497 1498 /* Connections for: tcpwm_line_compl */ 1499 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[227] = { 1500 {4u, 22u, P0_0, P0_0_TCPWM1_LINE_COMPL22}, 1501 {2u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL512}, 1502 {4u, 18u, P0_1, P0_1_TCPWM1_LINE_COMPL18}, 1503 {4u, 17u, P0_2, P0_2_TCPWM1_LINE_COMPL17}, 1504 {4u, 14u, P0_3, P0_3_TCPWM1_LINE_COMPL14}, 1505 {4u, 13u, P1_0, P1_0_TCPWM1_LINE_COMPL13}, 1506 {4u, 12u, P1_1, P1_1_TCPWM1_LINE_COMPL12}, 1507 {4u, 11u, P1_2, P1_2_TCPWM1_LINE_COMPL11}, 1508 {4u, 10u, P1_3, P1_3_TCPWM1_LINE_COMPL10}, 1509 {4u, 70u, P1_4, P1_4_TCPWM1_LINE_COMPL70}, 1510 {4u, 8u, P2_0, P2_0_TCPWM1_LINE_COMPL8}, 1511 {4u, 7u, P2_1, P2_1_TCPWM1_LINE_COMPL7}, 1512 {4u, 6u, P2_2, P2_2_TCPWM1_LINE_COMPL6}, 1513 {4u, 5u, P2_3, P2_3_TCPWM1_LINE_COMPL5}, 1514 {4u, 4u, P2_4, P2_4_TCPWM1_LINE_COMPL4}, 1515 {6u, 4u, P2_4, P2_4_TCPWM1_LINE_COMPL516}, 1516 {4u, 3u, P2_5, P2_5_TCPWM1_LINE_COMPL3}, 1517 {6u, 5u, P2_5, P2_5_TCPWM1_LINE_COMPL517}, 1518 {4u, 71u, P2_6, P2_6_TCPWM1_LINE_COMPL71}, 1519 {4u, 72u, P2_7, P2_7_TCPWM1_LINE_COMPL72}, 1520 {4u, 2u, P3_0, P3_0_TCPWM1_LINE_COMPL2}, 1521 {6u, 6u, P3_0, P3_0_TCPWM1_LINE_COMPL518}, 1522 {4u, 1u, P3_1, P3_1_TCPWM1_LINE_COMPL1}, 1523 {6u, 7u, P3_1, P3_1_TCPWM1_LINE_COMPL519}, 1524 {4u, 0u, P3_2, P3_2_TCPWM1_LINE_COMPL0}, 1525 {5u, 3u, P3_3, P3_3_TCPWM1_LINE_COMPL259}, 1526 {5u, 2u, P3_4, P3_4_TCPWM1_LINE_COMPL258}, 1527 {5u, 1u, P3_5, P3_5_TCPWM1_LINE_COMPL257}, 1528 {4u, 73u, P3_6, P3_6_TCPWM1_LINE_COMPL73}, 1529 {4u, 74u, P3_7, P3_7_TCPWM1_LINE_COMPL74}, 1530 {5u, 0u, P4_0, P4_0_TCPWM1_LINE_COMPL256}, 1531 {4u, 4u, P4_1, P4_1_TCPWM1_LINE_COMPL4}, 1532 {4u, 5u, P4_2, P4_2_TCPWM1_LINE_COMPL5}, 1533 {4u, 6u, P4_3, P4_3_TCPWM1_LINE_COMPL6}, 1534 {4u, 7u, P4_4, P4_4_TCPWM1_LINE_COMPL7}, 1535 {4u, 8u, P5_0, P5_0_TCPWM1_LINE_COMPL8}, 1536 {1u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL256}, 1537 {4u, 9u, P5_1, P5_1_TCPWM1_LINE_COMPL9}, 1538 {6u, 10u, P5_1, P5_1_TCPWM1_LINE_COMPL522}, 1539 {4u, 10u, P5_2, P5_2_TCPWM1_LINE_COMPL10}, 1540 {4u, 11u, P5_3, P5_3_TCPWM1_LINE_COMPL11}, 1541 {4u, 12u, P5_4, P5_4_TCPWM1_LINE_COMPL12}, 1542 {4u, 13u, P5_5, P5_5_TCPWM1_LINE_COMPL13}, 1543 {6u, 11u, P5_5, P5_5_TCPWM1_LINE_COMPL523}, 1544 {4u, 14u, P6_0, P6_0_TCPWM1_LINE_COMPL14}, 1545 {5u, 0u, P6_1, P6_1_TCPWM1_LINE_COMPL256}, 1546 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 1547 {4u, 0u, P6_2, P6_2_TCPWM1_LINE_COMPL0}, 1548 {5u, 1u, P6_3, P6_3_TCPWM1_LINE_COMPL257}, 1549 {6u, 12u, P6_3, P6_3_TCPWM1_LINE_COMPL524}, 1550 {4u, 1u, P6_4, P6_4_TCPWM1_LINE_COMPL1}, 1551 {5u, 2u, P6_5, P6_5_TCPWM1_LINE_COMPL258}, 1552 {4u, 2u, P6_6, P6_6_TCPWM1_LINE_COMPL2}, 1553 {5u, 3u, P6_7, P6_7_TCPWM1_LINE_COMPL259}, 1554 {4u, 3u, P7_0, P7_0_TCPWM1_LINE_COMPL3}, 1555 {5u, 4u, P7_1, P7_1_TCPWM1_LINE_COMPL260}, 1556 {0u, 1u, P7_2, P7_2_TCPWM0_LINE_COMPL1}, 1557 {4u, 15u, P7_2, P7_2_TCPWM1_LINE_COMPL15}, 1558 {5u, 5u, P7_3, P7_3_TCPWM1_LINE_COMPL261}, 1559 {4u, 16u, P7_4, P7_4_TCPWM1_LINE_COMPL16}, 1560 {5u, 6u, P7_5, P7_5_TCPWM1_LINE_COMPL262}, 1561 {4u, 17u, P7_6, P7_6_TCPWM1_LINE_COMPL17}, 1562 {5u, 7u, P7_7, P7_7_TCPWM1_LINE_COMPL263}, 1563 {2u, 2u, P8_0, P8_0_TCPWM0_LINE_COMPL514}, 1564 {4u, 18u, P8_0, P8_0_TCPWM1_LINE_COMPL18}, 1565 {4u, 19u, P8_1, P8_1_TCPWM1_LINE_COMPL19}, 1566 {6u, 8u, P8_1, P8_1_TCPWM1_LINE_COMPL520}, 1567 {4u, 20u, P8_2, P8_2_TCPWM1_LINE_COMPL20}, 1568 {4u, 21u, P8_3, P8_3_TCPWM1_LINE_COMPL21}, 1569 {4u, 22u, P8_4, P8_4_TCPWM1_LINE_COMPL22}, 1570 {4u, 23u, P9_0, P9_0_TCPWM1_LINE_COMPL23}, 1571 {4u, 24u, P9_1, P9_1_TCPWM1_LINE_COMPL24}, 1572 {6u, 9u, P9_1, P9_1_TCPWM1_LINE_COMPL521}, 1573 {4u, 25u, P9_2, P9_2_TCPWM1_LINE_COMPL25}, 1574 {4u, 26u, P9_3, P9_3_TCPWM1_LINE_COMPL26}, 1575 {4u, 27u, P10_0, P10_0_TCPWM1_LINE_COMPL27}, 1576 {4u, 28u, P10_1, P10_1_TCPWM1_LINE_COMPL28}, 1577 {6u, 10u, P10_1, P10_1_TCPWM1_LINE_COMPL522}, 1578 {4u, 29u, P10_2, P10_2_TCPWM1_LINE_COMPL29}, 1579 {4u, 30u, P10_3, P10_3_TCPWM1_LINE_COMPL30}, 1580 {4u, 31u, P10_4, P10_4_TCPWM1_LINE_COMPL31}, 1581 {4u, 32u, P10_5, P10_5_TCPWM1_LINE_COMPL32}, 1582 {6u, 11u, P10_5, P10_5_TCPWM1_LINE_COMPL523}, 1583 {4u, 33u, P10_6, P10_6_TCPWM1_LINE_COMPL33}, 1584 {4u, 34u, P10_7, P10_7_TCPWM1_LINE_COMPL34}, 1585 {4u, 62u, P11_0, P11_0_TCPWM1_LINE_COMPL62}, 1586 {4u, 61u, P11_1, P11_1_TCPWM1_LINE_COMPL61}, 1587 {4u, 60u, P11_2, P11_2_TCPWM1_LINE_COMPL60}, 1588 {4u, 35u, P12_0, P12_0_TCPWM1_LINE_COMPL35}, 1589 {2u, 1u, P12_1, P12_1_TCPWM0_LINE_COMPL513}, 1590 {4u, 36u, P12_1, P12_1_TCPWM1_LINE_COMPL36}, 1591 {4u, 37u, P12_2, P12_2_TCPWM1_LINE_COMPL37}, 1592 {4u, 38u, P12_3, P12_3_TCPWM1_LINE_COMPL38}, 1593 {4u, 39u, P12_4, P12_4_TCPWM1_LINE_COMPL39}, 1594 {4u, 40u, P12_5, P12_5_TCPWM1_LINE_COMPL40}, 1595 {4u, 41u, P12_6, P12_6_TCPWM1_LINE_COMPL41}, 1596 {4u, 42u, P12_7, P12_7_TCPWM1_LINE_COMPL42}, 1597 {4u, 43u, P13_0, P13_0_TCPWM1_LINE_COMPL43}, 1598 {0u, 2u, P13_1, P13_1_TCPWM0_LINE_COMPL2}, 1599 {5u, 8u, P13_1, P13_1_TCPWM1_LINE_COMPL264}, 1600 {4u, 44u, P13_2, P13_2_TCPWM1_LINE_COMPL44}, 1601 {5u, 9u, P13_3, P13_3_TCPWM1_LINE_COMPL265}, 1602 {4u, 45u, P13_4, P13_4_TCPWM1_LINE_COMPL45}, 1603 {5u, 10u, P13_5, P13_5_TCPWM1_LINE_COMPL266}, 1604 {6u, 4u, P13_5, P13_5_TCPWM1_LINE_COMPL516}, 1605 {4u, 46u, P13_6, P13_6_TCPWM1_LINE_COMPL46}, 1606 {5u, 11u, P13_7, P13_7_TCPWM1_LINE_COMPL267}, 1607 {6u, 5u, P13_7, P13_7_TCPWM1_LINE_COMPL517}, 1608 {4u, 47u, P14_0, P14_0_TCPWM1_LINE_COMPL47}, 1609 {1u, 1u, P14_1, P14_1_TCPWM0_LINE_COMPL257}, 1610 {4u, 48u, P14_1, P14_1_TCPWM1_LINE_COMPL48}, 1611 {6u, 6u, P14_1, P14_1_TCPWM1_LINE_COMPL518}, 1612 {4u, 49u, P14_2, P14_2_TCPWM1_LINE_COMPL49}, 1613 {4u, 50u, P14_3, P14_3_TCPWM1_LINE_COMPL50}, 1614 {6u, 7u, P14_3, P14_3_TCPWM1_LINE_COMPL519}, 1615 {4u, 51u, P14_4, P14_4_TCPWM1_LINE_COMPL51}, 1616 {4u, 52u, P14_5, P14_5_TCPWM1_LINE_COMPL52}, 1617 {4u, 53u, P14_6, P14_6_TCPWM1_LINE_COMPL53}, 1618 {4u, 54u, P14_7, P14_7_TCPWM1_LINE_COMPL54}, 1619 {4u, 55u, P15_0, P15_0_TCPWM1_LINE_COMPL55}, 1620 {4u, 56u, P15_1, P15_1_TCPWM1_LINE_COMPL56}, 1621 {4u, 57u, P15_2, P15_2_TCPWM1_LINE_COMPL57}, 1622 {4u, 58u, P15_3, P15_3_TCPWM1_LINE_COMPL58}, 1623 {4u, 59u, P16_0, P16_0_TCPWM1_LINE_COMPL59}, 1624 {4u, 60u, P16_1, P16_1_TCPWM1_LINE_COMPL60}, 1625 {6u, 0u, P16_1, P16_1_TCPWM1_LINE_COMPL512}, 1626 {4u, 61u, P16_2, P16_2_TCPWM1_LINE_COMPL61}, 1627 {4u, 62u, P16_3, P16_3_TCPWM1_LINE_COMPL62}, 1628 {6u, 1u, P16_3, P16_3_TCPWM1_LINE_COMPL513}, 1629 {4u, 69u, P16_4, P16_4_TCPWM1_LINE_COMPL69}, 1630 {4u, 68u, P16_5, P16_5_TCPWM1_LINE_COMPL68}, 1631 {4u, 67u, P16_6, P16_6_TCPWM1_LINE_COMPL67}, 1632 {4u, 66u, P16_7, P16_7_TCPWM1_LINE_COMPL66}, 1633 {4u, 62u, P17_0, P17_0_TCPWM1_LINE_COMPL62}, 1634 {4u, 61u, P17_1, P17_1_TCPWM1_LINE_COMPL61}, 1635 {4u, 60u, P17_2, P17_2_TCPWM1_LINE_COMPL60}, 1636 {4u, 59u, P17_3, P17_3_TCPWM1_LINE_COMPL59}, 1637 {4u, 58u, P17_4, P17_4_TCPWM1_LINE_COMPL58}, 1638 {6u, 3u, P17_4, P17_4_TCPWM1_LINE_COMPL515}, 1639 {4u, 57u, P17_5, P17_5_TCPWM1_LINE_COMPL57}, 1640 {4u, 56u, P17_6, P17_6_TCPWM1_LINE_COMPL56}, 1641 {6u, 2u, P17_6, P17_6_TCPWM1_LINE_COMPL514}, 1642 {5u, 4u, P17_7, P17_7_TCPWM1_LINE_COMPL260}, 1643 {5u, 5u, P18_0, P18_0_TCPWM1_LINE_COMPL261}, 1644 {5u, 6u, P18_1, P18_1_TCPWM1_LINE_COMPL262}, 1645 {6u, 0u, P18_1, P18_1_TCPWM1_LINE_COMPL512}, 1646 {5u, 7u, P18_2, P18_2_TCPWM1_LINE_COMPL263}, 1647 {4u, 55u, P18_3, P18_3_TCPWM1_LINE_COMPL55}, 1648 {6u, 1u, P18_3, P18_3_TCPWM1_LINE_COMPL513}, 1649 {4u, 54u, P18_4, P18_4_TCPWM1_LINE_COMPL54}, 1650 {1u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL258}, 1651 {4u, 53u, P18_5, P18_5_TCPWM1_LINE_COMPL53}, 1652 {6u, 2u, P18_5, P18_5_TCPWM1_LINE_COMPL514}, 1653 {4u, 52u, P18_6, P18_6_TCPWM1_LINE_COMPL52}, 1654 {4u, 51u, P18_7, P18_7_TCPWM1_LINE_COMPL51}, 1655 {6u, 3u, P18_7, P18_7_TCPWM1_LINE_COMPL515}, 1656 {4u, 50u, P19_0, P19_0_TCPWM1_LINE_COMPL50}, 1657 {5u, 3u, P19_1, P19_1_TCPWM1_LINE_COMPL259}, 1658 {4u, 26u, P19_2, P19_2_TCPWM1_LINE_COMPL26}, 1659 {4u, 27u, P19_3, P19_3_TCPWM1_LINE_COMPL27}, 1660 {4u, 28u, P19_4, P19_4_TCPWM1_LINE_COMPL28}, 1661 {4u, 29u, P20_0, P20_0_TCPWM1_LINE_COMPL29}, 1662 {4u, 30u, P20_1, P20_1_TCPWM1_LINE_COMPL30}, 1663 {4u, 49u, P20_2, P20_2_TCPWM1_LINE_COMPL49}, 1664 {4u, 48u, P20_3, P20_3_TCPWM1_LINE_COMPL48}, 1665 {4u, 47u, P20_4, P20_4_TCPWM1_LINE_COMPL47}, 1666 {4u, 46u, P20_5, P20_5_TCPWM1_LINE_COMPL46}, 1667 {4u, 45u, P20_6, P20_6_TCPWM1_LINE_COMPL45}, 1668 {4u, 44u, P20_7, P20_7_TCPWM1_LINE_COMPL44}, 1669 {4u, 43u, P21_0, P21_0_TCPWM1_LINE_COMPL43}, 1670 {4u, 42u, P21_1, P21_1_TCPWM1_LINE_COMPL42}, 1671 {4u, 41u, P21_2, P21_2_TCPWM1_LINE_COMPL41}, 1672 {4u, 40u, P21_3, P21_3_TCPWM1_LINE_COMPL40}, 1673 {4u, 39u, P21_4, P21_4_TCPWM1_LINE_COMPL39}, 1674 {4u, 35u, P21_5, P21_5_TCPWM1_LINE_COMPL35}, 1675 {4u, 38u, P21_5, P21_5_TCPWM1_LINE_COMPL38}, 1676 {4u, 37u, P21_6, P21_6_TCPWM1_LINE_COMPL37}, 1677 {4u, 36u, P21_7, P21_7_TCPWM1_LINE_COMPL36}, 1678 {4u, 34u, P22_1, P22_1_TCPWM1_LINE_COMPL34}, 1679 {4u, 33u, P22_2, P22_2_TCPWM1_LINE_COMPL33}, 1680 {4u, 32u, P22_3, P22_3_TCPWM1_LINE_COMPL32}, 1681 {4u, 31u, P22_4, P22_4_TCPWM1_LINE_COMPL31}, 1682 {4u, 30u, P22_5, P22_5_TCPWM1_LINE_COMPL30}, 1683 {4u, 29u, P22_6, P22_6_TCPWM1_LINE_COMPL29}, 1684 {6u, 8u, P22_6, P22_6_TCPWM1_LINE_COMPL520}, 1685 {4u, 28u, P22_7, P22_7_TCPWM1_LINE_COMPL28}, 1686 {4u, 27u, P23_0, P23_0_TCPWM1_LINE_COMPL27}, 1687 {5u, 8u, P23_1, P23_1_TCPWM1_LINE_COMPL264}, 1688 {5u, 9u, P23_2, P23_2_TCPWM1_LINE_COMPL265}, 1689 {5u, 10u, P23_3, P23_3_TCPWM1_LINE_COMPL266}, 1690 {5u, 11u, P23_4, P23_4_TCPWM1_LINE_COMPL267}, 1691 {4u, 25u, P23_5, P23_5_TCPWM1_LINE_COMPL25}, 1692 {6u, 9u, P23_5, P23_5_TCPWM1_LINE_COMPL521}, 1693 {4u, 24u, P23_6, P23_6_TCPWM1_LINE_COMPL24}, 1694 {4u, 23u, P23_7, P23_7_TCPWM1_LINE_COMPL23}, 1695 {4u, 65u, P28_0, P28_0_TCPWM1_LINE_COMPL65}, 1696 {4u, 63u, P28_1, P28_1_TCPWM1_LINE_COMPL63}, 1697 {6u, 12u, P28_1, P28_1_TCPWM1_LINE_COMPL524}, 1698 {4u, 64u, P28_2, P28_2_TCPWM1_LINE_COMPL64}, 1699 {4u, 65u, P28_3, P28_3_TCPWM1_LINE_COMPL65}, 1700 {4u, 66u, P28_4, P28_4_TCPWM1_LINE_COMPL66}, 1701 {4u, 67u, P28_5, P28_5_TCPWM1_LINE_COMPL67}, 1702 {4u, 68u, P28_6, P28_6_TCPWM1_LINE_COMPL68}, 1703 {4u, 69u, P28_7, P28_7_TCPWM1_LINE_COMPL69}, 1704 {4u, 75u, P29_0, P29_0_TCPWM1_LINE_COMPL75}, 1705 {4u, 76u, P29_1, P29_1_TCPWM1_LINE_COMPL76}, 1706 {4u, 77u, P29_2, P29_2_TCPWM1_LINE_COMPL77}, 1707 {4u, 78u, P29_3, P29_3_TCPWM1_LINE_COMPL78}, 1708 {4u, 79u, P29_4, P29_4_TCPWM1_LINE_COMPL79}, 1709 {4u, 80u, P29_5, P29_5_TCPWM1_LINE_COMPL80}, 1710 {4u, 81u, P29_6, P29_6_TCPWM1_LINE_COMPL81}, 1711 {4u, 82u, P29_7, P29_7_TCPWM1_LINE_COMPL82}, 1712 {4u, 83u, P30_0, P30_0_TCPWM1_LINE_COMPL83}, 1713 {4u, 83u, P30_1, P30_1_TCPWM1_LINE_COMPL83}, 1714 {4u, 82u, P30_2, P30_2_TCPWM1_LINE_COMPL82}, 1715 {4u, 81u, P30_3, P30_3_TCPWM1_LINE_COMPL81}, 1716 {4u, 80u, P31_0, P31_0_TCPWM1_LINE_COMPL80}, 1717 {4u, 79u, P31_1, P31_1_TCPWM1_LINE_COMPL79}, 1718 {4u, 78u, P31_2, P31_2_TCPWM1_LINE_COMPL78}, 1719 {4u, 77u, P32_0, P32_0_TCPWM1_LINE_COMPL77}, 1720 {4u, 76u, P32_1, P32_1_TCPWM1_LINE_COMPL76}, 1721 {4u, 75u, P32_2, P32_2_TCPWM1_LINE_COMPL75}, 1722 {4u, 74u, P32_3, P32_3_TCPWM1_LINE_COMPL74}, 1723 {4u, 73u, P32_4, P32_4_TCPWM1_LINE_COMPL73}, 1724 {4u, 72u, P32_5, P32_5_TCPWM1_LINE_COMPL72}, 1725 {4u, 71u, P32_6, P32_6_TCPWM1_LINE_COMPL71}, 1726 {4u, 70u, P32_7, P32_7_TCPWM1_LINE_COMPL70}, 1727 }; 1728 1729 /* Connections for: tcpwm_tr_one_cnt_in */ 1730 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[446] = { 1731 {4u, 54u, P0_0, P0_0_TCPWM1_TR_ONE_CNT_IN54}, 1732 {4u, 67u, P0_0, P0_0_TCPWM1_TR_ONE_CNT_IN67}, 1733 {4u, 51u, P0_1, P0_1_TCPWM1_TR_ONE_CNT_IN51}, 1734 {4u, 55u, P0_1, P0_1_TCPWM1_TR_ONE_CNT_IN55}, 1735 {4u, 42u, P0_2, P0_2_TCPWM1_TR_ONE_CNT_IN42}, 1736 {4u, 52u, P0_2, P0_2_TCPWM1_TR_ONE_CNT_IN52}, 1737 {6u, 0u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN1536}, 1738 {4u, 39u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN39}, 1739 {4u, 43u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN43}, 1740 {6u, 1u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN1537}, 1741 {4u, 36u, P1_0, P1_0_TCPWM1_TR_ONE_CNT_IN36}, 1742 {4u, 40u, P1_0, P1_0_TCPWM1_TR_ONE_CNT_IN40}, 1743 {4u, 33u, P1_1, P1_1_TCPWM1_TR_ONE_CNT_IN33}, 1744 {4u, 37u, P1_1, P1_1_TCPWM1_TR_ONE_CNT_IN37}, 1745 {4u, 30u, P1_2, P1_2_TCPWM1_TR_ONE_CNT_IN30}, 1746 {4u, 34u, P1_2, P1_2_TCPWM1_TR_ONE_CNT_IN34}, 1747 {4u, 24u, P1_3, P1_3_TCPWM1_TR_ONE_CNT_IN24}, 1748 {4u, 31u, P1_3, P1_3_TCPWM1_TR_ONE_CNT_IN31}, 1749 {4u, 211u, P1_4, P1_4_TCPWM1_TR_ONE_CNT_IN211}, 1750 {4u, 213u, P1_4, P1_4_TCPWM1_TR_ONE_CNT_IN213}, 1751 {4u, 21u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN21}, 1752 {4u, 25u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN25}, 1753 {10u, 12u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN1548}, 1754 {4u, 18u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN18}, 1755 {4u, 22u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN22}, 1756 {10u, 15u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN1551}, 1757 {4u, 15u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN15}, 1758 {4u, 19u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN19}, 1759 {10u, 18u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN1554}, 1760 {4u, 12u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN12}, 1761 {4u, 16u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN16}, 1762 {10u, 21u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN1557}, 1763 {4u, 9u, P2_4, P2_4_TCPWM1_TR_ONE_CNT_IN9}, 1764 {4u, 13u, P2_4, P2_4_TCPWM1_TR_ONE_CNT_IN13}, 1765 {4u, 6u, P2_5, P2_5_TCPWM1_TR_ONE_CNT_IN6}, 1766 {4u, 10u, P2_5, P2_5_TCPWM1_TR_ONE_CNT_IN10}, 1767 {4u, 214u, P2_6, P2_6_TCPWM1_TR_ONE_CNT_IN214}, 1768 {4u, 216u, P2_6, P2_6_TCPWM1_TR_ONE_CNT_IN216}, 1769 {4u, 217u, P2_7, P2_7_TCPWM1_TR_ONE_CNT_IN217}, 1770 {4u, 219u, P2_7, P2_7_TCPWM1_TR_ONE_CNT_IN219}, 1771 {4u, 3u, P3_0, P3_0_TCPWM1_TR_ONE_CNT_IN3}, 1772 {4u, 7u, P3_0, P3_0_TCPWM1_TR_ONE_CNT_IN7}, 1773 {4u, 0u, P3_1, P3_1_TCPWM1_TR_ONE_CNT_IN0}, 1774 {4u, 4u, P3_1, P3_1_TCPWM1_TR_ONE_CNT_IN4}, 1775 {4u, 1u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN1}, 1776 {7u, 9u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN777}, 1777 {10u, 13u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN1549}, 1778 {7u, 6u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN774}, 1779 {7u, 10u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN778}, 1780 {10u, 16u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN1552}, 1781 {7u, 3u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN771}, 1782 {7u, 7u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN775}, 1783 {10u, 19u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN1555}, 1784 {7u, 0u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN768}, 1785 {7u, 4u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN772}, 1786 {10u, 22u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN1558}, 1787 {4u, 220u, P3_6, P3_6_TCPWM1_TR_ONE_CNT_IN220}, 1788 {4u, 222u, P3_6, P3_6_TCPWM1_TR_ONE_CNT_IN222}, 1789 {4u, 223u, P3_7, P3_7_TCPWM1_TR_ONE_CNT_IN223}, 1790 {4u, 225u, P3_7, P3_7_TCPWM1_TR_ONE_CNT_IN225}, 1791 {4u, 12u, P4_0, P4_0_TCPWM1_TR_ONE_CNT_IN12}, 1792 {7u, 1u, P4_0, P4_0_TCPWM1_TR_ONE_CNT_IN769}, 1793 {4u, 13u, P4_1, P4_1_TCPWM1_TR_ONE_CNT_IN13}, 1794 {4u, 15u, P4_1, P4_1_TCPWM1_TR_ONE_CNT_IN15}, 1795 {4u, 16u, P4_2, P4_2_TCPWM1_TR_ONE_CNT_IN16}, 1796 {4u, 18u, P4_2, P4_2_TCPWM1_TR_ONE_CNT_IN18}, 1797 {4u, 19u, P4_3, P4_3_TCPWM1_TR_ONE_CNT_IN19}, 1798 {4u, 21u, P4_3, P4_3_TCPWM1_TR_ONE_CNT_IN21}, 1799 {4u, 22u, P4_4, P4_4_TCPWM1_TR_ONE_CNT_IN22}, 1800 {4u, 24u, P4_4, P4_4_TCPWM1_TR_ONE_CNT_IN24}, 1801 {4u, 25u, P5_0, P5_0_TCPWM1_TR_ONE_CNT_IN25}, 1802 {4u, 27u, P5_0, P5_0_TCPWM1_TR_ONE_CNT_IN27}, 1803 {4u, 28u, P5_1, P5_1_TCPWM1_TR_ONE_CNT_IN28}, 1804 {4u, 30u, P5_1, P5_1_TCPWM1_TR_ONE_CNT_IN30}, 1805 {3u, 0u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN768}, 1806 {4u, 31u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN31}, 1807 {4u, 33u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN33}, 1808 {10u, 30u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN1566}, 1809 {3u, 1u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN769}, 1810 {4u, 34u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN34}, 1811 {4u, 36u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN36}, 1812 {10u, 31u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN1567}, 1813 {4u, 37u, P5_4, P5_4_TCPWM1_TR_ONE_CNT_IN37}, 1814 {4u, 39u, P5_4, P5_4_TCPWM1_TR_ONE_CNT_IN39}, 1815 {4u, 40u, P5_5, P5_5_TCPWM1_TR_ONE_CNT_IN40}, 1816 {4u, 42u, P5_5, P5_5_TCPWM1_TR_ONE_CNT_IN42}, 1817 {4u, 43u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN43}, 1818 {7u, 0u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN768}, 1819 {10u, 33u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN1569}, 1820 {4u, 0u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN0}, 1821 {7u, 1u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN769}, 1822 {10u, 34u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN1570}, 1823 {4u, 1u, P6_2, P6_2_TCPWM1_TR_ONE_CNT_IN1}, 1824 {7u, 3u, P6_2, P6_2_TCPWM1_TR_ONE_CNT_IN771}, 1825 {4u, 3u, P6_3, P6_3_TCPWM1_TR_ONE_CNT_IN3}, 1826 {7u, 4u, P6_3, P6_3_TCPWM1_TR_ONE_CNT_IN772}, 1827 {0u, 0u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN0}, 1828 {4u, 4u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN4}, 1829 {7u, 6u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN774}, 1830 {10u, 36u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN1572}, 1831 {0u, 1u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN1}, 1832 {4u, 6u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN6}, 1833 {7u, 7u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN775}, 1834 {10u, 37u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN1573}, 1835 {4u, 7u, P6_6, P6_6_TCPWM1_TR_ONE_CNT_IN7}, 1836 {7u, 9u, P6_6, P6_6_TCPWM1_TR_ONE_CNT_IN777}, 1837 {4u, 9u, P6_7, P6_7_TCPWM1_TR_ONE_CNT_IN9}, 1838 {7u, 10u, P6_7, P6_7_TCPWM1_TR_ONE_CNT_IN778}, 1839 {4u, 10u, P7_0, P7_0_TCPWM1_TR_ONE_CNT_IN10}, 1840 {7u, 12u, P7_0, P7_0_TCPWM1_TR_ONE_CNT_IN780}, 1841 {4u, 45u, P7_1, P7_1_TCPWM1_TR_ONE_CNT_IN45}, 1842 {7u, 13u, P7_1, P7_1_TCPWM1_TR_ONE_CNT_IN781}, 1843 {4u, 46u, P7_2, P7_2_TCPWM1_TR_ONE_CNT_IN46}, 1844 {7u, 15u, P7_2, P7_2_TCPWM1_TR_ONE_CNT_IN783}, 1845 {0u, 3u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN3}, 1846 {4u, 48u, P7_3, P7_3_TCPWM1_TR_ONE_CNT_IN48}, 1847 {7u, 16u, P7_3, P7_3_TCPWM1_TR_ONE_CNT_IN784}, 1848 {0u, 4u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN4}, 1849 {4u, 49u, P7_4, P7_4_TCPWM1_TR_ONE_CNT_IN49}, 1850 {7u, 18u, P7_4, P7_4_TCPWM1_TR_ONE_CNT_IN786}, 1851 {4u, 51u, P7_5, P7_5_TCPWM1_TR_ONE_CNT_IN51}, 1852 {7u, 19u, P7_5, P7_5_TCPWM1_TR_ONE_CNT_IN787}, 1853 {4u, 52u, P7_6, P7_6_TCPWM1_TR_ONE_CNT_IN52}, 1854 {7u, 21u, P7_6, P7_6_TCPWM1_TR_ONE_CNT_IN789}, 1855 {4u, 54u, P7_7, P7_7_TCPWM1_TR_ONE_CNT_IN54}, 1856 {7u, 22u, P7_7, P7_7_TCPWM1_TR_ONE_CNT_IN790}, 1857 {4u, 55u, P8_0, P8_0_TCPWM1_TR_ONE_CNT_IN55}, 1858 {4u, 57u, P8_0, P8_0_TCPWM1_TR_ONE_CNT_IN57}, 1859 {4u, 58u, P8_1, P8_1_TCPWM1_TR_ONE_CNT_IN58}, 1860 {4u, 60u, P8_1, P8_1_TCPWM1_TR_ONE_CNT_IN60}, 1861 {6u, 6u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN1542}, 1862 {4u, 61u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN61}, 1863 {4u, 63u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN63}, 1864 {6u, 7u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN1543}, 1865 {10u, 24u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN1560}, 1866 {4u, 64u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN64}, 1867 {4u, 66u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN66}, 1868 {10u, 25u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN1561}, 1869 {4u, 67u, P8_4, P8_4_TCPWM1_TR_ONE_CNT_IN67}, 1870 {4u, 69u, P8_4, P8_4_TCPWM1_TR_ONE_CNT_IN69}, 1871 {4u, 70u, P9_0, P9_0_TCPWM1_TR_ONE_CNT_IN70}, 1872 {4u, 72u, P9_0, P9_0_TCPWM1_TR_ONE_CNT_IN72}, 1873 {4u, 73u, P9_1, P9_1_TCPWM1_TR_ONE_CNT_IN73}, 1874 {4u, 75u, P9_1, P9_1_TCPWM1_TR_ONE_CNT_IN75}, 1875 {4u, 76u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN76}, 1876 {4u, 78u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN78}, 1877 {10u, 27u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN1563}, 1878 {4u, 79u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN79}, 1879 {4u, 81u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN81}, 1880 {10u, 28u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN1564}, 1881 {4u, 82u, P10_0, P10_0_TCPWM1_TR_ONE_CNT_IN82}, 1882 {4u, 84u, P10_0, P10_0_TCPWM1_TR_ONE_CNT_IN84}, 1883 {4u, 85u, P10_1, P10_1_TCPWM1_TR_ONE_CNT_IN85}, 1884 {4u, 87u, P10_1, P10_1_TCPWM1_TR_ONE_CNT_IN87}, 1885 {4u, 88u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN88}, 1886 {4u, 90u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN90}, 1887 {10u, 30u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN1566}, 1888 {4u, 91u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN91}, 1889 {4u, 93u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN93}, 1890 {10u, 31u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN1567}, 1891 {4u, 94u, P10_4, P10_4_TCPWM1_TR_ONE_CNT_IN94}, 1892 {4u, 96u, P10_4, P10_4_TCPWM1_TR_ONE_CNT_IN96}, 1893 {4u, 97u, P10_5, P10_5_TCPWM1_TR_ONE_CNT_IN97}, 1894 {4u, 99u, P10_5, P10_5_TCPWM1_TR_ONE_CNT_IN99}, 1895 {4u, 100u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN100}, 1896 {4u, 102u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN102}, 1897 {10u, 33u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN1569}, 1898 {4u, 103u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN103}, 1899 {4u, 105u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN105}, 1900 {10u, 34u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN1570}, 1901 {4u, 183u, P11_0, P11_0_TCPWM1_TR_ONE_CNT_IN183}, 1902 {4u, 187u, P11_0, P11_0_TCPWM1_TR_ONE_CNT_IN187}, 1903 {4u, 180u, P11_1, P11_1_TCPWM1_TR_ONE_CNT_IN180}, 1904 {4u, 184u, P11_1, P11_1_TCPWM1_TR_ONE_CNT_IN184}, 1905 {4u, 177u, P11_2, P11_2_TCPWM1_TR_ONE_CNT_IN177}, 1906 {4u, 181u, P11_2, P11_2_TCPWM1_TR_ONE_CNT_IN181}, 1907 {4u, 106u, P12_0, P12_0_TCPWM1_TR_ONE_CNT_IN106}, 1908 {4u, 108u, P12_0, P12_0_TCPWM1_TR_ONE_CNT_IN108}, 1909 {4u, 109u, P12_1, P12_1_TCPWM1_TR_ONE_CNT_IN109}, 1910 {4u, 111u, P12_1, P12_1_TCPWM1_TR_ONE_CNT_IN111}, 1911 {4u, 112u, P12_2, P12_2_TCPWM1_TR_ONE_CNT_IN112}, 1912 {4u, 114u, P12_2, P12_2_TCPWM1_TR_ONE_CNT_IN114}, 1913 {6u, 3u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN1539}, 1914 {4u, 115u, P12_3, P12_3_TCPWM1_TR_ONE_CNT_IN115}, 1915 {4u, 117u, P12_3, P12_3_TCPWM1_TR_ONE_CNT_IN117}, 1916 {6u, 4u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN1540}, 1917 {0u, 7u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN7}, 1918 {4u, 118u, P12_4, P12_4_TCPWM1_TR_ONE_CNT_IN118}, 1919 {4u, 120u, P12_4, P12_4_TCPWM1_TR_ONE_CNT_IN120}, 1920 {4u, 121u, P12_5, P12_5_TCPWM1_TR_ONE_CNT_IN121}, 1921 {4u, 123u, P12_5, P12_5_TCPWM1_TR_ONE_CNT_IN123}, 1922 {4u, 124u, P12_6, P12_6_TCPWM1_TR_ONE_CNT_IN124}, 1923 {4u, 126u, P12_6, P12_6_TCPWM1_TR_ONE_CNT_IN126}, 1924 {4u, 127u, P12_7, P12_7_TCPWM1_TR_ONE_CNT_IN127}, 1925 {4u, 129u, P12_7, P12_7_TCPWM1_TR_ONE_CNT_IN129}, 1926 {0u, 6u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN6}, 1927 {4u, 130u, P13_0, P13_0_TCPWM1_TR_ONE_CNT_IN130}, 1928 {7u, 24u, P13_0, P13_0_TCPWM1_TR_ONE_CNT_IN792}, 1929 {4u, 132u, P13_1, P13_1_TCPWM1_TR_ONE_CNT_IN132}, 1930 {7u, 25u, P13_1, P13_1_TCPWM1_TR_ONE_CNT_IN793}, 1931 {4u, 133u, P13_2, P13_2_TCPWM1_TR_ONE_CNT_IN133}, 1932 {7u, 27u, P13_2, P13_2_TCPWM1_TR_ONE_CNT_IN795}, 1933 {4u, 135u, P13_3, P13_3_TCPWM1_TR_ONE_CNT_IN135}, 1934 {7u, 28u, P13_3, P13_3_TCPWM1_TR_ONE_CNT_IN796}, 1935 {4u, 136u, P13_4, P13_4_TCPWM1_TR_ONE_CNT_IN136}, 1936 {7u, 30u, P13_4, P13_4_TCPWM1_TR_ONE_CNT_IN798}, 1937 {4u, 138u, P13_5, P13_5_TCPWM1_TR_ONE_CNT_IN138}, 1938 {7u, 31u, P13_5, P13_5_TCPWM1_TR_ONE_CNT_IN799}, 1939 {4u, 139u, P13_6, P13_6_TCPWM1_TR_ONE_CNT_IN139}, 1940 {7u, 33u, P13_6, P13_6_TCPWM1_TR_ONE_CNT_IN801}, 1941 {4u, 141u, P13_7, P13_7_TCPWM1_TR_ONE_CNT_IN141}, 1942 {7u, 34u, P13_7, P13_7_TCPWM1_TR_ONE_CNT_IN802}, 1943 {4u, 142u, P14_0, P14_0_TCPWM1_TR_ONE_CNT_IN142}, 1944 {4u, 144u, P14_0, P14_0_TCPWM1_TR_ONE_CNT_IN144}, 1945 {4u, 145u, P14_1, P14_1_TCPWM1_TR_ONE_CNT_IN145}, 1946 {4u, 147u, P14_1, P14_1_TCPWM1_TR_ONE_CNT_IN147}, 1947 {3u, 3u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN771}, 1948 {4u, 148u, P14_2, P14_2_TCPWM1_TR_ONE_CNT_IN148}, 1949 {4u, 150u, P14_2, P14_2_TCPWM1_TR_ONE_CNT_IN150}, 1950 {3u, 4u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN772}, 1951 {4u, 151u, P14_3, P14_3_TCPWM1_TR_ONE_CNT_IN151}, 1952 {4u, 153u, P14_3, P14_3_TCPWM1_TR_ONE_CNT_IN153}, 1953 {4u, 154u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN154}, 1954 {4u, 156u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN156}, 1955 {10u, 12u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN1548}, 1956 {4u, 157u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN157}, 1957 {4u, 159u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN159}, 1958 {10u, 13u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN1549}, 1959 {4u, 160u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN160}, 1960 {4u, 162u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN162}, 1961 {10u, 15u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN1551}, 1962 {4u, 163u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN163}, 1963 {4u, 165u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN165}, 1964 {10u, 16u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN1552}, 1965 {4u, 166u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN166}, 1966 {4u, 168u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN168}, 1967 {10u, 18u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN1554}, 1968 {4u, 169u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN169}, 1969 {4u, 171u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN171}, 1970 {10u, 19u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN1555}, 1971 {4u, 172u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN172}, 1972 {4u, 174u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN174}, 1973 {10u, 21u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN1557}, 1974 {4u, 175u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN175}, 1975 {4u, 177u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN177}, 1976 {10u, 22u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN1558}, 1977 {4u, 178u, P16_0, P16_0_TCPWM1_TR_ONE_CNT_IN178}, 1978 {4u, 180u, P16_0, P16_0_TCPWM1_TR_ONE_CNT_IN180}, 1979 {4u, 181u, P16_1, P16_1_TCPWM1_TR_ONE_CNT_IN181}, 1980 {4u, 183u, P16_1, P16_1_TCPWM1_TR_ONE_CNT_IN183}, 1981 {4u, 184u, P16_2, P16_2_TCPWM1_TR_ONE_CNT_IN184}, 1982 {4u, 186u, P16_2, P16_2_TCPWM1_TR_ONE_CNT_IN186}, 1983 {4u, 186u, P16_3, P16_3_TCPWM1_TR_ONE_CNT_IN186}, 1984 {4u, 187u, P16_3, P16_3_TCPWM1_TR_ONE_CNT_IN187}, 1985 {4u, 204u, P16_4, P16_4_TCPWM1_TR_ONE_CNT_IN204}, 1986 {4u, 208u, P16_4, P16_4_TCPWM1_TR_ONE_CNT_IN208}, 1987 {4u, 201u, P16_5, P16_5_TCPWM1_TR_ONE_CNT_IN201}, 1988 {4u, 205u, P16_5, P16_5_TCPWM1_TR_ONE_CNT_IN205}, 1989 {4u, 198u, P16_6, P16_6_TCPWM1_TR_ONE_CNT_IN198}, 1990 {4u, 202u, P16_6, P16_6_TCPWM1_TR_ONE_CNT_IN202}, 1991 {4u, 195u, P16_7, P16_7_TCPWM1_TR_ONE_CNT_IN195}, 1992 {4u, 199u, P16_7, P16_7_TCPWM1_TR_ONE_CNT_IN199}, 1993 {4u, 183u, P17_0, P17_0_TCPWM1_TR_ONE_CNT_IN183}, 1994 {4u, 187u, P17_0, P17_0_TCPWM1_TR_ONE_CNT_IN187}, 1995 {4u, 180u, P17_1, P17_1_TCPWM1_TR_ONE_CNT_IN180}, 1996 {4u, 184u, P17_1, P17_1_TCPWM1_TR_ONE_CNT_IN184}, 1997 {4u, 177u, P17_2, P17_2_TCPWM1_TR_ONE_CNT_IN177}, 1998 {4u, 181u, P17_2, P17_2_TCPWM1_TR_ONE_CNT_IN181}, 1999 {4u, 174u, P17_3, P17_3_TCPWM1_TR_ONE_CNT_IN174}, 2000 {4u, 178u, P17_3, P17_3_TCPWM1_TR_ONE_CNT_IN178}, 2001 {4u, 171u, P17_4, P17_4_TCPWM1_TR_ONE_CNT_IN171}, 2002 {4u, 175u, P17_4, P17_4_TCPWM1_TR_ONE_CNT_IN175}, 2003 {4u, 168u, P17_5, P17_5_TCPWM1_TR_ONE_CNT_IN168}, 2004 {4u, 172u, P17_5, P17_5_TCPWM1_TR_ONE_CNT_IN172}, 2005 {4u, 169u, P17_6, P17_6_TCPWM1_TR_ONE_CNT_IN169}, 2006 {7u, 12u, P17_6, P17_6_TCPWM1_TR_ONE_CNT_IN780}, 2007 {7u, 13u, P17_7, P17_7_TCPWM1_TR_ONE_CNT_IN781}, 2008 {7u, 15u, P17_7, P17_7_TCPWM1_TR_ONE_CNT_IN783}, 2009 {7u, 16u, P18_0, P18_0_TCPWM1_TR_ONE_CNT_IN784}, 2010 {7u, 18u, P18_0, P18_0_TCPWM1_TR_ONE_CNT_IN786}, 2011 {7u, 19u, P18_1, P18_1_TCPWM1_TR_ONE_CNT_IN787}, 2012 {7u, 21u, P18_1, P18_1_TCPWM1_TR_ONE_CNT_IN789}, 2013 {4u, 165u, P18_2, P18_2_TCPWM1_TR_ONE_CNT_IN165}, 2014 {7u, 22u, P18_2, P18_2_TCPWM1_TR_ONE_CNT_IN790}, 2015 {4u, 162u, P18_3, P18_3_TCPWM1_TR_ONE_CNT_IN162}, 2016 {4u, 166u, P18_3, P18_3_TCPWM1_TR_ONE_CNT_IN166}, 2017 {4u, 159u, P18_4, P18_4_TCPWM1_TR_ONE_CNT_IN159}, 2018 {4u, 163u, P18_4, P18_4_TCPWM1_TR_ONE_CNT_IN163}, 2019 {4u, 156u, P18_5, P18_5_TCPWM1_TR_ONE_CNT_IN156}, 2020 {4u, 160u, P18_5, P18_5_TCPWM1_TR_ONE_CNT_IN160}, 2021 {3u, 6u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN774}, 2022 {4u, 153u, P18_6, P18_6_TCPWM1_TR_ONE_CNT_IN153}, 2023 {4u, 157u, P18_6, P18_6_TCPWM1_TR_ONE_CNT_IN157}, 2024 {3u, 7u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN775}, 2025 {4u, 150u, P18_7, P18_7_TCPWM1_TR_ONE_CNT_IN150}, 2026 {4u, 154u, P18_7, P18_7_TCPWM1_TR_ONE_CNT_IN154}, 2027 {4u, 151u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN151}, 2028 {7u, 9u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN777}, 2029 {10u, 0u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN1536}, 2030 {4u, 78u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN78}, 2031 {7u, 10u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN778}, 2032 {10u, 1u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN1537}, 2033 {4u, 79u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN79}, 2034 {4u, 81u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN81}, 2035 {10u, 3u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN1539}, 2036 {4u, 82u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN82}, 2037 {4u, 84u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN84}, 2038 {10u, 4u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN1540}, 2039 {4u, 85u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN85}, 2040 {4u, 87u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN87}, 2041 {10u, 6u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN1542}, 2042 {4u, 88u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN88}, 2043 {4u, 90u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN90}, 2044 {10u, 7u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN1543}, 2045 {4u, 91u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN91}, 2046 {4u, 147u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN147}, 2047 {10u, 9u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN1545}, 2048 {4u, 144u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN144}, 2049 {4u, 148u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN148}, 2050 {10u, 10u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN1546}, 2051 {4u, 141u, P20_3, P20_3_TCPWM1_TR_ONE_CNT_IN141}, 2052 {4u, 145u, P20_3, P20_3_TCPWM1_TR_ONE_CNT_IN145}, 2053 {4u, 138u, P20_4, P20_4_TCPWM1_TR_ONE_CNT_IN138}, 2054 {4u, 142u, P20_4, P20_4_TCPWM1_TR_ONE_CNT_IN142}, 2055 {4u, 135u, P20_5, P20_5_TCPWM1_TR_ONE_CNT_IN135}, 2056 {4u, 139u, P20_5, P20_5_TCPWM1_TR_ONE_CNT_IN139}, 2057 {4u, 132u, P20_6, P20_6_TCPWM1_TR_ONE_CNT_IN132}, 2058 {4u, 136u, P20_6, P20_6_TCPWM1_TR_ONE_CNT_IN136}, 2059 {4u, 129u, P20_7, P20_7_TCPWM1_TR_ONE_CNT_IN129}, 2060 {4u, 133u, P20_7, P20_7_TCPWM1_TR_ONE_CNT_IN133}, 2061 {4u, 126u, P21_0, P21_0_TCPWM1_TR_ONE_CNT_IN126}, 2062 {4u, 130u, P21_0, P21_0_TCPWM1_TR_ONE_CNT_IN130}, 2063 {4u, 123u, P21_1, P21_1_TCPWM1_TR_ONE_CNT_IN123}, 2064 {4u, 127u, P21_1, P21_1_TCPWM1_TR_ONE_CNT_IN127}, 2065 {4u, 120u, P21_2, P21_2_TCPWM1_TR_ONE_CNT_IN120}, 2066 {4u, 124u, P21_2, P21_2_TCPWM1_TR_ONE_CNT_IN124}, 2067 {4u, 117u, P21_3, P21_3_TCPWM1_TR_ONE_CNT_IN117}, 2068 {4u, 121u, P21_3, P21_3_TCPWM1_TR_ONE_CNT_IN121}, 2069 {4u, 114u, P21_4, P21_4_TCPWM1_TR_ONE_CNT_IN114}, 2070 {4u, 118u, P21_4, P21_4_TCPWM1_TR_ONE_CNT_IN118}, 2071 {4u, 102u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN102}, 2072 {4u, 106u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN106}, 2073 {4u, 111u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN111}, 2074 {4u, 115u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN115}, 2075 {4u, 108u, P21_6, P21_6_TCPWM1_TR_ONE_CNT_IN108}, 2076 {4u, 112u, P21_6, P21_6_TCPWM1_TR_ONE_CNT_IN112}, 2077 {4u, 105u, P21_7, P21_7_TCPWM1_TR_ONE_CNT_IN105}, 2078 {4u, 109u, P21_7, P21_7_TCPWM1_TR_ONE_CNT_IN109}, 2079 {4u, 99u, P22_1, P22_1_TCPWM1_TR_ONE_CNT_IN99}, 2080 {4u, 103u, P22_1, P22_1_TCPWM1_TR_ONE_CNT_IN103}, 2081 {4u, 96u, P22_2, P22_2_TCPWM1_TR_ONE_CNT_IN96}, 2082 {4u, 100u, P22_2, P22_2_TCPWM1_TR_ONE_CNT_IN100}, 2083 {4u, 93u, P22_3, P22_3_TCPWM1_TR_ONE_CNT_IN93}, 2084 {4u, 97u, P22_3, P22_3_TCPWM1_TR_ONE_CNT_IN97}, 2085 {4u, 90u, P22_4, P22_4_TCPWM1_TR_ONE_CNT_IN90}, 2086 {4u, 94u, P22_4, P22_4_TCPWM1_TR_ONE_CNT_IN94}, 2087 {4u, 87u, P22_5, P22_5_TCPWM1_TR_ONE_CNT_IN87}, 2088 {4u, 91u, P22_5, P22_5_TCPWM1_TR_ONE_CNT_IN91}, 2089 {4u, 84u, P22_6, P22_6_TCPWM1_TR_ONE_CNT_IN84}, 2090 {4u, 88u, P22_6, P22_6_TCPWM1_TR_ONE_CNT_IN88}, 2091 {4u, 81u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN81}, 2092 {4u, 85u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN85}, 2093 {10u, 24u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN1560}, 2094 {4u, 82u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN82}, 2095 {7u, 24u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN792}, 2096 {10u, 25u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN1561}, 2097 {7u, 25u, P23_1, P23_1_TCPWM1_TR_ONE_CNT_IN793}, 2098 {7u, 27u, P23_1, P23_1_TCPWM1_TR_ONE_CNT_IN795}, 2099 {7u, 28u, P23_2, P23_2_TCPWM1_TR_ONE_CNT_IN796}, 2100 {7u, 30u, P23_2, P23_2_TCPWM1_TR_ONE_CNT_IN798}, 2101 {7u, 31u, P23_3, P23_3_TCPWM1_TR_ONE_CNT_IN799}, 2102 {7u, 33u, P23_3, P23_3_TCPWM1_TR_ONE_CNT_IN801}, 2103 {4u, 75u, P23_4, P23_4_TCPWM1_TR_ONE_CNT_IN75}, 2104 {7u, 34u, P23_4, P23_4_TCPWM1_TR_ONE_CNT_IN802}, 2105 {4u, 72u, P23_5, P23_5_TCPWM1_TR_ONE_CNT_IN72}, 2106 {4u, 76u, P23_5, P23_5_TCPWM1_TR_ONE_CNT_IN76}, 2107 {4u, 69u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN69}, 2108 {4u, 73u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN73}, 2109 {10u, 27u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN1563}, 2110 {4u, 66u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN66}, 2111 {4u, 70u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN70}, 2112 {10u, 28u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN1564}, 2113 {4u, 189u, P28_0, P28_0_TCPWM1_TR_ONE_CNT_IN189}, 2114 {4u, 196u, P28_0, P28_0_TCPWM1_TR_ONE_CNT_IN196}, 2115 {4u, 190u, P28_1, P28_1_TCPWM1_TR_ONE_CNT_IN190}, 2116 {4u, 192u, P28_1, P28_1_TCPWM1_TR_ONE_CNT_IN192}, 2117 {4u, 193u, P28_2, P28_2_TCPWM1_TR_ONE_CNT_IN193}, 2118 {4u, 195u, P28_2, P28_2_TCPWM1_TR_ONE_CNT_IN195}, 2119 {10u, 36u, P28_2, P28_2_TCPWM1_TR_ONE_CNT_IN1572}, 2120 {4u, 196u, P28_3, P28_3_TCPWM1_TR_ONE_CNT_IN196}, 2121 {4u, 198u, P28_3, P28_3_TCPWM1_TR_ONE_CNT_IN198}, 2122 {10u, 37u, P28_3, P28_3_TCPWM1_TR_ONE_CNT_IN1573}, 2123 {4u, 199u, P28_4, P28_4_TCPWM1_TR_ONE_CNT_IN199}, 2124 {4u, 201u, P28_4, P28_4_TCPWM1_TR_ONE_CNT_IN201}, 2125 {4u, 202u, P28_5, P28_5_TCPWM1_TR_ONE_CNT_IN202}, 2126 {4u, 204u, P28_5, P28_5_TCPWM1_TR_ONE_CNT_IN204}, 2127 {4u, 205u, P28_6, P28_6_TCPWM1_TR_ONE_CNT_IN205}, 2128 {4u, 207u, P28_6, P28_6_TCPWM1_TR_ONE_CNT_IN207}, 2129 {4u, 208u, P28_7, P28_7_TCPWM1_TR_ONE_CNT_IN208}, 2130 {4u, 210u, P28_7, P28_7_TCPWM1_TR_ONE_CNT_IN210}, 2131 {4u, 226u, P29_0, P29_0_TCPWM1_TR_ONE_CNT_IN226}, 2132 {4u, 228u, P29_0, P29_0_TCPWM1_TR_ONE_CNT_IN228}, 2133 {4u, 229u, P29_1, P29_1_TCPWM1_TR_ONE_CNT_IN229}, 2134 {4u, 231u, P29_1, P29_1_TCPWM1_TR_ONE_CNT_IN231}, 2135 {4u, 232u, P29_2, P29_2_TCPWM1_TR_ONE_CNT_IN232}, 2136 {4u, 234u, P29_2, P29_2_TCPWM1_TR_ONE_CNT_IN234}, 2137 {4u, 235u, P29_3, P29_3_TCPWM1_TR_ONE_CNT_IN235}, 2138 {4u, 237u, P29_3, P29_3_TCPWM1_TR_ONE_CNT_IN237}, 2139 {4u, 238u, P29_4, P29_4_TCPWM1_TR_ONE_CNT_IN238}, 2140 {4u, 240u, P29_4, P29_4_TCPWM1_TR_ONE_CNT_IN240}, 2141 {4u, 241u, P29_5, P29_5_TCPWM1_TR_ONE_CNT_IN241}, 2142 {4u, 243u, P29_5, P29_5_TCPWM1_TR_ONE_CNT_IN243}, 2143 {4u, 244u, P29_6, P29_6_TCPWM1_TR_ONE_CNT_IN244}, 2144 {4u, 246u, P29_6, P29_6_TCPWM1_TR_ONE_CNT_IN246}, 2145 {4u, 247u, P29_7, P29_7_TCPWM1_TR_ONE_CNT_IN247}, 2146 {4u, 249u, P29_7, P29_7_TCPWM1_TR_ONE_CNT_IN249}, 2147 {4u, 249u, P30_0, P30_0_TCPWM1_TR_ONE_CNT_IN249}, 2148 {4u, 250u, P30_0, P30_0_TCPWM1_TR_ONE_CNT_IN250}, 2149 {4u, 246u, P30_1, P30_1_TCPWM1_TR_ONE_CNT_IN246}, 2150 {4u, 250u, P30_1, P30_1_TCPWM1_TR_ONE_CNT_IN250}, 2151 {4u, 243u, P30_2, P30_2_TCPWM1_TR_ONE_CNT_IN243}, 2152 {4u, 247u, P30_2, P30_2_TCPWM1_TR_ONE_CNT_IN247}, 2153 {4u, 240u, P30_3, P30_3_TCPWM1_TR_ONE_CNT_IN240}, 2154 {4u, 244u, P30_3, P30_3_TCPWM1_TR_ONE_CNT_IN244}, 2155 {4u, 237u, P31_0, P31_0_TCPWM1_TR_ONE_CNT_IN237}, 2156 {4u, 241u, P31_0, P31_0_TCPWM1_TR_ONE_CNT_IN241}, 2157 {4u, 234u, P31_1, P31_1_TCPWM1_TR_ONE_CNT_IN234}, 2158 {4u, 238u, P31_1, P31_1_TCPWM1_TR_ONE_CNT_IN238}, 2159 {4u, 231u, P31_2, P31_2_TCPWM1_TR_ONE_CNT_IN231}, 2160 {4u, 235u, P31_2, P31_2_TCPWM1_TR_ONE_CNT_IN235}, 2161 {4u, 228u, P32_0, P32_0_TCPWM1_TR_ONE_CNT_IN228}, 2162 {4u, 232u, P32_0, P32_0_TCPWM1_TR_ONE_CNT_IN232}, 2163 {4u, 225u, P32_1, P32_1_TCPWM1_TR_ONE_CNT_IN225}, 2164 {4u, 229u, P32_1, P32_1_TCPWM1_TR_ONE_CNT_IN229}, 2165 {4u, 222u, P32_2, P32_2_TCPWM1_TR_ONE_CNT_IN222}, 2166 {4u, 226u, P32_2, P32_2_TCPWM1_TR_ONE_CNT_IN226}, 2167 {4u, 219u, P32_3, P32_3_TCPWM1_TR_ONE_CNT_IN219}, 2168 {4u, 223u, P32_3, P32_3_TCPWM1_TR_ONE_CNT_IN223}, 2169 {4u, 216u, P32_4, P32_4_TCPWM1_TR_ONE_CNT_IN216}, 2170 {4u, 220u, P32_4, P32_4_TCPWM1_TR_ONE_CNT_IN220}, 2171 {4u, 213u, P32_5, P32_5_TCPWM1_TR_ONE_CNT_IN213}, 2172 {4u, 217u, P32_5, P32_5_TCPWM1_TR_ONE_CNT_IN217}, 2173 {4u, 210u, P32_6, P32_6_TCPWM1_TR_ONE_CNT_IN210}, 2174 {4u, 214u, P32_6, P32_6_TCPWM1_TR_ONE_CNT_IN214}, 2175 {4u, 207u, P32_7, P32_7_TCPWM1_TR_ONE_CNT_IN207}, 2176 {4u, 211u, P32_7, P32_7_TCPWM1_TR_ONE_CNT_IN211}, 2177 }; 2178 2179 #endif 2180
