1 /***************************************************************************//** 2 * \file cyhal_xmc7200_176_teqfp.h 3 * 4 * \brief 5 * XMC7200 device GPIO HAL header for 176-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_XMC7200_176_TEQFP_H_ 28 #define _CYHAL_XMC7200_176_TEQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_xmc7200_176_teqfp XMC7200 176-TEQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the XMC7200 176-TEQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 176-TEQFP package for the XMC7200 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 61 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 62 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 63 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 64 65 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 66 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 67 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 68 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 69 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 70 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 71 72 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 73 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 74 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 75 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 76 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 77 P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 78 79 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 80 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 81 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 82 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 83 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 84 85 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 86 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 87 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 88 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 89 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 90 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 91 92 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 93 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 94 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 95 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 96 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 97 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 98 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 99 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 100 101 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 102 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 103 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 104 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 105 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 106 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 107 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 108 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 109 110 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 111 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 112 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 113 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 114 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 115 116 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 117 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 118 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 119 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 120 121 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 122 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 123 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 124 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 125 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 126 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 127 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 128 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 129 130 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 131 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 132 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 133 134 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 135 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 136 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 137 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 138 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 139 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 140 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 141 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 142 143 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 144 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 145 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 146 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 147 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 148 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 149 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 150 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 151 152 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 153 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 154 P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2 155 P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3 156 P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4 157 P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5 158 P14_6 = CYHAL_GET_GPIO(CYHAL_PORT_14, 6), //!< Port 14 Pin 6 159 P14_7 = CYHAL_GET_GPIO(CYHAL_PORT_14, 7), //!< Port 14 Pin 7 160 161 P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0 162 P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1 163 P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2 164 P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3 165 166 P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3), //!< Port 16 Pin 3 167 168 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 169 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 170 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 171 P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3 172 P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4 173 P17_5 = CYHAL_GET_GPIO(CYHAL_PORT_17, 5), //!< Port 17 Pin 5 174 P17_6 = CYHAL_GET_GPIO(CYHAL_PORT_17, 6), //!< Port 17 Pin 6 175 P17_7 = CYHAL_GET_GPIO(CYHAL_PORT_17, 7), //!< Port 17 Pin 7 176 177 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 178 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 179 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 180 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 181 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 182 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 183 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 184 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 185 186 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 187 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 188 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 189 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 190 P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4 191 192 P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0 193 P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1 194 P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2 195 P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3 196 P20_4 = CYHAL_GET_GPIO(CYHAL_PORT_20, 4), //!< Port 20 Pin 4 197 P20_5 = CYHAL_GET_GPIO(CYHAL_PORT_20, 5), //!< Port 20 Pin 5 198 P20_6 = CYHAL_GET_GPIO(CYHAL_PORT_20, 6), //!< Port 20 Pin 6 199 P20_7 = CYHAL_GET_GPIO(CYHAL_PORT_20, 7), //!< Port 20 Pin 7 200 201 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 202 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 203 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 204 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 205 P21_4 = CYHAL_GET_GPIO(CYHAL_PORT_21, 4), //!< Port 21 Pin 4 206 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 207 P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6 208 P21_7 = CYHAL_GET_GPIO(CYHAL_PORT_21, 7), //!< Port 21 Pin 7 209 210 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 211 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 212 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 213 P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4 214 P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5 215 P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6 216 P22_7 = CYHAL_GET_GPIO(CYHAL_PORT_22, 7), //!< Port 22 Pin 7 217 218 P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0 219 P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1 220 P23_2 = CYHAL_GET_GPIO(CYHAL_PORT_23, 2), //!< Port 23 Pin 2 221 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 222 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 223 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 224 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 225 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 226 } cyhal_gpio_xmc7200_176_teqfp_t; 227 228 /** Create generic name for the series/package specific type. */ 229 typedef cyhal_gpio_xmc7200_176_teqfp_t cyhal_gpio_t; 230 231 /* Connection type definition */ 232 /** Represents an association between a pin and a resource */ 233 typedef struct 234 { 235 uint8_t block_num; //!< The block number of the resource with this connection 236 uint8_t channel_num; //!< The channel number of the block with this connection 237 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 238 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 239 } cyhal_resource_pin_mapping_t; 240 241 /* Pin connections */ 242 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 243 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 244 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 245 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; 246 /** Indicates that a pin map exists for audioss_mclk*/ 247 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_MCLK (CY_GPIO_DM_STRONG) 248 /** List of valid pin to peripheral connections for the audioss_mclk signal. */ 249 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3]; 250 /** Indicates that a pin map exists for audioss_rx_sck*/ 251 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 252 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 253 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3]; 254 /** Indicates that a pin map exists for audioss_rx_sdi*/ 255 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 256 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 257 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3]; 258 /** Indicates that a pin map exists for audioss_rx_ws*/ 259 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 260 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 261 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3]; 262 /** Indicates that a pin map exists for audioss_tx_sck*/ 263 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 264 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 265 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; 266 /** Indicates that a pin map exists for audioss_tx_sdo*/ 267 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 268 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 269 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3]; 270 /** Indicates that a pin map exists for audioss_tx_ws*/ 271 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 272 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 273 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3]; 274 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 275 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 276 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 277 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[18]; 278 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 279 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 280 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 281 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[18]; 282 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 283 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 284 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 285 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3]; 286 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 287 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 288 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 289 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 290 /** Indicates that a pin map exists for cpuss_fault_out*/ 291 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 292 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 293 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8]; 294 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 295 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 296 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 297 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 298 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 299 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 300 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 301 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 302 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 303 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 304 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 305 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 306 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 307 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 308 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 309 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 310 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 311 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 312 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 313 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 314 /** Indicates that a pin map exists for cpuss_trace_clock*/ 315 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 316 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 317 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 318 /** Indicates that a pin map exists for cpuss_trace_data*/ 319 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 320 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 321 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 322 /** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/ 323 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF) 324 /** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */ 325 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1]; 326 /** Indicates that a pin map exists for eth_mdc*/ 327 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF) 328 /** List of valid pin to peripheral connections for the eth_mdc signal. */ 329 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1]; 330 /** Indicates that a pin map exists for eth_mdio*/ 331 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF) 332 /** List of valid pin to peripheral connections for the eth_mdio signal. */ 333 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1]; 334 /** Indicates that a pin map exists for eth_ref_clk*/ 335 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_DM_HIGHZ) 336 /** List of valid pin to peripheral connections for the eth_ref_clk signal. */ 337 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1]; 338 /** Indicates that a pin map exists for eth_rx_clk*/ 339 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_DM_HIGHZ) 340 /** List of valid pin to peripheral connections for the eth_rx_clk signal. */ 341 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1]; 342 /** Indicates that a pin map exists for eth_rx_ctl*/ 343 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_DM_HIGHZ) 344 /** List of valid pin to peripheral connections for the eth_rx_ctl signal. */ 345 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1]; 346 /** Indicates that a pin map exists for eth_rx_er*/ 347 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_DM_HIGHZ) 348 /** List of valid pin to peripheral connections for the eth_rx_er signal. */ 349 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1]; 350 /** Indicates that a pin map exists for eth_rxd*/ 351 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_DM_HIGHZ) 352 /** List of valid pin to peripheral connections for the eth_rxd signal. */ 353 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4]; 354 /** Indicates that a pin map exists for eth_tx_clk*/ 355 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF) 356 /** List of valid pin to peripheral connections for the eth_tx_clk signal. */ 357 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1]; 358 /** Indicates that a pin map exists for eth_tx_ctl*/ 359 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF) 360 /** List of valid pin to peripheral connections for the eth_tx_ctl signal. */ 361 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1]; 362 /** Indicates that a pin map exists for eth_tx_er*/ 363 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_ER (CY_GPIO_DM_STRONG) 364 /** List of valid pin to peripheral connections for the eth_tx_er signal. */ 365 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1]; 366 /** Indicates that a pin map exists for eth_txd*/ 367 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF) 368 /** List of valid pin to peripheral connections for the eth_txd signal. */ 369 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4]; 370 /** Indicates that a pin map exists for flexray_rxda*/ 371 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDA (CY_GPIO_DM_HIGHZ) 372 /** List of valid pin to peripheral connections for the flexray_rxda signal. */ 373 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1]; 374 /** Indicates that a pin map exists for flexray_rxdb*/ 375 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDB (CY_GPIO_DM_HIGHZ) 376 /** List of valid pin to peripheral connections for the flexray_rxdb signal. */ 377 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1]; 378 /** Indicates that a pin map exists for flexray_txda*/ 379 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDA (CY_GPIO_DM_STRONG) 380 /** List of valid pin to peripheral connections for the flexray_txda signal. */ 381 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1]; 382 /** Indicates that a pin map exists for flexray_txdb*/ 383 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDB (CY_GPIO_DM_STRONG) 384 /** List of valid pin to peripheral connections for the flexray_txdb signal. */ 385 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1]; 386 /** Indicates that a pin map exists for flexray_txena_n*/ 387 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENA_N (CY_GPIO_DM_STRONG) 388 /** List of valid pin to peripheral connections for the flexray_txena_n signal. */ 389 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1]; 390 /** Indicates that a pin map exists for flexray_txenb_n*/ 391 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENB_N (CY_GPIO_DM_STRONG) 392 /** List of valid pin to peripheral connections for the flexray_txenb_n signal. */ 393 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1]; 394 /** Indicates that a pin map exists for lin_lin_en*/ 395 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 396 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 397 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[27]; 398 /** Indicates that a pin map exists for lin_lin_rx*/ 399 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 400 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 401 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[37]; 402 /** Indicates that a pin map exists for lin_lin_tx*/ 403 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 404 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 405 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[37]; 406 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 407 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 408 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 409 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3]; 410 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 411 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 412 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 413 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9]; 414 /** Indicates that a pin map exists for pass_sarmux_pads*/ 415 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 416 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 417 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[81]; 418 /** Indicates that a pin map exists for peri_tr_io_input*/ 419 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 420 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 421 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[34]; 422 /** Indicates that a pin map exists for peri_tr_io_output*/ 423 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 424 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 425 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 426 /** Indicates that a pin map exists for scb_i2c_scl*/ 427 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 428 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 429 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19]; 430 /** Indicates that a pin map exists for scb_i2c_sda*/ 431 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 432 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 433 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[19]; 434 /** Indicates that a pin map exists for scb_spi_m_clk*/ 435 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 436 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 437 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[21]; 438 /** Indicates that a pin map exists for scb_spi_m_miso*/ 439 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 440 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 441 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[20]; 442 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 443 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 444 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 445 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[20]; 446 /** Indicates that a pin map exists for scb_spi_m_select0*/ 447 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 448 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 449 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[21]; 450 /** Indicates that a pin map exists for scb_spi_m_select1*/ 451 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 452 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 453 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[16]; 454 /** Indicates that a pin map exists for scb_spi_m_select2*/ 455 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 456 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 457 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[15]; 458 /** Indicates that a pin map exists for scb_spi_m_select3*/ 459 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 460 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 461 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5]; 462 /** Indicates that a pin map exists for scb_spi_s_clk*/ 463 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 464 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 465 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[21]; 466 /** Indicates that a pin map exists for scb_spi_s_miso*/ 467 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 468 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 469 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[20]; 470 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 471 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 472 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 473 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[20]; 474 /** Indicates that a pin map exists for scb_spi_s_select0*/ 475 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 476 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 477 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[21]; 478 /** Indicates that a pin map exists for scb_spi_s_select1*/ 479 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 480 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 481 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[16]; 482 /** Indicates that a pin map exists for scb_spi_s_select2*/ 483 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 484 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 485 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[15]; 486 /** Indicates that a pin map exists for scb_spi_s_select3*/ 487 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 488 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 489 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5]; 490 /** Indicates that a pin map exists for scb_uart_cts*/ 491 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 492 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 493 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[17]; 494 /** Indicates that a pin map exists for scb_uart_rts*/ 495 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 496 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 497 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[17]; 498 /** Indicates that a pin map exists for scb_uart_rx*/ 499 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 500 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 501 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17]; 502 /** Indicates that a pin map exists for scb_uart_tx*/ 503 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 504 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 505 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[17]; 506 /** Indicates that a pin map exists for sdhc_card_cmd*/ 507 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 508 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 509 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; 510 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 511 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 512 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 513 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; 514 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 515 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 516 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 517 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; 518 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 519 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 520 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 521 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; 522 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 523 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 524 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 525 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; 526 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 527 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 528 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 529 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; 530 /** Indicates that a pin map exists for sdhc_clk_card*/ 531 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 532 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 533 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; 534 /** Indicates that a pin map exists for smif_spi_clk*/ 535 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 536 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 537 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 538 /** Indicates that a pin map exists for smif_spi_data0*/ 539 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 540 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 541 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 542 /** Indicates that a pin map exists for smif_spi_data1*/ 543 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 544 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 545 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 546 /** Indicates that a pin map exists for smif_spi_data2*/ 547 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 548 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 549 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 550 /** Indicates that a pin map exists for smif_spi_data3*/ 551 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 552 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 553 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 554 /** Indicates that a pin map exists for smif_spi_data4*/ 555 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 556 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 557 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 558 /** Indicates that a pin map exists for smif_spi_data5*/ 559 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 560 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 561 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 562 /** Indicates that a pin map exists for smif_spi_data6*/ 563 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 564 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 565 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 566 /** Indicates that a pin map exists for smif_spi_data7*/ 567 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 568 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 569 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 570 /** Indicates that a pin map exists for smif_spi_rwds*/ 571 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_RWDS (CY_GPIO_DM_STRONG) 572 /** List of valid pin to peripheral connections for the smif_spi_rwds signal. */ 573 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[1]; 574 /** Indicates that a pin map exists for smif_spi_select0*/ 575 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 576 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 577 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 578 /** Indicates that a pin map exists for smif_spi_select1*/ 579 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 580 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 581 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 582 /** Indicates that a pin map exists for tcpwm_line*/ 583 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 584 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 585 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[181]; 586 /** Indicates that a pin map exists for tcpwm_line_compl*/ 587 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 588 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 589 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[182]; 590 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 591 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 592 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 593 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[358]; 594 595 #if defined(__cplusplus) 596 } 597 #endif /* __cplusplus */ 598 599 /** \} group_hal_impl_pin_package */ 600 601 #endif /* _CYHAL_XMC7200_176_TEQFP_H_ */ 602 603 604 /* [] END OF FILE */ 605
