1 /***************************************************************************//** 2 * \file cyhal_xmc7100_100_teqfp.h 3 * 4 * \brief 5 * XMC7100 device GPIO HAL header for 100-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_XMC7100_100_TEQFP_H_ 28 #define _CYHAL_XMC7100_100_TEQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_xmc7100_100_teqfp XMC7100 100-TEQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the XMC7100 100-TEQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 100-TEQFP package for the XMC7100 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 61 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 62 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 63 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 64 65 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 66 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 67 68 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 69 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 70 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 71 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 72 73 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 74 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 75 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 76 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 77 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 78 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 79 80 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 81 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 82 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 83 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 84 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 85 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 86 87 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 88 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 89 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 90 91 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 92 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 93 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 94 95 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 96 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 97 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 98 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 99 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 100 101 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 102 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 103 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 104 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 105 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 106 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 107 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 108 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 109 110 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 111 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 112 113 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 114 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 115 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 116 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 117 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 118 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 119 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 120 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 121 122 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 123 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 124 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 125 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 126 127 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 128 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 129 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 130 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 131 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 132 133 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 134 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 135 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 136 137 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 138 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 139 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 140 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 141 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 142 } cyhal_gpio_xmc7100_100_teqfp_t; 143 144 /** Create generic name for the series/package specific type. */ 145 typedef cyhal_gpio_xmc7100_100_teqfp_t cyhal_gpio_t; 146 147 /* Connection type definition */ 148 /** Represents an association between a pin and a resource */ 149 typedef struct 150 { 151 uint8_t block_num; //!< The block number of the resource with this connection 152 uint8_t channel_num; //!< The channel number of the block with this connection 153 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 154 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 155 } cyhal_resource_pin_mapping_t; 156 157 /* Pin connections */ 158 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 159 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 160 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 161 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[2]; 162 /** Indicates that a pin map exists for audioss_mclk*/ 163 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_MCLK (CY_GPIO_DM_STRONG) 164 /** List of valid pin to peripheral connections for the audioss_mclk signal. */ 165 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3]; 166 /** Indicates that a pin map exists for audioss_rx_sck*/ 167 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 168 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 169 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[2]; 170 /** Indicates that a pin map exists for audioss_rx_sdi*/ 171 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 172 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 173 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2]; 174 /** Indicates that a pin map exists for audioss_rx_ws*/ 175 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 176 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 177 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[2]; 178 /** Indicates that a pin map exists for audioss_tx_sck*/ 179 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 180 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 181 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; 182 /** Indicates that a pin map exists for audioss_tx_sdo*/ 183 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 184 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 185 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2]; 186 /** Indicates that a pin map exists for audioss_tx_ws*/ 187 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 188 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 189 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2]; 190 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 191 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 192 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 193 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[10]; 194 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 195 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 196 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 197 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[11]; 198 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 199 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 200 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 201 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2]; 202 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 203 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 204 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 205 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 206 /** Indicates that a pin map exists for cpuss_fault_out*/ 207 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 208 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 209 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5]; 210 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 211 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 212 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 213 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 214 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 215 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 216 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 217 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 218 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 219 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 220 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 221 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 222 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 223 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 224 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 225 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 226 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 227 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 228 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 229 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 230 /** Indicates that a pin map exists for cpuss_trace_clock*/ 231 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 232 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 233 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 234 /** Indicates that a pin map exists for cpuss_trace_data*/ 235 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 236 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 237 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 238 /** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/ 239 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF) 240 /** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */ 241 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1]; 242 /** Indicates that a pin map exists for eth_mdc*/ 243 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF) 244 /** List of valid pin to peripheral connections for the eth_mdc signal. */ 245 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1]; 246 /** Indicates that a pin map exists for eth_mdio*/ 247 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF) 248 /** List of valid pin to peripheral connections for the eth_mdio signal. */ 249 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1]; 250 /** Indicates that a pin map exists for eth_ref_clk*/ 251 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_DM_HIGHZ) 252 /** List of valid pin to peripheral connections for the eth_ref_clk signal. */ 253 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1]; 254 /** Indicates that a pin map exists for eth_rx_clk*/ 255 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_DM_HIGHZ) 256 /** List of valid pin to peripheral connections for the eth_rx_clk signal. */ 257 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1]; 258 /** Indicates that a pin map exists for eth_rx_ctl*/ 259 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_DM_HIGHZ) 260 /** List of valid pin to peripheral connections for the eth_rx_ctl signal. */ 261 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1]; 262 /** Indicates that a pin map exists for eth_rx_er*/ 263 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_DM_HIGHZ) 264 /** List of valid pin to peripheral connections for the eth_rx_er signal. */ 265 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1]; 266 /** Indicates that a pin map exists for eth_rxd*/ 267 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_DM_HIGHZ) 268 /** List of valid pin to peripheral connections for the eth_rxd signal. */ 269 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4]; 270 /** Indicates that a pin map exists for eth_tx_clk*/ 271 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF) 272 /** List of valid pin to peripheral connections for the eth_tx_clk signal. */ 273 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1]; 274 /** Indicates that a pin map exists for eth_tx_ctl*/ 275 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF) 276 /** List of valid pin to peripheral connections for the eth_tx_ctl signal. */ 277 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1]; 278 /** Indicates that a pin map exists for eth_tx_er*/ 279 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_ER (CY_GPIO_DM_STRONG) 280 /** List of valid pin to peripheral connections for the eth_tx_er signal. */ 281 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1]; 282 /** Indicates that a pin map exists for eth_txd*/ 283 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF) 284 /** List of valid pin to peripheral connections for the eth_txd signal. */ 285 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4]; 286 /** Indicates that a pin map exists for lin_lin_en*/ 287 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 288 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 289 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[12]; 290 /** Indicates that a pin map exists for lin_lin_rx*/ 291 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 292 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 293 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[17]; 294 /** Indicates that a pin map exists for lin_lin_tx*/ 295 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 296 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 297 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[16]; 298 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 299 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 300 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 301 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2]; 302 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 303 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 304 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 305 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[5]; 306 /** Indicates that a pin map exists for pass_sarmux_pads*/ 307 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 308 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 309 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[37]; 310 /** Indicates that a pin map exists for peri_tr_io_input*/ 311 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 312 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 313 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[14]; 314 /** Indicates that a pin map exists for peri_tr_io_output*/ 315 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 316 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 317 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4]; 318 /** Indicates that a pin map exists for scb_i2c_scl*/ 319 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 320 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 321 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10]; 322 /** Indicates that a pin map exists for scb_i2c_sda*/ 323 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 324 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 325 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; 326 /** Indicates that a pin map exists for scb_spi_m_clk*/ 327 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 328 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 329 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11]; 330 /** Indicates that a pin map exists for scb_spi_m_miso*/ 331 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 332 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 333 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13]; 334 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 335 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 336 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 337 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; 338 /** Indicates that a pin map exists for scb_spi_m_select0*/ 339 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 340 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 341 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12]; 342 /** Indicates that a pin map exists for scb_spi_m_select1*/ 343 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 344 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 345 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[7]; 346 /** Indicates that a pin map exists for scb_spi_m_select2*/ 347 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 348 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 349 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; 350 /** Indicates that a pin map exists for scb_spi_m_select3*/ 351 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 352 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 353 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; 354 /** Indicates that a pin map exists for scb_spi_s_clk*/ 355 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 356 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 357 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11]; 358 /** Indicates that a pin map exists for scb_spi_s_miso*/ 359 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 360 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 361 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13]; 362 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 363 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 364 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 365 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; 366 /** Indicates that a pin map exists for scb_spi_s_select0*/ 367 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 368 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 369 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12]; 370 /** Indicates that a pin map exists for scb_spi_s_select1*/ 371 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 372 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 373 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[7]; 374 /** Indicates that a pin map exists for scb_spi_s_select2*/ 375 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 376 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 377 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; 378 /** Indicates that a pin map exists for scb_spi_s_select3*/ 379 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 380 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 381 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; 382 /** Indicates that a pin map exists for scb_uart_cts*/ 383 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 384 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 385 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; 386 /** Indicates that a pin map exists for scb_uart_rts*/ 387 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 388 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 389 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9]; 390 /** Indicates that a pin map exists for scb_uart_rx*/ 391 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 392 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 393 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10]; 394 /** Indicates that a pin map exists for scb_uart_tx*/ 395 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 396 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 397 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; 398 /** Indicates that a pin map exists for sdhc_card_cmd*/ 399 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 400 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 401 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; 402 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 403 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 404 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 405 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; 406 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 407 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 408 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 409 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; 410 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 411 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 412 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 413 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; 414 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 415 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 416 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 417 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; 418 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 419 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 420 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 421 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; 422 /** Indicates that a pin map exists for sdhc_clk_card*/ 423 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 424 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 425 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; 426 /** Indicates that a pin map exists for smif_spi_clk*/ 427 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 428 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 429 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 430 /** Indicates that a pin map exists for smif_spi_data0*/ 431 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 432 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 433 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 434 /** Indicates that a pin map exists for smif_spi_data1*/ 435 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 436 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 437 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 438 /** Indicates that a pin map exists for smif_spi_data2*/ 439 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 440 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 441 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 442 /** Indicates that a pin map exists for smif_spi_data3*/ 443 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 444 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 445 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 446 /** Indicates that a pin map exists for smif_spi_data4*/ 447 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 448 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 449 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 450 /** Indicates that a pin map exists for smif_spi_data5*/ 451 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 452 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 453 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 454 /** Indicates that a pin map exists for smif_spi_data6*/ 455 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 456 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 457 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 458 /** Indicates that a pin map exists for smif_spi_data7*/ 459 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 460 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 461 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 462 /** Indicates that a pin map exists for smif_spi_rwds*/ 463 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_RWDS (CY_GPIO_DM_STRONG) 464 /** List of valid pin to peripheral connections for the smif_spi_rwds signal. */ 465 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[1]; 466 /** Indicates that a pin map exists for smif_spi_select0*/ 467 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 468 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 469 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 470 /** Indicates that a pin map exists for smif_spi_select1*/ 471 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 472 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 473 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 474 /** Indicates that a pin map exists for tcpwm_line*/ 475 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 476 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 477 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80]; 478 /** Indicates that a pin map exists for tcpwm_line_compl*/ 479 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 480 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 481 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82]; 482 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 483 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 484 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 485 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[154]; 486 487 #if defined(__cplusplus) 488 } 489 #endif /* __cplusplus */ 490 491 /** \} group_hal_impl_pin_package */ 492 493 #endif /* _CYHAL_XMC7100_100_TEQFP_H_ */ 494 495 496 /* [] END OF FILE */ 497
