1 /***************************************************************************//** 2 * \file cyhal_xmc7100_100_teqfp.c 3 * 4 * \brief 5 * XMC7100 device GPIO HAL header for 100-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_XMC7100_100_TEQFP_H_) 31 #include "pin_packages/cyhal_xmc7100_100_teqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: audioss_clk_i2s_if */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[2] = { 36 {0u, 0u, P12_1, P12_1_AUDIOSS0_CLK_I2S_IF}, 37 {1u, 0u, P13_4, P13_4_AUDIOSS1_CLK_I2S_IF}, 38 }; 39 40 /* Connections for: audioss_mclk */ 41 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3] = { 42 {0u, 0u, P11_0, P11_0_AUDIOSS0_MCLK}, 43 {1u, 0u, P13_0, P13_0_AUDIOSS1_MCLK}, 44 {2u, 0u, P14_0, P14_0_AUDIOSS2_MCLK}, 45 }; 46 47 /* Connections for: audioss_rx_sck */ 48 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[2] = { 49 {0u, 0u, P12_2, P12_2_AUDIOSS0_RX_SCK}, 50 {1u, 0u, P13_5, P13_5_AUDIOSS1_RX_SCK}, 51 }; 52 53 /* Connections for: audioss_rx_sdi */ 54 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2] = { 55 {0u, 0u, P12_4, P12_4_AUDIOSS0_RX_SDI}, 56 {1u, 0u, P13_7, P13_7_AUDIOSS1_RX_SDI}, 57 }; 58 59 /* Connections for: audioss_rx_ws */ 60 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[2] = { 61 {0u, 0u, P12_3, P12_3_AUDIOSS0_RX_WS}, 62 {1u, 0u, P13_6, P13_6_AUDIOSS1_RX_WS}, 63 }; 64 65 /* Connections for: audioss_tx_sck */ 66 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3] = { 67 {0u, 0u, P11_1, P11_1_AUDIOSS0_TX_SCK}, 68 {1u, 0u, P13_1, P13_1_AUDIOSS1_TX_SCK}, 69 {2u, 0u, P14_1, P14_1_AUDIOSS2_TX_SCK}, 70 }; 71 72 /* Connections for: audioss_tx_sdo */ 73 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2] = { 74 {0u, 0u, P12_0, P12_0_AUDIOSS0_TX_SDO}, 75 {1u, 0u, P13_3, P13_3_AUDIOSS1_TX_SDO}, 76 }; 77 78 /* Connections for: audioss_tx_ws */ 79 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2] = { 80 {0u, 0u, P11_2, P11_2_AUDIOSS0_TX_WS}, 81 {1u, 0u, P13_2, P13_2_AUDIOSS1_TX_WS}, 82 }; 83 84 /* Connections for: canfd_ttcan_rx */ 85 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[10] = { 86 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 87 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 88 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 89 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 90 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 91 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 92 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 93 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 94 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 95 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 96 }; 97 98 /* Connections for: canfd_ttcan_tx */ 99 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[11] = { 100 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 101 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 102 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 103 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 104 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 105 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 106 {1u, 1u, P12_4, P12_4_CANFD1_TTCAN_TX1}, 107 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 108 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 109 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 110 {1u, 1u, P21_5, P21_5_CANFD1_TTCAN_TX1}, 111 }; 112 113 /* Connections for: cpuss_cal_sup_nz */ 114 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 115 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 116 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 117 }; 118 119 /* Connections for: cpuss_clk_fm_pump */ 120 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 121 {0u, 0u, NC, HSIOM_SEL_GPIO}, 122 }; 123 124 /* Connections for: cpuss_fault_out */ 125 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5] = { 126 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 127 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 128 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 129 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 130 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 131 }; 132 133 /* Connections for: cpuss_swj_swclk_tclk */ 134 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 135 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 136 }; 137 138 /* Connections for: cpuss_swj_swdio_tms */ 139 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 140 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 141 }; 142 143 /* Connections for: cpuss_swj_swdoe_tdi */ 144 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 145 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 146 }; 147 148 /* Connections for: cpuss_swj_swo_tdo */ 149 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 150 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 151 }; 152 153 /* Connections for: cpuss_swj_trstn */ 154 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 155 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 156 }; 157 158 /* Connections for: cpuss_trace_clock */ 159 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 160 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 161 }; 162 163 /* Connections for: cpuss_trace_data */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 165 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 166 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 167 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 168 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 169 {0u, 0u, P21_5, P21_5_CPUSS_TRACE_DATA0}, 170 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 171 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 172 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 173 }; 174 175 /* Connections for: eth_eth_tsu_timer_cmp_val */ 176 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1] = { 177 {0u, 0u, P2_3, P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL}, 178 }; 179 180 /* Connections for: eth_mdc */ 181 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1] = { 182 {0u, 0u, P3_1, P3_1_ETH0_MDC}, 183 }; 184 185 /* Connections for: eth_mdio */ 186 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1] = { 187 {0u, 0u, P3_0, P3_0_ETH0_MDIO}, 188 }; 189 190 /* Connections for: eth_ref_clk */ 191 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1] = { 192 {0u, 0u, P18_0, P18_0_ETH0_REF_CLK}, 193 }; 194 195 /* Connections for: eth_rx_clk */ 196 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1] = { 197 {0u, 0u, P23_3, P23_3_ETH0_RX_CLK}, 198 }; 199 200 /* Connections for: eth_rx_ctl */ 201 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1] = { 202 {0u, 0u, P21_5, P21_5_ETH0_RX_CTL}, 203 }; 204 205 /* Connections for: eth_rx_er */ 206 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1] = { 207 {0u, 0u, P2_2, P2_2_ETH0_RX_ER}, 208 }; 209 210 /* Connections for: eth_rxd */ 211 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4] = { 212 {0u, 0u, P19_0, P19_0_ETH0_RXD0}, 213 {0u, 1u, P19_1, P19_1_ETH0_RXD1}, 214 {0u, 2u, P19_2, P19_2_ETH0_RXD2}, 215 {0u, 3u, P19_3, P19_3_ETH0_RXD3}, 216 }; 217 218 /* Connections for: eth_tx_clk */ 219 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1] = { 220 {0u, 0u, P18_3, P18_3_ETH0_TX_CLK}, 221 }; 222 223 /* Connections for: eth_tx_ctl */ 224 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1] = { 225 {0u, 0u, P18_1, P18_1_ETH0_TX_CTL}, 226 }; 227 228 /* Connections for: eth_tx_er */ 229 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1] = { 230 {0u, 0u, P18_2, P18_2_ETH0_TX_ER}, 231 }; 232 233 /* Connections for: eth_txd */ 234 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4] = { 235 {0u, 0u, P18_4, P18_4_ETH0_TXD0}, 236 {0u, 1u, P18_5, P18_5_ETH0_TXD1}, 237 {0u, 2u, P18_6, P18_6_ETH0_TXD2}, 238 {0u, 3u, P18_7, P18_7_ETH0_TXD3}, 239 }; 240 241 /* Connections for: lin_lin_en */ 242 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[12] = { 243 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 244 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 245 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 246 {0u, 9u, P6_0, P6_0_LIN0_LIN_EN9}, 247 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 248 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 249 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 250 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 251 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 252 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 253 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 254 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 255 }; 256 257 /* Connections for: lin_lin_rx */ 258 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[17] = { 259 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 260 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 261 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 262 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 263 {0u, 10u, P5_2, P5_2_LIN0_LIN_RX10}, 264 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 265 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 266 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 267 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 268 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 269 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 270 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 271 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 272 {0u, 2u, P13_3, P13_3_LIN0_LIN_RX2}, 273 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 274 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 275 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 276 }; 277 278 /* Connections for: lin_lin_tx */ 279 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[16] = { 280 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 281 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 282 {0u, 15u, P5_0, P5_0_LIN0_LIN_TX15}, 283 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 284 {0u, 10u, P5_3, P5_3_LIN0_LIN_TX10}, 285 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 286 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 287 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 288 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 289 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 290 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 291 {0u, 2u, P13_4, P13_4_LIN0_LIN_TX2}, 292 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 293 {0u, 12u, P18_0, P18_0_LIN0_LIN_TX12}, 294 {0u, 6u, P23_3, P23_3_LIN0_LIN_TX6}, 295 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 296 }; 297 298 /* Connections for: pass_sar_ext_mux_en */ 299 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 300 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 301 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 302 }; 303 304 /* Connections for: pass_sar_ext_mux_sel */ 305 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[5] = { 306 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 307 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 308 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 309 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 310 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 311 }; 312 313 /* Connections for: pass_sarmux_pads */ 314 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[37] = { 315 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 316 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 317 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 318 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 319 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 320 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 321 {0u, 16u, P7_0, HSIOM_SEL_GPIO}, 322 {0u, 17u, P7_1, HSIOM_SEL_GPIO}, 323 {0u, 18u, P7_2, HSIOM_SEL_GPIO}, 324 {0u, 19u, P7_3, HSIOM_SEL_GPIO}, 325 {0u, 20u, P7_4, HSIOM_SEL_GPIO}, 326 {0u, 21u, P7_5, HSIOM_SEL_GPIO}, 327 {0u, 24u, P8_1, HSIOM_SEL_GPIO}, 328 {0u, 25u, P8_2, HSIOM_SEL_GPIO}, 329 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 330 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 331 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 332 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 333 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 334 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 335 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 336 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 337 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 338 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 339 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 340 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 341 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 342 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 343 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 344 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 345 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 346 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 347 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 348 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 349 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 350 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 351 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 352 }; 353 354 /* Connections for: peri_tr_io_input */ 355 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 356 to know the index of the input or output trigger line. Store that in the channel_num field 357 instead. */ 358 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[14] = { 359 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 360 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 361 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 362 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 363 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 364 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 365 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 366 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 367 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 368 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 369 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 370 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 371 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 372 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 373 }; 374 375 /* Connections for: peri_tr_io_output */ 376 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 377 to know the index of the input or output trigger line. Store that in the channel_num field 378 instead. */ 379 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4] = { 380 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 381 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 382 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 383 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 384 }; 385 386 /* Connections for: scb_i2c_scl */ 387 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10] = { 388 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 389 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 390 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 391 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 392 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 393 {8u, 0u, P12_2, P12_2_SCB8_I2C_SCL}, 394 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 395 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 396 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 397 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 398 }; 399 400 /* Connections for: scb_i2c_sda */ 401 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12] = { 402 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 403 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 404 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 405 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 406 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 407 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 408 {8u, 0u, P12_1, P12_1_SCB8_I2C_SDA}, 409 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 410 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 411 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 412 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 413 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 414 }; 415 416 /* Connections for: scb_spi_m_clk */ 417 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11] = { 418 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 419 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 420 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 421 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 422 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 423 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 424 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 425 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 426 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 427 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 428 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 429 }; 430 431 /* Connections for: scb_spi_m_miso */ 432 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13] = { 433 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 434 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 435 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 436 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 437 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 438 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 439 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 440 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 441 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 442 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 443 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 444 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 445 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 446 }; 447 448 /* Connections for: scb_spi_m_mosi */ 449 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14] = { 450 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 451 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 452 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 453 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 454 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 455 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 456 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 457 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 458 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 459 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 460 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 461 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 462 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 463 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 464 }; 465 466 /* Connections for: scb_spi_m_select0 */ 467 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12] = { 468 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 469 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 470 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 471 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 472 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 473 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 474 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 475 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 476 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 477 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 478 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 479 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 480 }; 481 482 /* Connections for: scb_spi_m_select1 */ 483 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[7] = { 484 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 485 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 486 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 487 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 488 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 489 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 490 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 491 }; 492 493 /* Connections for: scb_spi_m_select2 */ 494 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8] = { 495 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 496 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 497 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 498 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 499 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 500 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 501 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 502 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 503 }; 504 505 /* Connections for: scb_spi_m_select3 */ 506 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = { 507 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 508 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 509 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 510 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 511 }; 512 513 /* Connections for: scb_spi_s_clk */ 514 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11] = { 515 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 516 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 517 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 518 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 519 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 520 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 521 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 522 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 523 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 524 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 525 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 526 }; 527 528 /* Connections for: scb_spi_s_miso */ 529 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13] = { 530 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 531 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 532 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 533 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 534 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 535 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 536 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 537 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 538 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 539 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 540 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 541 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 542 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 543 }; 544 545 /* Connections for: scb_spi_s_mosi */ 546 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14] = { 547 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 548 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 549 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 550 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 551 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 552 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 553 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 554 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 555 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 556 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 557 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 558 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 559 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 560 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 561 }; 562 563 /* Connections for: scb_spi_s_select0 */ 564 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12] = { 565 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 566 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 567 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 568 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 569 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 570 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 571 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 572 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 573 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 574 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 575 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 576 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 577 }; 578 579 /* Connections for: scb_spi_s_select1 */ 580 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[7] = { 581 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 582 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 583 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 584 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 585 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 586 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 587 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 588 }; 589 590 /* Connections for: scb_spi_s_select2 */ 591 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8] = { 592 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 593 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 594 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 595 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 596 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 597 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 598 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 599 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 600 }; 601 602 /* Connections for: scb_spi_s_select3 */ 603 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = { 604 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 605 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 606 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 607 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 608 }; 609 610 /* Connections for: scb_uart_cts */ 611 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10] = { 612 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 613 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 614 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 615 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 616 {8u, 0u, P12_3, P12_3_SCB8_UART_CTS}, 617 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 618 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 619 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 620 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 621 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 622 }; 623 624 /* Connections for: scb_uart_rts */ 625 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9] = { 626 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 627 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 628 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 629 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 630 {8u, 0u, P12_2, P12_2_SCB8_UART_RTS}, 631 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 632 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 633 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 634 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 635 }; 636 637 /* Connections for: scb_uart_rx */ 638 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10] = { 639 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 640 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 641 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 642 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 643 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 644 {8u, 0u, P12_0, P12_0_SCB8_UART_RX}, 645 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 646 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 647 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 648 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 649 }; 650 651 /* Connections for: scb_uart_tx */ 652 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11] = { 653 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 654 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 655 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 656 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 657 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 658 {8u, 0u, P12_1, P12_1_SCB8_UART_TX}, 659 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 660 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 661 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 662 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 663 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 664 }; 665 666 /* Connections for: sdhc_card_cmd */ 667 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1] = { 668 {0u, 0u, P6_3, P6_3_SDHC0_CARD_CMD}, 669 }; 670 671 /* Connections for: sdhc_card_dat_3to0 */ 672 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4] = { 673 {0u, 0u, P7_1, P7_1_SDHC0_CARD_DAT_3TO00}, 674 {0u, 1u, P7_2, P7_2_SDHC0_CARD_DAT_3TO01}, 675 {0u, 2u, P7_3, P7_3_SDHC0_CARD_DAT_3TO02}, 676 {0u, 3u, P7_4, P7_4_SDHC0_CARD_DAT_3TO03}, 677 }; 678 679 /* Connections for: sdhc_card_dat_7to4 */ 680 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4] = { 681 {0u, 0u, P7_5, P7_5_SDHC0_CARD_DAT_7TO40}, 682 {0u, 1u, P8_0, P8_0_SDHC0_CARD_DAT_7TO41}, 683 {0u, 2u, P8_1, P8_1_SDHC0_CARD_DAT_7TO42}, 684 {0u, 3u, P8_2, P8_2_SDHC0_CARD_DAT_7TO43}, 685 }; 686 687 /* Connections for: sdhc_card_detect_n */ 688 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1] = { 689 {0u, 0u, P6_5, P6_5_SDHC0_CARD_DETECT_N}, 690 }; 691 692 /* Connections for: sdhc_card_if_pwr_en */ 693 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1] = { 694 {0u, 0u, P7_0, P7_0_SDHC0_CARD_IF_PWR_EN}, 695 }; 696 697 /* Connections for: sdhc_card_mech_write_prot */ 698 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1] = { 699 {0u, 0u, P6_2, P6_2_SDHC0_CARD_MECH_WRITE_PROT}, 700 }; 701 702 /* Connections for: sdhc_clk_card */ 703 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1] = { 704 {0u, 0u, P6_4, P6_4_SDHC0_CLK_CARD}, 705 }; 706 707 /* Connections for: smif_spi_clk */ 708 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 709 {0u, 0u, P6_3, P6_3_SMIF0_SPIHB_CLK}, 710 }; 711 712 /* Connections for: smif_spi_data0 */ 713 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 714 {0u, 0u, P7_1, P7_1_SMIF0_SPIHB_DATA0}, 715 }; 716 717 /* Connections for: smif_spi_data1 */ 718 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 719 {0u, 0u, P7_2, P7_2_SMIF0_SPIHB_DATA1}, 720 }; 721 722 /* Connections for: smif_spi_data2 */ 723 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 724 {0u, 0u, P7_3, P7_3_SMIF0_SPIHB_DATA2}, 725 }; 726 727 /* Connections for: smif_spi_data3 */ 728 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 729 {0u, 0u, P7_4, P7_4_SMIF0_SPIHB_DATA3}, 730 }; 731 732 /* Connections for: smif_spi_data4 */ 733 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = { 734 {0u, 0u, P7_5, P7_5_SMIF0_SPIHB_DATA4}, 735 }; 736 737 /* Connections for: smif_spi_data5 */ 738 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = { 739 {0u, 0u, P8_0, P8_0_SMIF0_SPIHB_DATA5}, 740 }; 741 742 /* Connections for: smif_spi_data6 */ 743 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = { 744 {0u, 0u, P8_1, P8_1_SMIF0_SPIHB_DATA6}, 745 }; 746 747 /* Connections for: smif_spi_data7 */ 748 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = { 749 {0u, 0u, P8_2, P8_2_SMIF0_SPIHB_DATA7}, 750 }; 751 752 /* Connections for: smif_spi_rwds */ 753 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[1] = { 754 {0u, 0u, P6_4, P6_4_SMIF0_SPIHB_RWDS}, 755 }; 756 757 /* Connections for: smif_spi_select0 */ 758 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 759 {0u, 0u, P6_5, P6_5_SMIF0_SPIHB_SELECT0}, 760 }; 761 762 /* Connections for: smif_spi_select1 */ 763 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 764 {0u, 0u, P7_0, P7_0_SMIF0_SPIHB_SELECT1}, 765 }; 766 767 /* Connections for: tcpwm_line */ 768 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80] = { 769 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 770 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 771 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 772 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 773 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 774 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 775 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 776 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 777 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 778 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 779 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 780 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 781 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 782 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 783 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 784 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 785 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 786 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 787 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 788 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 789 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 790 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 791 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 792 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 793 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 794 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 795 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 796 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 797 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 798 {0u, 61u, P11_0, P11_0_TCPWM0_LINE61}, 799 {0u, 60u, P11_1, P11_1_TCPWM0_LINE60}, 800 {0u, 59u, P11_2, P11_2_TCPWM0_LINE59}, 801 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 802 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 803 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 804 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 805 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 806 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 807 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 808 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 809 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 810 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 811 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 812 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 813 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 814 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 815 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 816 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 817 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 818 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 819 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 820 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 821 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 822 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 823 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 824 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 825 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 826 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 827 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 828 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 829 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 830 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 831 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 832 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 833 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 834 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 835 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 836 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 837 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 838 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 839 {0u, 34u, P21_5, P21_5_TCPWM0_LINE34}, 840 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 841 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 842 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 843 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 844 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 845 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 846 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 847 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 848 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 849 }; 850 851 /* Connections for: tcpwm_line_compl */ 852 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82] = { 853 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 854 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 855 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 856 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 857 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 858 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 859 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 860 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 861 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 862 {2u, 6u, P3_0, P3_0_TCPWM0_LINE_COMPL518}, 863 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 864 {2u, 7u, P3_1, P3_1_TCPWM0_LINE_COMPL519}, 865 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 866 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 867 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 868 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 869 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 870 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 871 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 872 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 873 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 874 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 875 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 876 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 877 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 878 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 879 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 880 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 881 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 882 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 883 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 884 {0u, 62u, P11_0, P11_0_TCPWM0_LINE_COMPL62}, 885 {0u, 61u, P11_1, P11_1_TCPWM0_LINE_COMPL61}, 886 {0u, 60u, P11_2, P11_2_TCPWM0_LINE_COMPL60}, 887 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 888 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 889 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 890 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 891 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 892 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 893 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 894 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 895 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 896 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 897 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 898 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 899 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 900 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 901 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 902 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 903 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 904 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 905 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 906 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 907 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 908 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 909 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 910 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 911 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 912 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 913 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 914 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 915 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 916 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 917 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 918 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 919 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 920 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 921 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 922 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 923 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 924 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 925 {0u, 35u, P21_5, P21_5_TCPWM0_LINE_COMPL35}, 926 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 927 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 928 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 929 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 930 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 931 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 932 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 933 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 934 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 935 }; 936 937 /* Connections for: tcpwm_tr_one_cnt_in */ 938 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[154] = { 939 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 940 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 941 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 942 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 943 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 944 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 945 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 946 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 947 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 948 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 949 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 950 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 951 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 952 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 953 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 954 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 955 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 956 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 957 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 958 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 959 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 960 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 961 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 962 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 963 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 964 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 965 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 966 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 967 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 968 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 969 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 970 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 971 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 972 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 973 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 974 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 975 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 976 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 977 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 978 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 979 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 980 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 981 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 982 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 983 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 984 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 985 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 986 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 987 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 988 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 989 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 990 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 991 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 992 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 993 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 994 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 995 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 996 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 997 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 998 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 999 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 1000 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 1001 {0u, 183u, P11_0, P11_0_TCPWM0_TR_ONE_CNT_IN183}, 1002 {0u, 187u, P11_0, P11_0_TCPWM0_TR_ONE_CNT_IN187}, 1003 {0u, 180u, P11_1, P11_1_TCPWM0_TR_ONE_CNT_IN180}, 1004 {0u, 184u, P11_1, P11_1_TCPWM0_TR_ONE_CNT_IN184}, 1005 {0u, 177u, P11_2, P11_2_TCPWM0_TR_ONE_CNT_IN177}, 1006 {0u, 181u, P11_2, P11_2_TCPWM0_TR_ONE_CNT_IN181}, 1007 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 1008 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 1009 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 1010 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 1011 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 1012 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 1013 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1014 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1015 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1016 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1017 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1018 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1019 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1020 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1021 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1022 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1023 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1024 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1025 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1026 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1027 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1028 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1029 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1030 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1031 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1032 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1033 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1034 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1035 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1036 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1037 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1038 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1039 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1040 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1041 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1042 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1043 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1044 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1045 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1046 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1047 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1048 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1049 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1050 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1051 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1052 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1053 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1054 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1055 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1056 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1057 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1058 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1059 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1060 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1061 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1062 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1063 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1064 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1065 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1066 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1067 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1068 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1069 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1070 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1071 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1072 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1073 {0u, 102u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN102}, 1074 {0u, 106u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN106}, 1075 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1076 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1077 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1078 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1079 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1080 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1081 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1082 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1083 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1084 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1085 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1086 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1087 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1088 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1089 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1090 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1091 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1092 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1093 }; 1094 1095 #endif 1096
