1 /***************************************************************************//** 2 * \file cyhal_tviibe4m_144_lqfp.c 3 * 4 * \brief 5 * TVIIBE4M device GPIO HAL header for 144-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE4M_144_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe4m_144_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[13] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 39 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 40 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 41 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 42 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 43 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 44 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 45 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 46 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 47 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 48 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 49 }; 50 51 /* Connections for: canfd_ttcan_tx */ 52 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[14] = { 53 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 54 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 55 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 56 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 57 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 58 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 59 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 60 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 61 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 62 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 63 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 64 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 65 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 66 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 67 }; 68 69 /* Connections for: cpuss_cal_sup_nz */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 71 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 72 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 73 }; 74 75 /* Connections for: cpuss_clk_fm_pump */ 76 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 77 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 78 }; 79 80 /* Connections for: cpuss_fault_out */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[7] = { 82 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 83 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 84 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 85 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 86 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 87 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 88 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 89 }; 90 91 /* Connections for: cpuss_swj_swclk_tclk */ 92 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 93 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 94 }; 95 96 /* Connections for: cpuss_swj_swdio_tms */ 97 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 98 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 99 }; 100 101 /* Connections for: cpuss_swj_swdoe_tdi */ 102 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 103 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 104 }; 105 106 /* Connections for: cpuss_swj_swo_tdo */ 107 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 108 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 109 }; 110 111 /* Connections for: cpuss_swj_trstn */ 112 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 113 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 114 }; 115 116 /* Connections for: cpuss_trace_clock */ 117 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 118 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 119 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 120 }; 121 122 /* Connections for: cpuss_trace_data */ 123 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 124 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 125 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 126 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 127 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 128 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 129 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 130 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 131 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 132 }; 133 134 /* Connections for: cxpi_cxpi_en */ 135 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[5] = { 136 {0u, 0u, P7_2, P7_2_CXPI0_CXPI_EN0}, 137 {0u, 1u, P13_2, P13_2_CXPI0_CXPI_EN1}, 138 {0u, 2u, P13_7, P13_7_CXPI0_CXPI_EN2}, 139 {0u, 1u, P15_2, P15_2_CXPI0_CXPI_EN1}, 140 {0u, 3u, P19_3, P19_3_CXPI0_CXPI_EN3}, 141 }; 142 143 /* Connections for: cxpi_cxpi_rx */ 144 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[6] = { 145 {0u, 0u, P7_0, P7_0_CXPI0_CXPI_RX0}, 146 {0u, 1u, P13_0, P13_0_CXPI0_CXPI_RX1}, 147 {0u, 2u, P13_5, P13_5_CXPI0_CXPI_RX2}, 148 {0u, 2u, P14_5, P14_5_CXPI0_CXPI_RX2}, 149 {0u, 1u, P15_0, P15_0_CXPI0_CXPI_RX1}, 150 {0u, 3u, P19_1, P19_1_CXPI0_CXPI_RX3}, 151 }; 152 153 /* Connections for: cxpi_cxpi_tx */ 154 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[5] = { 155 {0u, 0u, P7_1, P7_1_CXPI0_CXPI_TX0}, 156 {0u, 1u, P13_1, P13_1_CXPI0_CXPI_TX1}, 157 {0u, 2u, P13_6, P13_6_CXPI0_CXPI_TX2}, 158 {0u, 1u, P15_1, P15_1_CXPI0_CXPI_TX1}, 159 {0u, 3u, P19_2, P19_2_CXPI0_CXPI_TX3}, 160 }; 161 162 /* Connections for: lin_lin_en */ 163 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[16] = { 164 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 165 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 166 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 167 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 168 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 169 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 170 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 171 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 172 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 173 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 174 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 175 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 176 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 177 {0u, 11u, P16_2, P16_2_LIN0_LIN_EN11}, 178 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 179 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 180 }; 181 182 /* Connections for: lin_lin_rx */ 183 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[21] = { 184 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 185 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 186 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 187 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 188 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 189 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 190 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 191 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 192 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 193 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 194 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 195 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 196 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 197 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 198 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 199 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 200 {0u, 11u, P16_0, P16_0_LIN0_LIN_RX11}, 201 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 202 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 203 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 204 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 205 }; 206 207 /* Connections for: lin_lin_tx */ 208 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[21] = { 209 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 210 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 211 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 212 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 213 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 214 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 215 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 216 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 217 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 218 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 219 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 220 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 221 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 222 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 223 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 224 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 225 {0u, 11u, P16_1, P16_1_LIN0_LIN_TX11}, 226 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 227 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 228 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 229 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 230 }; 231 232 /* Connections for: pass_sar_ext_mux_en */ 233 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 234 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 235 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 236 }; 237 238 /* Connections for: pass_sar_ext_mux_sel */ 239 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[8] = { 240 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 241 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 242 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 243 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 244 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 245 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 246 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 247 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 248 }; 249 250 /* Connections for: pass_sarmux_pads */ 251 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[54] = { 252 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 253 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 254 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 255 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 256 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 257 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 258 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 259 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 260 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 261 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 262 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 263 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 264 {0u, 12u, P7_4, HSIOM_SEL_GPIO}, 265 {0u, 13u, P7_5, HSIOM_SEL_GPIO}, 266 {0u, 14u, P7_6, HSIOM_SEL_GPIO}, 267 {0u, 15u, P7_7, HSIOM_SEL_GPIO}, 268 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 269 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 270 {0u, 18u, P8_3, HSIOM_SEL_GPIO}, 271 {0u, 20u, P9_0, HSIOM_SEL_GPIO}, 272 {0u, 21u, P9_1, HSIOM_SEL_GPIO}, 273 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 274 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 275 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 276 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 277 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 278 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 279 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 280 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 281 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 282 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 283 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 284 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 285 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 286 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 287 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 288 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 289 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 290 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 291 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 292 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 293 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 294 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 295 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 296 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 297 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 298 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 299 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 300 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 301 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 302 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 303 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 304 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 305 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 306 }; 307 308 /* Connections for: peri_tr_io_input */ 309 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 310 to know the index of the input or output trigger line. Store that in the channel_num field 311 instead. */ 312 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[25] = { 313 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 314 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 315 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 316 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 317 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 318 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 319 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 320 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 321 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 322 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 323 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 324 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 325 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 326 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 327 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 328 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 329 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 330 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 331 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 332 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 333 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 334 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 335 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 336 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 337 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 338 }; 339 340 /* Connections for: peri_tr_io_output */ 341 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 342 to know the index of the input or output trigger line. Store that in the channel_num field 343 instead. */ 344 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[5] = { 345 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 346 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 347 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 348 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 349 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 350 }; 351 352 /* Connections for: scb_i2c_scl */ 353 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = { 354 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 355 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 356 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 357 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 358 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 359 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 360 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 361 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 362 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 363 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 364 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 365 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 366 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 367 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 368 }; 369 370 /* Connections for: scb_i2c_sda */ 371 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[16] = { 372 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 373 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 374 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 375 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 376 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 377 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 378 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 379 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 380 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 381 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 382 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 383 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 384 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 385 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 386 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 387 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 388 }; 389 390 /* Connections for: scb_spi_m_clk */ 391 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12] = { 392 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 393 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 394 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 395 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 396 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 397 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 398 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 399 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 400 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 401 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 402 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 403 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 404 }; 405 406 /* Connections for: scb_spi_m_miso */ 407 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[16] = { 408 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 409 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 410 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 411 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 412 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 413 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 414 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 415 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 416 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 417 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 418 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 419 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 420 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 421 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 422 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 423 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 424 }; 425 426 /* Connections for: scb_spi_m_mosi */ 427 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15] = { 428 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 429 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 430 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 431 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 432 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 433 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 434 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 435 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 436 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 437 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 438 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 439 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 440 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 441 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 442 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 443 }; 444 445 /* Connections for: scb_spi_m_select0 */ 446 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13] = { 447 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 448 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 449 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 450 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 451 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 452 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 453 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 454 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 455 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 456 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 457 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 458 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 459 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 460 }; 461 462 /* Connections for: scb_spi_m_select1 */ 463 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[12] = { 464 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 465 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 466 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 467 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 468 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 469 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 470 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 471 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 472 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 473 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 474 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 475 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 476 }; 477 478 /* Connections for: scb_spi_m_select2 */ 479 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11] = { 480 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 481 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 482 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 483 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 484 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 485 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 486 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 487 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 488 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 489 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 490 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 491 }; 492 493 /* Connections for: scb_spi_m_select3 */ 494 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = { 495 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 496 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 497 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 498 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 499 }; 500 501 /* Connections for: scb_spi_s_clk */ 502 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12] = { 503 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 504 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 505 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 506 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 507 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 508 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 509 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 510 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 511 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 512 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 513 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 514 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 515 }; 516 517 /* Connections for: scb_spi_s_miso */ 518 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[16] = { 519 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 520 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 521 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 522 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 523 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 524 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 525 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 526 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 527 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 528 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 529 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 530 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 531 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 532 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 533 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 534 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 535 }; 536 537 /* Connections for: scb_spi_s_mosi */ 538 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15] = { 539 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 540 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 541 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 542 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 543 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 544 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 545 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 546 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 547 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 548 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 549 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 550 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 551 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 552 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 553 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 554 }; 555 556 /* Connections for: scb_spi_s_select0 */ 557 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13] = { 558 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 559 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 560 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 561 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 562 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 563 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 564 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 565 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 566 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 567 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 568 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 569 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 570 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 571 }; 572 573 /* Connections for: scb_spi_s_select1 */ 574 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[12] = { 575 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 576 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 577 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 578 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 579 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 580 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 581 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 582 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 583 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 584 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 585 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 586 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 587 }; 588 589 /* Connections for: scb_spi_s_select2 */ 590 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11] = { 591 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 592 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 593 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 594 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 595 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 596 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 597 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 598 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 599 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 600 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 601 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 602 }; 603 604 /* Connections for: scb_spi_s_select3 */ 605 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = { 606 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 607 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 608 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 609 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 610 }; 611 612 /* Connections for: scb_uart_cts */ 613 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[13] = { 614 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 615 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 616 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 617 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 618 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 619 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 620 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 621 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 622 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 623 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 624 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 625 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 626 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 627 }; 628 629 /* Connections for: scb_uart_rts */ 630 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12] = { 631 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 632 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 633 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 634 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 635 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 636 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 637 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 638 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 639 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 640 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 641 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 642 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 643 }; 644 645 /* Connections for: scb_uart_rx */ 646 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15] = { 647 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 648 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 649 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 650 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 651 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 652 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 653 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 654 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 655 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 656 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 657 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 658 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 659 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 660 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 661 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 662 }; 663 664 /* Connections for: scb_uart_tx */ 665 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[14] = { 666 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 667 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 668 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 669 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 670 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 671 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 672 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 673 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 674 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 675 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 676 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 677 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 678 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 679 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 680 }; 681 682 /* Connections for: tcpwm_line */ 683 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[133] = { 684 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 685 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 686 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 687 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 688 {0u, 12u, P1_0, P1_0_TCPWM0_LINE12}, 689 {2u, 4u, P1_0, P1_0_TCPWM0_LINE516}, 690 {0u, 11u, P1_1, P1_1_TCPWM0_LINE11}, 691 {2u, 5u, P1_1, P1_1_TCPWM0_LINE517}, 692 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 693 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 694 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 695 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 696 {0u, 3u, P2_4, P2_4_TCPWM0_LINE3}, 697 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 698 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 699 {1u, 3u, P3_2, P3_2_TCPWM0_LINE259}, 700 {1u, 2u, P3_3, P3_3_TCPWM0_LINE258}, 701 {1u, 1u, P3_4, P3_4_TCPWM0_LINE257}, 702 {0u, 4u, P4_0, P4_0_TCPWM0_LINE4}, 703 {0u, 5u, P4_1, P4_1_TCPWM0_LINE5}, 704 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 705 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 706 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 707 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 708 {0u, 13u, P5_4, P5_4_TCPWM0_LINE13}, 709 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 710 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 711 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 712 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 713 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 714 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 715 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 716 {0u, 3u, P6_7, P6_7_TCPWM0_LINE3}, 717 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 718 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 719 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 720 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 721 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 722 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 723 {1u, 7u, P7_6, P7_6_TCPWM0_LINE263}, 724 {0u, 18u, P7_7, P7_7_TCPWM0_LINE18}, 725 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 726 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 727 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 728 {0u, 22u, P8_3, P8_3_TCPWM0_LINE22}, 729 {0u, 24u, P9_0, P9_0_TCPWM0_LINE24}, 730 {0u, 25u, P9_1, P9_1_TCPWM0_LINE25}, 731 {0u, 28u, P10_0, P10_0_TCPWM0_LINE28}, 732 {0u, 29u, P10_1, P10_1_TCPWM0_LINE29}, 733 {0u, 30u, P10_2, P10_2_TCPWM0_LINE30}, 734 {0u, 31u, P10_3, P10_3_TCPWM0_LINE31}, 735 {0u, 32u, P10_4, P10_4_TCPWM0_LINE32}, 736 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 737 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 738 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 739 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 740 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 741 {0u, 41u, P12_5, P12_5_TCPWM0_LINE41}, 742 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 743 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 744 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 745 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 746 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 747 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 748 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 749 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 750 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 751 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 752 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 753 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 754 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 755 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 756 {2u, 7u, P14_2, P14_2_TCPWM0_LINE519}, 757 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 758 {0u, 52u, P14_4, P14_4_TCPWM0_LINE52}, 759 {0u, 53u, P14_5, P14_5_TCPWM0_LINE53}, 760 {0u, 56u, P15_0, P15_0_TCPWM0_LINE56}, 761 {0u, 57u, P15_1, P15_1_TCPWM0_LINE57}, 762 {0u, 58u, P15_2, P15_2_TCPWM0_LINE58}, 763 {0u, 59u, P15_3, P15_3_TCPWM0_LINE59}, 764 {0u, 60u, P16_0, P16_0_TCPWM0_LINE60}, 765 {2u, 0u, P16_0, P16_0_TCPWM0_LINE512}, 766 {0u, 61u, P16_1, P16_1_TCPWM0_LINE61}, 767 {0u, 62u, P16_2, P16_2_TCPWM0_LINE62}, 768 {2u, 1u, P16_2, P16_2_TCPWM0_LINE513}, 769 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 770 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 771 {2u, 2u, P17_1, P17_1_TCPWM0_LINE514}, 772 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 773 {0u, 58u, P17_3, P17_3_TCPWM0_LINE58}, 774 {2u, 3u, P17_3, P17_3_TCPWM0_LINE515}, 775 {0u, 57u, P17_4, P17_4_TCPWM0_LINE57}, 776 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 777 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 778 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 779 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 780 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 781 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 782 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 783 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 784 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 785 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 786 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 787 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 788 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 789 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 790 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 791 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 792 {0u, 29u, P19_4, P19_4_TCPWM0_LINE29}, 793 {0u, 30u, P20_0, P20_0_TCPWM0_LINE30}, 794 {0u, 49u, P20_1, P20_1_TCPWM0_LINE49}, 795 {0u, 48u, P20_2, P20_2_TCPWM0_LINE48}, 796 {0u, 47u, P20_3, P20_3_TCPWM0_LINE47}, 797 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 798 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 799 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 800 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 801 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 802 {0u, 36u, P21_6, P21_6_TCPWM0_LINE36}, 803 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 804 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 805 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 806 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 807 {0u, 30u, P22_4, P22_4_TCPWM0_LINE30}, 808 {0u, 29u, P22_5, P22_5_TCPWM0_LINE29}, 809 {0u, 28u, P22_6, P22_6_TCPWM0_LINE28}, 810 {1u, 8u, P23_0, P23_0_TCPWM0_LINE264}, 811 {1u, 9u, P23_1, P23_1_TCPWM0_LINE265}, 812 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 813 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 814 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 815 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 816 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 817 }; 818 819 /* Connections for: tcpwm_line_compl */ 820 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[133] = { 821 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 822 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 823 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 824 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 825 {0u, 13u, P1_0, P1_0_TCPWM0_LINE_COMPL13}, 826 {0u, 12u, P1_1, P1_1_TCPWM0_LINE_COMPL12}, 827 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 828 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 829 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 830 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 831 {0u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL4}, 832 {2u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL516}, 833 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 834 {2u, 6u, P3_0, P3_0_TCPWM0_LINE_COMPL518}, 835 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 836 {2u, 7u, P3_1, P3_1_TCPWM0_LINE_COMPL519}, 837 {0u, 0u, P3_2, P3_2_TCPWM0_LINE_COMPL0}, 838 {1u, 3u, P3_3, P3_3_TCPWM0_LINE_COMPL259}, 839 {1u, 2u, P3_4, P3_4_TCPWM0_LINE_COMPL258}, 840 {1u, 0u, P4_0, P4_0_TCPWM0_LINE_COMPL256}, 841 {0u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL4}, 842 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 843 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 844 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 845 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 846 {0u, 12u, P5_4, P5_4_TCPWM0_LINE_COMPL12}, 847 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 848 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 849 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 850 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 851 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 852 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 853 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 854 {1u, 3u, P6_7, P6_7_TCPWM0_LINE_COMPL259}, 855 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 856 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 857 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 858 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 859 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 860 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 861 {0u, 17u, P7_6, P7_6_TCPWM0_LINE_COMPL17}, 862 {1u, 7u, P7_7, P7_7_TCPWM0_LINE_COMPL263}, 863 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 864 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 865 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 866 {0u, 21u, P8_3, P8_3_TCPWM0_LINE_COMPL21}, 867 {0u, 23u, P9_0, P9_0_TCPWM0_LINE_COMPL23}, 868 {0u, 24u, P9_1, P9_1_TCPWM0_LINE_COMPL24}, 869 {0u, 27u, P10_0, P10_0_TCPWM0_LINE_COMPL27}, 870 {0u, 28u, P10_1, P10_1_TCPWM0_LINE_COMPL28}, 871 {0u, 29u, P10_2, P10_2_TCPWM0_LINE_COMPL29}, 872 {0u, 30u, P10_3, P10_3_TCPWM0_LINE_COMPL30}, 873 {0u, 31u, P10_4, P10_4_TCPWM0_LINE_COMPL31}, 874 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 875 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 876 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 877 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 878 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 879 {0u, 40u, P12_5, P12_5_TCPWM0_LINE_COMPL40}, 880 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 881 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 882 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 883 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 884 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 885 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 886 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 887 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 888 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 889 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 890 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 891 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 892 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 893 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 894 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 895 {2u, 7u, P14_3, P14_3_TCPWM0_LINE_COMPL519}, 896 {0u, 51u, P14_4, P14_4_TCPWM0_LINE_COMPL51}, 897 {0u, 52u, P14_5, P14_5_TCPWM0_LINE_COMPL52}, 898 {0u, 55u, P15_0, P15_0_TCPWM0_LINE_COMPL55}, 899 {0u, 56u, P15_1, P15_1_TCPWM0_LINE_COMPL56}, 900 {0u, 57u, P15_2, P15_2_TCPWM0_LINE_COMPL57}, 901 {0u, 58u, P15_3, P15_3_TCPWM0_LINE_COMPL58}, 902 {0u, 59u, P16_0, P16_0_TCPWM0_LINE_COMPL59}, 903 {0u, 60u, P16_1, P16_1_TCPWM0_LINE_COMPL60}, 904 {2u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL512}, 905 {0u, 61u, P16_2, P16_2_TCPWM0_LINE_COMPL61}, 906 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 907 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 908 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 909 {2u, 2u, P17_2, P17_2_TCPWM0_LINE_COMPL514}, 910 {0u, 59u, P17_3, P17_3_TCPWM0_LINE_COMPL59}, 911 {0u, 58u, P17_4, P17_4_TCPWM0_LINE_COMPL58}, 912 {2u, 3u, P17_4, P17_4_TCPWM0_LINE_COMPL515}, 913 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 914 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 915 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 916 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 917 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 918 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 919 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 920 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 921 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 922 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 923 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 924 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 925 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 926 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 927 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 928 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 929 {0u, 28u, P19_4, P19_4_TCPWM0_LINE_COMPL28}, 930 {0u, 29u, P20_0, P20_0_TCPWM0_LINE_COMPL29}, 931 {0u, 30u, P20_1, P20_1_TCPWM0_LINE_COMPL30}, 932 {0u, 49u, P20_2, P20_2_TCPWM0_LINE_COMPL49}, 933 {0u, 48u, P20_3, P20_3_TCPWM0_LINE_COMPL48}, 934 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 935 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 936 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 937 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 938 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 939 {0u, 37u, P21_6, P21_6_TCPWM0_LINE_COMPL37}, 940 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 941 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 942 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 943 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 944 {0u, 31u, P22_4, P22_4_TCPWM0_LINE_COMPL31}, 945 {0u, 30u, P22_5, P22_5_TCPWM0_LINE_COMPL30}, 946 {0u, 29u, P22_6, P22_6_TCPWM0_LINE_COMPL29}, 947 {0u, 27u, P23_0, P23_0_TCPWM0_LINE_COMPL27}, 948 {1u, 8u, P23_1, P23_1_TCPWM0_LINE_COMPL264}, 949 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 950 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 951 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 952 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 953 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 954 }; 955 956 /* Connections for: tcpwm_tr_one_cnt_in */ 957 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[259] = { 958 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 959 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 960 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 961 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 962 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 963 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 964 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 965 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 966 {0u, 36u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN36}, 967 {0u, 40u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN40}, 968 {0u, 33u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN33}, 969 {0u, 37u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN37}, 970 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 971 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 972 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 973 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 974 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 975 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 976 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 977 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 978 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 979 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 980 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 981 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 982 {0u, 9u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN9}, 983 {0u, 13u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN13}, 984 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 985 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 986 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 987 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 988 {0u, 1u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1}, 989 {3u, 9u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN777}, 990 {6u, 13u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1549}, 991 {3u, 6u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN774}, 992 {3u, 10u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN778}, 993 {6u, 16u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN1552}, 994 {3u, 3u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN771}, 995 {3u, 7u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN775}, 996 {6u, 19u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN1555}, 997 {0u, 12u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN12}, 998 {3u, 1u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN769}, 999 {0u, 13u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN13}, 1000 {0u, 15u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN15}, 1001 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 1002 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 1003 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 1004 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 1005 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 1006 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 1007 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 1008 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 1009 {0u, 37u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN37}, 1010 {0u, 39u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN39}, 1011 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 1012 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 1013 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 1014 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 1015 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 1016 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 1017 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 1018 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 1019 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 1020 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 1021 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 1022 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 1023 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 1024 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 1025 {0u, 9u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN9}, 1026 {3u, 10u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN778}, 1027 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 1028 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 1029 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 1030 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 1031 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 1032 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 1033 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 1034 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 1035 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 1036 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 1037 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 1038 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 1039 {0u, 52u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN52}, 1040 {3u, 21u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN789}, 1041 {0u, 54u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN54}, 1042 {3u, 22u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN790}, 1043 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 1044 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 1045 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 1046 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 1047 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 1048 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 1049 {0u, 64u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN64}, 1050 {0u, 66u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN66}, 1051 {0u, 70u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN70}, 1052 {0u, 72u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN72}, 1053 {0u, 73u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN73}, 1054 {0u, 75u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN75}, 1055 {0u, 82u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN82}, 1056 {0u, 84u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN84}, 1057 {0u, 85u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN85}, 1058 {0u, 87u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN87}, 1059 {0u, 88u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN88}, 1060 {0u, 90u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN90}, 1061 {0u, 91u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN91}, 1062 {0u, 93u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN93}, 1063 {0u, 94u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN94}, 1064 {0u, 96u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN96}, 1065 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 1066 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 1067 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 1068 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 1069 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 1070 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 1071 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1072 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1073 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1074 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1075 {0u, 121u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN121}, 1076 {0u, 123u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN123}, 1077 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1078 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1079 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1080 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1081 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1082 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1083 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1084 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1085 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1086 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1087 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1088 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1089 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1090 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1091 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1092 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1093 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1094 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1095 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1096 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1097 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 1098 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 1099 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 1100 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 1101 {0u, 154u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN154}, 1102 {0u, 156u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN156}, 1103 {6u, 12u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN1548}, 1104 {0u, 157u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN157}, 1105 {0u, 159u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN159}, 1106 {6u, 13u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN1549}, 1107 {0u, 166u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN166}, 1108 {0u, 168u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN168}, 1109 {6u, 18u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN1554}, 1110 {0u, 169u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN169}, 1111 {0u, 171u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN171}, 1112 {6u, 19u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN1555}, 1113 {0u, 172u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN172}, 1114 {0u, 174u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN174}, 1115 {6u, 21u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN1557}, 1116 {0u, 175u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN175}, 1117 {0u, 177u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN177}, 1118 {6u, 22u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN1558}, 1119 {0u, 178u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN178}, 1120 {0u, 180u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN180}, 1121 {0u, 181u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN181}, 1122 {0u, 183u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN183}, 1123 {0u, 184u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN184}, 1124 {0u, 186u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN186}, 1125 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 1126 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 1127 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 1128 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 1129 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 1130 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 1131 {0u, 174u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN174}, 1132 {0u, 178u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN178}, 1133 {0u, 171u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN171}, 1134 {0u, 175u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN175}, 1135 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1136 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1137 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1138 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1139 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1140 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1141 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1142 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1143 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1144 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1145 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1146 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1147 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1148 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1149 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1150 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1151 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1152 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1153 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1154 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1155 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1156 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1157 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1158 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1159 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1160 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1161 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1162 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1163 {0u, 85u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN85}, 1164 {0u, 87u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN87}, 1165 {6u, 6u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN1542}, 1166 {0u, 88u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN88}, 1167 {0u, 90u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN90}, 1168 {6u, 7u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN1543}, 1169 {0u, 91u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN91}, 1170 {0u, 147u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN147}, 1171 {6u, 9u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN1545}, 1172 {0u, 144u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN144}, 1173 {0u, 148u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN148}, 1174 {6u, 10u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN1546}, 1175 {0u, 141u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN141}, 1176 {0u, 145u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN145}, 1177 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1178 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1179 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1180 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1181 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1182 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1183 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1184 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1185 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1186 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1187 {0u, 108u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN108}, 1188 {0u, 112u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN112}, 1189 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 1190 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 1191 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1192 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1193 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1194 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1195 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1196 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1197 {0u, 90u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN90}, 1198 {0u, 94u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN94}, 1199 {0u, 87u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN87}, 1200 {0u, 91u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN91}, 1201 {0u, 84u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN84}, 1202 {0u, 88u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN88}, 1203 {0u, 82u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN82}, 1204 {3u, 24u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN792}, 1205 {3u, 25u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN793}, 1206 {3u, 27u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN795}, 1207 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1208 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1209 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1210 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1211 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1212 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1213 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1214 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1215 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1216 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1217 }; 1218 1219 #endif 1220
