1 /***************************************************************************//** 2 * \file cyhal_tviibe2m_176_lqfp.c 3 * 4 * \brief 5 * TVIIBE2M device GPIO HAL header for 176-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE2M_176_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe2m_176_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[15] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 39 {0u, 1u, P4_4, P4_4_CANFD0_TTCAN_RX1}, 40 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 41 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 42 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 43 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 44 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 45 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 46 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 47 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 48 {1u, 2u, P20_4, P20_4_CANFD1_TTCAN_RX2}, 49 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 50 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 51 }; 52 53 /* Connections for: canfd_ttcan_tx */ 54 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[15] = { 55 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 56 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 57 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 58 {0u, 1u, P4_3, P4_3_CANFD0_TTCAN_TX1}, 59 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 60 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 61 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 62 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 63 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 64 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 65 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 66 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 67 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 68 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 69 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 70 }; 71 72 /* Connections for: cpuss_cal_sup_nz */ 73 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3] = { 74 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 75 {0u, 0u, P21_7, P21_7_CPUSS_CAL_SUP_NZ}, 76 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 77 }; 78 79 /* Connections for: cpuss_clk_fm_pump */ 80 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 81 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 82 }; 83 84 /* Connections for: cpuss_fault_out */ 85 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8] = { 86 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 87 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 88 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 89 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 90 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 91 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 92 {0u, 2u, P23_2, P23_2_CPUSS_FAULT_OUT2}, 93 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 94 }; 95 96 /* Connections for: cpuss_swj_swclk_tclk */ 97 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 98 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 99 }; 100 101 /* Connections for: cpuss_swj_swdio_tms */ 102 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 103 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 104 }; 105 106 /* Connections for: cpuss_swj_swdoe_tdi */ 107 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 108 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 109 }; 110 111 /* Connections for: cpuss_swj_swo_tdo */ 112 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 113 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 114 }; 115 116 /* Connections for: cpuss_swj_trstn */ 117 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 118 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 119 }; 120 121 /* Connections for: cpuss_trace_clock */ 122 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 123 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 124 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 125 }; 126 127 /* Connections for: cpuss_trace_data */ 128 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 129 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 130 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 131 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 132 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 133 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 134 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 135 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 136 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 137 }; 138 139 /* Connections for: cxpi_cxpi_en */ 140 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[8] = { 141 {0u, 0u, P7_2, P7_2_CXPI0_CXPI_EN0}, 142 {0u, 0u, P10_7, P10_7_CXPI0_CXPI_EN0}, 143 {0u, 1u, P13_2, P13_2_CXPI0_CXPI_EN1}, 144 {0u, 2u, P13_7, P13_7_CXPI0_CXPI_EN2}, 145 {0u, 2u, P14_7, P14_7_CXPI0_CXPI_EN2}, 146 {0u, 1u, P15_2, P15_2_CXPI0_CXPI_EN1}, 147 {0u, 3u, P19_3, P19_3_CXPI0_CXPI_EN3}, 148 {0u, 3u, P20_7, P20_7_CXPI0_CXPI_EN3}, 149 }; 150 151 /* Connections for: cxpi_cxpi_rx */ 152 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[8] = { 153 {0u, 0u, P7_0, P7_0_CXPI0_CXPI_RX0}, 154 {0u, 0u, P10_5, P10_5_CXPI0_CXPI_RX0}, 155 {0u, 1u, P13_0, P13_0_CXPI0_CXPI_RX1}, 156 {0u, 2u, P13_5, P13_5_CXPI0_CXPI_RX2}, 157 {0u, 2u, P14_5, P14_5_CXPI0_CXPI_RX2}, 158 {0u, 1u, P15_0, P15_0_CXPI0_CXPI_RX1}, 159 {0u, 3u, P19_1, P19_1_CXPI0_CXPI_RX3}, 160 {0u, 3u, P20_5, P20_5_CXPI0_CXPI_RX3}, 161 }; 162 163 /* Connections for: cxpi_cxpi_tx */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[8] = { 165 {0u, 0u, P7_1, P7_1_CXPI0_CXPI_TX0}, 166 {0u, 0u, P10_6, P10_6_CXPI0_CXPI_TX0}, 167 {0u, 1u, P13_1, P13_1_CXPI0_CXPI_TX1}, 168 {0u, 2u, P13_6, P13_6_CXPI0_CXPI_TX2}, 169 {0u, 2u, P14_6, P14_6_CXPI0_CXPI_TX2}, 170 {0u, 1u, P15_1, P15_1_CXPI0_CXPI_TX1}, 171 {0u, 3u, P19_2, P19_2_CXPI0_CXPI_TX3}, 172 {0u, 3u, P20_6, P20_6_CXPI0_CXPI_TX3}, 173 }; 174 175 /* Connections for: lin_lin_en */ 176 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[21] = { 177 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 178 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 179 {0u, 5u, P2_5, P2_5_LIN0_LIN_EN5}, 180 {0u, 1u, P4_2, P4_2_LIN0_LIN_EN1}, 181 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 182 {0u, 2u, P5_5, P5_5_LIN0_LIN_EN2}, 183 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 184 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 185 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 186 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 187 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 188 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 189 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 190 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 191 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 192 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 193 {0u, 11u, P16_2, P16_2_LIN0_LIN_EN11}, 194 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 195 {0u, 0u, P21_7, P21_7_LIN0_LIN_EN0}, 196 {0u, 7u, P22_7, P22_7_LIN0_LIN_EN7}, 197 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 198 }; 199 200 /* Connections for: lin_lin_rx */ 201 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[21] = { 202 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 203 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 204 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 205 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 206 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 207 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 208 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 209 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 210 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 211 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 212 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 213 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 214 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 215 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 216 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 217 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 218 {0u, 11u, P16_0, P16_0_LIN0_LIN_RX11}, 219 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 220 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 221 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 222 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 223 }; 224 225 /* Connections for: lin_lin_tx */ 226 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[21] = { 227 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 228 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 229 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 230 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 231 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 232 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 233 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 234 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 235 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 236 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 237 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 238 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 239 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 240 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 241 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 242 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 243 {0u, 11u, P16_1, P16_1_LIN0_LIN_TX11}, 244 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 245 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 246 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 247 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 248 }; 249 250 /* Connections for: pass_sar_ext_mux_en */ 251 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3] = { 252 {0u, 0u, P4_3, P4_3_PASS0_SAR_EXT_MUX_EN0}, 253 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 254 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 255 }; 256 257 /* Connections for: pass_sar_ext_mux_sel */ 258 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9] = { 259 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 260 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 261 {0u, 2u, P4_2, P4_2_PASS0_SAR_EXT_MUX_SEL2}, 262 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 263 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 264 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 265 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 266 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 267 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 268 }; 269 270 /* Connections for: pass_sarmux_pads */ 271 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[64] = { 272 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 273 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 274 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 275 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 276 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 277 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 278 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 279 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 280 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 281 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 282 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 283 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 284 {0u, 12u, P7_4, HSIOM_SEL_GPIO}, 285 {0u, 13u, P7_5, HSIOM_SEL_GPIO}, 286 {0u, 14u, P7_6, HSIOM_SEL_GPIO}, 287 {0u, 15u, P7_7, HSIOM_SEL_GPIO}, 288 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 289 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 290 {0u, 18u, P8_3, HSIOM_SEL_GPIO}, 291 {0u, 19u, P8_4, HSIOM_SEL_GPIO}, 292 {0u, 20u, P9_0, HSIOM_SEL_GPIO}, 293 {0u, 21u, P9_1, HSIOM_SEL_GPIO}, 294 {0u, 22u, P9_2, HSIOM_SEL_GPIO}, 295 {0u, 23u, P9_3, HSIOM_SEL_GPIO}, 296 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 297 {1u, 1u, P10_5, HSIOM_SEL_GPIO}, 298 {1u, 2u, P10_6, HSIOM_SEL_GPIO}, 299 {1u, 3u, P10_7, HSIOM_SEL_GPIO}, 300 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 301 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 302 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 303 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 304 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 305 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 306 {1u, 10u, P12_6, HSIOM_SEL_GPIO}, 307 {1u, 11u, P12_7, HSIOM_SEL_GPIO}, 308 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 309 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 310 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 311 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 312 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 313 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 314 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 315 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 316 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 317 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 318 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 319 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 320 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 321 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 322 {1u, 26u, P14_6, HSIOM_SEL_GPIO}, 323 {1u, 27u, P14_7, HSIOM_SEL_GPIO}, 324 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 325 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 326 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 327 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 328 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 329 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 330 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 331 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 332 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 333 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 334 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 335 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 336 }; 337 338 /* Connections for: peri_tr_io_input */ 339 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 340 to know the index of the input or output trigger line. Store that in the channel_num field 341 instead. */ 342 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[32] = { 343 {0u, 0u, P1_2, P1_2_PERI_TR_IO_INPUT0}, 344 {0u, 1u, P1_3, P1_3_PERI_TR_IO_INPUT1}, 345 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 346 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 347 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 348 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 349 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 350 {0u, 7u, P2_5, P2_5_PERI_TR_IO_INPUT7}, 351 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 352 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 353 {0u, 12u, P4_2, P4_2_PERI_TR_IO_INPUT12}, 354 {0u, 13u, P4_3, P4_3_PERI_TR_IO_INPUT13}, 355 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 356 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 357 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 358 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 359 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 360 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 361 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 362 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 363 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 364 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 365 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 366 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 367 {0u, 24u, P14_6, P14_6_PERI_TR_IO_INPUT24}, 368 {0u, 25u, P14_7, P14_7_PERI_TR_IO_INPUT25}, 369 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 370 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 371 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 372 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 373 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 374 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 375 }; 376 377 /* Connections for: peri_tr_io_output */ 378 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 379 to know the index of the input or output trigger line. Store that in the channel_num field 380 instead. */ 381 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6] = { 382 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 383 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 384 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 385 {0u, 1u, P8_4, P8_4_PERI_TR_IO_OUTPUT1}, 386 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 387 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 388 }; 389 390 /* Connections for: scb_i2c_scl */ 391 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17] = { 392 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 393 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 394 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 395 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 396 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 397 {5u, 0u, P4_2, P4_2_SCB5_I2C_SCL}, 398 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 399 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 400 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 401 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 402 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 403 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 404 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 405 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 406 {1u, 0u, P20_5, P20_5_SCB1_I2C_SCL}, 407 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 408 {7u, 0u, P23_2, P23_2_SCB7_I2C_SCL}, 409 }; 410 411 /* Connections for: scb_i2c_sda */ 412 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17] = { 413 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 414 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 415 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 416 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 417 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 418 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 419 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 420 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 421 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 422 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 423 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 424 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 425 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 426 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 427 {1u, 0u, P20_4, P20_4_SCB1_I2C_SDA}, 428 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 429 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 430 }; 431 432 /* Connections for: scb_spi_m_clk */ 433 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16] = { 434 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 435 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 436 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 437 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 438 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 439 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 440 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 441 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 442 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 443 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 444 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 445 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 446 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 447 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 448 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 449 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 450 }; 451 452 /* Connections for: scb_spi_m_miso */ 453 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[16] = { 454 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 455 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 456 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 457 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 458 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 459 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 460 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 461 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 462 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 463 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 464 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 465 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 466 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 467 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 468 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 469 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 470 }; 471 472 /* Connections for: scb_spi_m_mosi */ 473 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[16] = { 474 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 475 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 476 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 477 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 478 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 479 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 480 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 481 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 482 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 483 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 484 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 485 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 486 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 487 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 488 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 489 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 490 }; 491 492 /* Connections for: scb_spi_m_select0 */ 493 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16] = { 494 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 495 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 496 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 497 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 498 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 499 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 500 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 501 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 502 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 503 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 504 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 505 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 506 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 507 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 508 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 509 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 510 }; 511 512 /* Connections for: scb_spi_m_select1 */ 513 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[15] = { 514 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 515 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 516 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 517 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 518 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 519 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 520 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 521 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 522 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 523 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 524 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 525 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 526 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 527 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 528 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 529 }; 530 531 /* Connections for: scb_spi_m_select2 */ 532 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[15] = { 533 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 534 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 535 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 536 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 537 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 538 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 539 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 540 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 541 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 542 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 543 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 544 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 545 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 546 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 547 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 548 }; 549 550 /* Connections for: scb_spi_m_select3 */ 551 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = { 552 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 553 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 554 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 555 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 556 }; 557 558 /* Connections for: scb_spi_s_clk */ 559 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16] = { 560 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 561 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 562 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 563 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 564 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 565 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 566 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 567 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 568 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 569 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 570 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 571 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 572 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 573 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 574 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 575 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 576 }; 577 578 /* Connections for: scb_spi_s_miso */ 579 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[16] = { 580 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 581 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 582 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 583 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 584 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 585 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 586 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 587 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 588 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 589 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 590 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 591 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 592 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 593 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 594 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 595 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 596 }; 597 598 /* Connections for: scb_spi_s_mosi */ 599 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[16] = { 600 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 601 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 602 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 603 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 604 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 605 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 606 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 607 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 608 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 609 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 610 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 611 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 612 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 613 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 614 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 615 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 616 }; 617 618 /* Connections for: scb_spi_s_select0 */ 619 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16] = { 620 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 621 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 622 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 623 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 624 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 625 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 626 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 627 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 628 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 629 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 630 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 631 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 632 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 633 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 634 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 635 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 636 }; 637 638 /* Connections for: scb_spi_s_select1 */ 639 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[15] = { 640 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 641 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 642 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 643 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 644 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 645 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 646 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 647 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 648 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 649 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 650 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 651 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 652 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 653 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 654 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 655 }; 656 657 /* Connections for: scb_spi_s_select2 */ 658 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[15] = { 659 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 660 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 661 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 662 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 663 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 664 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 665 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 666 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 667 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 668 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 669 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 670 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 671 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 672 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 673 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 674 }; 675 676 /* Connections for: scb_spi_s_select3 */ 677 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = { 678 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 679 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 680 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 681 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 682 }; 683 684 /* Connections for: scb_uart_cts */ 685 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15] = { 686 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 687 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 688 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 689 {5u, 0u, P4_3, P4_3_SCB5_UART_CTS}, 690 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 691 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 692 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 693 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 694 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 695 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 696 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 697 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 698 {1u, 0u, P20_6, P20_6_SCB1_UART_CTS}, 699 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 700 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 701 }; 702 703 /* Connections for: scb_uart_rts */ 704 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15] = { 705 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 706 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 707 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 708 {5u, 0u, P4_2, P4_2_SCB5_UART_RTS}, 709 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 710 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 711 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 712 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 713 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 714 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 715 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 716 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 717 {1u, 0u, P20_5, P20_5_SCB1_UART_RTS}, 718 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 719 {7u, 0u, P23_2, P23_2_SCB7_UART_RTS}, 720 }; 721 722 /* Connections for: scb_uart_rx */ 723 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15] = { 724 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 725 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 726 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 727 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 728 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 729 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 730 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 731 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 732 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 733 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 734 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 735 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 736 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 737 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 738 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 739 }; 740 741 /* Connections for: scb_uart_tx */ 742 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15] = { 743 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 744 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 745 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 746 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 747 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 748 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 749 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 750 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 751 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 752 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 753 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 754 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 755 {1u, 0u, P20_4, P20_4_SCB1_UART_TX}, 756 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 757 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 758 }; 759 760 /* Connections for: tcpwm_line */ 761 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[165] = { 762 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 763 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 764 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 765 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 766 {0u, 12u, P1_0, P1_0_TCPWM0_LINE12}, 767 {2u, 4u, P1_0, P1_0_TCPWM0_LINE516}, 768 {0u, 11u, P1_1, P1_1_TCPWM0_LINE11}, 769 {2u, 5u, P1_1, P1_1_TCPWM0_LINE517}, 770 {0u, 10u, P1_2, P1_2_TCPWM0_LINE10}, 771 {2u, 6u, P1_2, P1_2_TCPWM0_LINE518}, 772 {0u, 8u, P1_3, P1_3_TCPWM0_LINE8}, 773 {2u, 7u, P1_3, P1_3_TCPWM0_LINE519}, 774 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 775 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 776 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 777 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 778 {0u, 3u, P2_4, P2_4_TCPWM0_LINE3}, 779 {0u, 2u, P2_5, P2_5_TCPWM0_LINE2}, 780 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 781 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 782 {1u, 3u, P3_2, P3_2_TCPWM0_LINE259}, 783 {1u, 2u, P3_3, P3_3_TCPWM0_LINE258}, 784 {1u, 1u, P3_4, P3_4_TCPWM0_LINE257}, 785 {1u, 0u, P3_5, P3_5_TCPWM0_LINE256}, 786 {0u, 4u, P4_0, P4_0_TCPWM0_LINE4}, 787 {0u, 5u, P4_1, P4_1_TCPWM0_LINE5}, 788 {0u, 6u, P4_2, P4_2_TCPWM0_LINE6}, 789 {0u, 7u, P4_3, P4_3_TCPWM0_LINE7}, 790 {0u, 8u, P4_4, P4_4_TCPWM0_LINE8}, 791 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 792 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 793 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 794 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 795 {0u, 13u, P5_4, P5_4_TCPWM0_LINE13}, 796 {0u, 14u, P5_5, P5_5_TCPWM0_LINE14}, 797 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 798 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 799 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 800 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 801 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 802 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 803 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 804 {0u, 3u, P6_7, P6_7_TCPWM0_LINE3}, 805 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 806 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 807 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 808 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 809 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 810 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 811 {1u, 7u, P7_6, P7_6_TCPWM0_LINE263}, 812 {0u, 18u, P7_7, P7_7_TCPWM0_LINE18}, 813 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 814 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 815 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 816 {0u, 22u, P8_3, P8_3_TCPWM0_LINE22}, 817 {0u, 23u, P8_4, P8_4_TCPWM0_LINE23}, 818 {0u, 24u, P9_0, P9_0_TCPWM0_LINE24}, 819 {0u, 25u, P9_1, P9_1_TCPWM0_LINE25}, 820 {0u, 26u, P9_2, P9_2_TCPWM0_LINE26}, 821 {0u, 27u, P9_3, P9_3_TCPWM0_LINE27}, 822 {0u, 28u, P10_0, P10_0_TCPWM0_LINE28}, 823 {0u, 29u, P10_1, P10_1_TCPWM0_LINE29}, 824 {0u, 30u, P10_2, P10_2_TCPWM0_LINE30}, 825 {0u, 31u, P10_3, P10_3_TCPWM0_LINE31}, 826 {0u, 32u, P10_4, P10_4_TCPWM0_LINE32}, 827 {0u, 33u, P10_5, P10_5_TCPWM0_LINE33}, 828 {0u, 34u, P10_6, P10_6_TCPWM0_LINE34}, 829 {0u, 35u, P10_7, P10_7_TCPWM0_LINE35}, 830 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 831 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 832 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 833 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 834 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 835 {0u, 41u, P12_5, P12_5_TCPWM0_LINE41}, 836 {0u, 42u, P12_6, P12_6_TCPWM0_LINE42}, 837 {0u, 43u, P12_7, P12_7_TCPWM0_LINE43}, 838 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 839 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 840 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 841 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 842 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 843 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 844 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 845 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 846 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 847 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 848 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 849 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 850 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 851 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 852 {2u, 7u, P14_2, P14_2_TCPWM0_LINE519}, 853 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 854 {0u, 52u, P14_4, P14_4_TCPWM0_LINE52}, 855 {0u, 53u, P14_5, P14_5_TCPWM0_LINE53}, 856 {0u, 54u, P14_6, P14_6_TCPWM0_LINE54}, 857 {0u, 55u, P14_7, P14_7_TCPWM0_LINE55}, 858 {0u, 56u, P15_0, P15_0_TCPWM0_LINE56}, 859 {0u, 57u, P15_1, P15_1_TCPWM0_LINE57}, 860 {0u, 58u, P15_2, P15_2_TCPWM0_LINE58}, 861 {0u, 59u, P15_3, P15_3_TCPWM0_LINE59}, 862 {0u, 60u, P16_0, P16_0_TCPWM0_LINE60}, 863 {2u, 0u, P16_0, P16_0_TCPWM0_LINE512}, 864 {0u, 61u, P16_1, P16_1_TCPWM0_LINE61}, 865 {0u, 62u, P16_2, P16_2_TCPWM0_LINE62}, 866 {2u, 1u, P16_2, P16_2_TCPWM0_LINE513}, 867 {0u, 62u, P16_3, P16_3_TCPWM0_LINE62}, 868 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 869 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 870 {2u, 2u, P17_1, P17_1_TCPWM0_LINE514}, 871 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 872 {0u, 58u, P17_3, P17_3_TCPWM0_LINE58}, 873 {2u, 3u, P17_3, P17_3_TCPWM0_LINE515}, 874 {0u, 57u, P17_4, P17_4_TCPWM0_LINE57}, 875 {0u, 56u, P17_5, P17_5_TCPWM0_LINE56}, 876 {1u, 4u, P17_6, P17_6_TCPWM0_LINE260}, 877 {1u, 5u, P17_7, P17_7_TCPWM0_LINE261}, 878 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 879 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 880 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 881 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 882 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 883 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 884 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 885 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 886 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 887 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 888 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 889 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 890 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 891 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 892 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 893 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 894 {0u, 29u, P19_4, P19_4_TCPWM0_LINE29}, 895 {0u, 30u, P20_0, P20_0_TCPWM0_LINE30}, 896 {0u, 49u, P20_1, P20_1_TCPWM0_LINE49}, 897 {0u, 48u, P20_2, P20_2_TCPWM0_LINE48}, 898 {0u, 47u, P20_3, P20_3_TCPWM0_LINE47}, 899 {0u, 46u, P20_4, P20_4_TCPWM0_LINE46}, 900 {0u, 45u, P20_5, P20_5_TCPWM0_LINE45}, 901 {0u, 44u, P20_6, P20_6_TCPWM0_LINE44}, 902 {0u, 43u, P20_7, P20_7_TCPWM0_LINE43}, 903 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 904 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 905 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 906 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 907 {0u, 38u, P21_4, P21_4_TCPWM0_LINE38}, 908 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 909 {0u, 36u, P21_6, P21_6_TCPWM0_LINE36}, 910 {0u, 35u, P21_7, P21_7_TCPWM0_LINE35}, 911 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 912 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 913 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 914 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 915 {0u, 30u, P22_4, P22_4_TCPWM0_LINE30}, 916 {0u, 29u, P22_5, P22_5_TCPWM0_LINE29}, 917 {0u, 28u, P22_6, P22_6_TCPWM0_LINE28}, 918 {0u, 27u, P22_7, P22_7_TCPWM0_LINE27}, 919 {1u, 8u, P23_0, P23_0_TCPWM0_LINE264}, 920 {1u, 9u, P23_1, P23_1_TCPWM0_LINE265}, 921 {1u, 10u, P23_2, P23_2_TCPWM0_LINE266}, 922 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 923 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 924 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 925 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 926 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 927 }; 928 929 /* Connections for: tcpwm_line_compl */ 930 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[165] = { 931 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 932 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 933 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 934 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 935 {0u, 13u, P1_0, P1_0_TCPWM0_LINE_COMPL13}, 936 {0u, 12u, P1_1, P1_1_TCPWM0_LINE_COMPL12}, 937 {0u, 11u, P1_2, P1_2_TCPWM0_LINE_COMPL11}, 938 {0u, 10u, P1_3, P1_3_TCPWM0_LINE_COMPL10}, 939 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 940 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 941 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 942 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 943 {0u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL4}, 944 {2u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL516}, 945 {0u, 3u, P2_5, P2_5_TCPWM0_LINE_COMPL3}, 946 {2u, 5u, P2_5, P2_5_TCPWM0_LINE_COMPL517}, 947 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 948 {2u, 6u, P3_0, P3_0_TCPWM0_LINE_COMPL518}, 949 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 950 {2u, 7u, P3_1, P3_1_TCPWM0_LINE_COMPL519}, 951 {0u, 0u, P3_2, P3_2_TCPWM0_LINE_COMPL0}, 952 {1u, 3u, P3_3, P3_3_TCPWM0_LINE_COMPL259}, 953 {1u, 2u, P3_4, P3_4_TCPWM0_LINE_COMPL258}, 954 {1u, 1u, P3_5, P3_5_TCPWM0_LINE_COMPL257}, 955 {1u, 0u, P4_0, P4_0_TCPWM0_LINE_COMPL256}, 956 {0u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL4}, 957 {0u, 5u, P4_2, P4_2_TCPWM0_LINE_COMPL5}, 958 {0u, 6u, P4_3, P4_3_TCPWM0_LINE_COMPL6}, 959 {0u, 7u, P4_4, P4_4_TCPWM0_LINE_COMPL7}, 960 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 961 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 962 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 963 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 964 {0u, 12u, P5_4, P5_4_TCPWM0_LINE_COMPL12}, 965 {0u, 13u, P5_5, P5_5_TCPWM0_LINE_COMPL13}, 966 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 967 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 968 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 969 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 970 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 971 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 972 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 973 {1u, 3u, P6_7, P6_7_TCPWM0_LINE_COMPL259}, 974 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 975 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 976 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 977 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 978 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 979 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 980 {0u, 17u, P7_6, P7_6_TCPWM0_LINE_COMPL17}, 981 {1u, 7u, P7_7, P7_7_TCPWM0_LINE_COMPL263}, 982 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 983 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 984 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 985 {0u, 21u, P8_3, P8_3_TCPWM0_LINE_COMPL21}, 986 {0u, 22u, P8_4, P8_4_TCPWM0_LINE_COMPL22}, 987 {0u, 23u, P9_0, P9_0_TCPWM0_LINE_COMPL23}, 988 {0u, 24u, P9_1, P9_1_TCPWM0_LINE_COMPL24}, 989 {0u, 25u, P9_2, P9_2_TCPWM0_LINE_COMPL25}, 990 {0u, 26u, P9_3, P9_3_TCPWM0_LINE_COMPL26}, 991 {0u, 27u, P10_0, P10_0_TCPWM0_LINE_COMPL27}, 992 {0u, 28u, P10_1, P10_1_TCPWM0_LINE_COMPL28}, 993 {0u, 29u, P10_2, P10_2_TCPWM0_LINE_COMPL29}, 994 {0u, 30u, P10_3, P10_3_TCPWM0_LINE_COMPL30}, 995 {0u, 31u, P10_4, P10_4_TCPWM0_LINE_COMPL31}, 996 {0u, 32u, P10_5, P10_5_TCPWM0_LINE_COMPL32}, 997 {0u, 33u, P10_6, P10_6_TCPWM0_LINE_COMPL33}, 998 {0u, 34u, P10_7, P10_7_TCPWM0_LINE_COMPL34}, 999 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 1000 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 1001 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 1002 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 1003 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 1004 {0u, 40u, P12_5, P12_5_TCPWM0_LINE_COMPL40}, 1005 {0u, 41u, P12_6, P12_6_TCPWM0_LINE_COMPL41}, 1006 {0u, 42u, P12_7, P12_7_TCPWM0_LINE_COMPL42}, 1007 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 1008 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 1009 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 1010 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 1011 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 1012 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 1013 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 1014 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 1015 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 1016 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 1017 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 1018 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 1019 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 1020 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 1021 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 1022 {2u, 7u, P14_3, P14_3_TCPWM0_LINE_COMPL519}, 1023 {0u, 51u, P14_4, P14_4_TCPWM0_LINE_COMPL51}, 1024 {0u, 52u, P14_5, P14_5_TCPWM0_LINE_COMPL52}, 1025 {0u, 53u, P14_6, P14_6_TCPWM0_LINE_COMPL53}, 1026 {0u, 54u, P14_7, P14_7_TCPWM0_LINE_COMPL54}, 1027 {0u, 55u, P15_0, P15_0_TCPWM0_LINE_COMPL55}, 1028 {0u, 56u, P15_1, P15_1_TCPWM0_LINE_COMPL56}, 1029 {0u, 57u, P15_2, P15_2_TCPWM0_LINE_COMPL57}, 1030 {0u, 58u, P15_3, P15_3_TCPWM0_LINE_COMPL58}, 1031 {0u, 59u, P16_0, P16_0_TCPWM0_LINE_COMPL59}, 1032 {0u, 60u, P16_1, P16_1_TCPWM0_LINE_COMPL60}, 1033 {2u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL512}, 1034 {0u, 61u, P16_2, P16_2_TCPWM0_LINE_COMPL61}, 1035 {0u, 62u, P16_3, P16_3_TCPWM0_LINE_COMPL62}, 1036 {2u, 1u, P16_3, P16_3_TCPWM0_LINE_COMPL513}, 1037 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 1038 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 1039 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 1040 {2u, 2u, P17_2, P17_2_TCPWM0_LINE_COMPL514}, 1041 {0u, 59u, P17_3, P17_3_TCPWM0_LINE_COMPL59}, 1042 {0u, 58u, P17_4, P17_4_TCPWM0_LINE_COMPL58}, 1043 {2u, 3u, P17_4, P17_4_TCPWM0_LINE_COMPL515}, 1044 {0u, 57u, P17_5, P17_5_TCPWM0_LINE_COMPL57}, 1045 {0u, 56u, P17_6, P17_6_TCPWM0_LINE_COMPL56}, 1046 {1u, 4u, P17_7, P17_7_TCPWM0_LINE_COMPL260}, 1047 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 1048 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 1049 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 1050 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 1051 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 1052 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 1053 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 1054 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 1055 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 1056 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 1057 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 1058 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 1059 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 1060 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 1061 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 1062 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 1063 {0u, 28u, P19_4, P19_4_TCPWM0_LINE_COMPL28}, 1064 {0u, 29u, P20_0, P20_0_TCPWM0_LINE_COMPL29}, 1065 {0u, 30u, P20_1, P20_1_TCPWM0_LINE_COMPL30}, 1066 {0u, 49u, P20_2, P20_2_TCPWM0_LINE_COMPL49}, 1067 {0u, 48u, P20_3, P20_3_TCPWM0_LINE_COMPL48}, 1068 {0u, 47u, P20_4, P20_4_TCPWM0_LINE_COMPL47}, 1069 {0u, 46u, P20_5, P20_5_TCPWM0_LINE_COMPL46}, 1070 {0u, 45u, P20_6, P20_6_TCPWM0_LINE_COMPL45}, 1071 {0u, 44u, P20_7, P20_7_TCPWM0_LINE_COMPL44}, 1072 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 1073 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 1074 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 1075 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 1076 {0u, 39u, P21_4, P21_4_TCPWM0_LINE_COMPL39}, 1077 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 1078 {0u, 37u, P21_6, P21_6_TCPWM0_LINE_COMPL37}, 1079 {0u, 36u, P21_7, P21_7_TCPWM0_LINE_COMPL36}, 1080 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 1081 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 1082 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 1083 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 1084 {0u, 31u, P22_4, P22_4_TCPWM0_LINE_COMPL31}, 1085 {0u, 30u, P22_5, P22_5_TCPWM0_LINE_COMPL30}, 1086 {0u, 29u, P22_6, P22_6_TCPWM0_LINE_COMPL29}, 1087 {0u, 28u, P22_7, P22_7_TCPWM0_LINE_COMPL28}, 1088 {0u, 27u, P23_0, P23_0_TCPWM0_LINE_COMPL27}, 1089 {1u, 8u, P23_1, P23_1_TCPWM0_LINE_COMPL264}, 1090 {1u, 9u, P23_2, P23_2_TCPWM0_LINE_COMPL265}, 1091 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 1092 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 1093 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 1094 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 1095 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 1096 }; 1097 1098 /* Connections for: tcpwm_tr_one_cnt_in */ 1099 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[322] = { 1100 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 1101 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 1102 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 1103 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 1104 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 1105 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 1106 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 1107 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 1108 {0u, 36u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN36}, 1109 {0u, 40u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN40}, 1110 {0u, 33u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN33}, 1111 {0u, 37u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN37}, 1112 {0u, 30u, P1_2, P1_2_TCPWM0_TR_ONE_CNT_IN30}, 1113 {0u, 34u, P1_2, P1_2_TCPWM0_TR_ONE_CNT_IN34}, 1114 {0u, 24u, P1_3, P1_3_TCPWM0_TR_ONE_CNT_IN24}, 1115 {0u, 31u, P1_3, P1_3_TCPWM0_TR_ONE_CNT_IN31}, 1116 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 1117 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 1118 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 1119 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 1120 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 1121 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 1122 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 1123 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 1124 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 1125 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 1126 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 1127 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 1128 {0u, 9u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN9}, 1129 {0u, 13u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN13}, 1130 {0u, 6u, P2_5, P2_5_TCPWM0_TR_ONE_CNT_IN6}, 1131 {0u, 10u, P2_5, P2_5_TCPWM0_TR_ONE_CNT_IN10}, 1132 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 1133 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 1134 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 1135 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 1136 {0u, 1u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1}, 1137 {3u, 9u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN777}, 1138 {6u, 13u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1549}, 1139 {3u, 6u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN774}, 1140 {3u, 10u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN778}, 1141 {6u, 16u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN1552}, 1142 {3u, 3u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN771}, 1143 {3u, 7u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN775}, 1144 {6u, 19u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN1555}, 1145 {3u, 0u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN768}, 1146 {3u, 4u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN772}, 1147 {6u, 22u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN1558}, 1148 {0u, 12u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN12}, 1149 {3u, 1u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN769}, 1150 {0u, 13u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN13}, 1151 {0u, 15u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN15}, 1152 {0u, 16u, P4_2, P4_2_TCPWM0_TR_ONE_CNT_IN16}, 1153 {0u, 18u, P4_2, P4_2_TCPWM0_TR_ONE_CNT_IN18}, 1154 {0u, 19u, P4_3, P4_3_TCPWM0_TR_ONE_CNT_IN19}, 1155 {0u, 21u, P4_3, P4_3_TCPWM0_TR_ONE_CNT_IN21}, 1156 {0u, 22u, P4_4, P4_4_TCPWM0_TR_ONE_CNT_IN22}, 1157 {0u, 24u, P4_4, P4_4_TCPWM0_TR_ONE_CNT_IN24}, 1158 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 1159 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 1160 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 1161 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 1162 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 1163 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 1164 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 1165 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 1166 {0u, 37u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN37}, 1167 {0u, 39u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN39}, 1168 {0u, 40u, P5_5, P5_5_TCPWM0_TR_ONE_CNT_IN40}, 1169 {0u, 42u, P5_5, P5_5_TCPWM0_TR_ONE_CNT_IN42}, 1170 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 1171 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 1172 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 1173 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 1174 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 1175 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 1176 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 1177 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 1178 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 1179 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 1180 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 1181 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 1182 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 1183 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 1184 {0u, 9u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN9}, 1185 {3u, 10u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN778}, 1186 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 1187 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 1188 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 1189 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 1190 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 1191 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 1192 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 1193 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 1194 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 1195 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 1196 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 1197 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 1198 {0u, 52u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN52}, 1199 {3u, 21u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN789}, 1200 {0u, 54u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN54}, 1201 {3u, 22u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN790}, 1202 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 1203 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 1204 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 1205 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 1206 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 1207 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 1208 {0u, 64u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN64}, 1209 {0u, 66u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN66}, 1210 {0u, 67u, P8_4, P8_4_TCPWM0_TR_ONE_CNT_IN67}, 1211 {0u, 69u, P8_4, P8_4_TCPWM0_TR_ONE_CNT_IN69}, 1212 {0u, 70u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN70}, 1213 {0u, 72u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN72}, 1214 {0u, 73u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN73}, 1215 {0u, 75u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN75}, 1216 {0u, 76u, P9_2, P9_2_TCPWM0_TR_ONE_CNT_IN76}, 1217 {0u, 78u, P9_2, P9_2_TCPWM0_TR_ONE_CNT_IN78}, 1218 {0u, 79u, P9_3, P9_3_TCPWM0_TR_ONE_CNT_IN79}, 1219 {0u, 81u, P9_3, P9_3_TCPWM0_TR_ONE_CNT_IN81}, 1220 {0u, 82u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN82}, 1221 {0u, 84u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN84}, 1222 {0u, 85u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN85}, 1223 {0u, 87u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN87}, 1224 {0u, 88u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN88}, 1225 {0u, 90u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN90}, 1226 {0u, 91u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN91}, 1227 {0u, 93u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN93}, 1228 {0u, 94u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN94}, 1229 {0u, 96u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN96}, 1230 {0u, 97u, P10_5, P10_5_TCPWM0_TR_ONE_CNT_IN97}, 1231 {0u, 99u, P10_5, P10_5_TCPWM0_TR_ONE_CNT_IN99}, 1232 {0u, 100u, P10_6, P10_6_TCPWM0_TR_ONE_CNT_IN100}, 1233 {0u, 102u, P10_6, P10_6_TCPWM0_TR_ONE_CNT_IN102}, 1234 {0u, 103u, P10_7, P10_7_TCPWM0_TR_ONE_CNT_IN103}, 1235 {0u, 105u, P10_7, P10_7_TCPWM0_TR_ONE_CNT_IN105}, 1236 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 1237 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 1238 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 1239 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 1240 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 1241 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 1242 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1243 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1244 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1245 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1246 {0u, 121u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN121}, 1247 {0u, 123u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN123}, 1248 {0u, 124u, P12_6, P12_6_TCPWM0_TR_ONE_CNT_IN124}, 1249 {0u, 126u, P12_6, P12_6_TCPWM0_TR_ONE_CNT_IN126}, 1250 {0u, 127u, P12_7, P12_7_TCPWM0_TR_ONE_CNT_IN127}, 1251 {0u, 129u, P12_7, P12_7_TCPWM0_TR_ONE_CNT_IN129}, 1252 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1253 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1254 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1255 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1256 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1257 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1258 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1259 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1260 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1261 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1262 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1263 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1264 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1265 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1266 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1267 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1268 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1269 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1270 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1271 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1272 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 1273 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 1274 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 1275 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 1276 {0u, 154u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN154}, 1277 {0u, 156u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN156}, 1278 {6u, 12u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN1548}, 1279 {0u, 157u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN157}, 1280 {0u, 159u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN159}, 1281 {6u, 13u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN1549}, 1282 {0u, 160u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN160}, 1283 {0u, 162u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN162}, 1284 {6u, 15u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN1551}, 1285 {0u, 163u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN163}, 1286 {0u, 165u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN165}, 1287 {6u, 16u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN1552}, 1288 {0u, 166u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN166}, 1289 {0u, 168u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN168}, 1290 {6u, 18u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN1554}, 1291 {0u, 169u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN169}, 1292 {0u, 171u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN171}, 1293 {6u, 19u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN1555}, 1294 {0u, 172u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN172}, 1295 {0u, 174u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN174}, 1296 {6u, 21u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN1557}, 1297 {0u, 175u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN175}, 1298 {0u, 177u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN177}, 1299 {6u, 22u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN1558}, 1300 {0u, 178u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN178}, 1301 {0u, 180u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN180}, 1302 {0u, 181u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN181}, 1303 {0u, 183u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN183}, 1304 {0u, 184u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN184}, 1305 {0u, 186u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN186}, 1306 {0u, 186u, P16_3, P16_3_TCPWM0_TR_ONE_CNT_IN186}, 1307 {0u, 187u, P16_3, P16_3_TCPWM0_TR_ONE_CNT_IN187}, 1308 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 1309 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 1310 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 1311 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 1312 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 1313 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 1314 {0u, 174u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN174}, 1315 {0u, 178u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN178}, 1316 {0u, 171u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN171}, 1317 {0u, 175u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN175}, 1318 {0u, 168u, P17_5, P17_5_TCPWM0_TR_ONE_CNT_IN168}, 1319 {0u, 172u, P17_5, P17_5_TCPWM0_TR_ONE_CNT_IN172}, 1320 {0u, 169u, P17_6, P17_6_TCPWM0_TR_ONE_CNT_IN169}, 1321 {3u, 12u, P17_6, P17_6_TCPWM0_TR_ONE_CNT_IN780}, 1322 {3u, 13u, P17_7, P17_7_TCPWM0_TR_ONE_CNT_IN781}, 1323 {3u, 15u, P17_7, P17_7_TCPWM0_TR_ONE_CNT_IN783}, 1324 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1325 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1326 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1327 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1328 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1329 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1330 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1331 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1332 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1333 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1334 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1335 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1336 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1337 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1338 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1339 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1340 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1341 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1342 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1343 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1344 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1345 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1346 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1347 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1348 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1349 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1350 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1351 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1352 {0u, 85u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN85}, 1353 {0u, 87u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN87}, 1354 {6u, 6u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN1542}, 1355 {0u, 88u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN88}, 1356 {0u, 90u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN90}, 1357 {6u, 7u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN1543}, 1358 {0u, 91u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN91}, 1359 {0u, 147u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN147}, 1360 {6u, 9u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN1545}, 1361 {0u, 144u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN144}, 1362 {0u, 148u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN148}, 1363 {6u, 10u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN1546}, 1364 {0u, 141u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN141}, 1365 {0u, 145u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN145}, 1366 {0u, 138u, P20_4, P20_4_TCPWM0_TR_ONE_CNT_IN138}, 1367 {0u, 142u, P20_4, P20_4_TCPWM0_TR_ONE_CNT_IN142}, 1368 {0u, 135u, P20_5, P20_5_TCPWM0_TR_ONE_CNT_IN135}, 1369 {0u, 139u, P20_5, P20_5_TCPWM0_TR_ONE_CNT_IN139}, 1370 {0u, 132u, P20_6, P20_6_TCPWM0_TR_ONE_CNT_IN132}, 1371 {0u, 136u, P20_6, P20_6_TCPWM0_TR_ONE_CNT_IN136}, 1372 {0u, 129u, P20_7, P20_7_TCPWM0_TR_ONE_CNT_IN129}, 1373 {0u, 133u, P20_7, P20_7_TCPWM0_TR_ONE_CNT_IN133}, 1374 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1375 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1376 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1377 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1378 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1379 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1380 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1381 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1382 {0u, 114u, P21_4, P21_4_TCPWM0_TR_ONE_CNT_IN114}, 1383 {0u, 118u, P21_4, P21_4_TCPWM0_TR_ONE_CNT_IN118}, 1384 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1385 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1386 {0u, 108u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN108}, 1387 {0u, 112u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN112}, 1388 {0u, 105u, P21_7, P21_7_TCPWM0_TR_ONE_CNT_IN105}, 1389 {0u, 109u, P21_7, P21_7_TCPWM0_TR_ONE_CNT_IN109}, 1390 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 1391 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 1392 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1393 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1394 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1395 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1396 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1397 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1398 {0u, 90u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN90}, 1399 {0u, 94u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN94}, 1400 {0u, 87u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN87}, 1401 {0u, 91u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN91}, 1402 {0u, 84u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN84}, 1403 {0u, 88u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN88}, 1404 {0u, 81u, P22_7, P22_7_TCPWM0_TR_ONE_CNT_IN81}, 1405 {0u, 85u, P22_7, P22_7_TCPWM0_TR_ONE_CNT_IN85}, 1406 {0u, 82u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN82}, 1407 {3u, 24u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN792}, 1408 {3u, 25u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN793}, 1409 {3u, 27u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN795}, 1410 {3u, 28u, P23_2, P23_2_TCPWM0_TR_ONE_CNT_IN796}, 1411 {3u, 30u, P23_2, P23_2_TCPWM0_TR_ONE_CNT_IN798}, 1412 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1413 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1414 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1415 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1416 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1417 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1418 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1419 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1420 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1421 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1422 }; 1423 1424 #endif 1425
