1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_80_lqfp.c 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 80-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE1M_80_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe1m_80_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[8] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 39 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 40 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 41 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 42 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 43 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 44 }; 45 46 /* Connections for: canfd_ttcan_tx */ 47 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[8] = { 48 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 49 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 50 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 51 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 52 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 53 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 54 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 55 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 56 }; 57 58 /* Connections for: cpuss_cal_sup_nz */ 59 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 60 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 61 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 62 }; 63 64 /* Connections for: cpuss_clk_fm_pump */ 65 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 66 {0u, 0u, NC, HSIOM_SEL_GPIO}, 67 }; 68 69 /* Connections for: cpuss_fault_out */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5] = { 71 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 72 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 73 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 74 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 75 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 76 }; 77 78 /* Connections for: cpuss_swj_swclk_tclk */ 79 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 80 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 81 }; 82 83 /* Connections for: cpuss_swj_swdio_tms */ 84 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 85 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 86 }; 87 88 /* Connections for: cpuss_swj_swdoe_tdi */ 89 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 90 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 91 }; 92 93 /* Connections for: cpuss_swj_swo_tdo */ 94 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 95 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 96 }; 97 98 /* Connections for: cpuss_swj_trstn */ 99 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 100 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 101 }; 102 103 /* Connections for: cpuss_trace_clock */ 104 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 105 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 106 }; 107 108 /* Connections for: cpuss_trace_data */ 109 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[6] = { 110 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 111 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 112 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 113 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 114 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 115 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 116 }; 117 118 /* Connections for: lin_lin_en */ 119 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[8] = { 120 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 121 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 122 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 123 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 124 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 125 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 126 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 127 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 128 }; 129 130 /* Connections for: lin_lin_rx */ 131 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[10] = { 132 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 133 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 134 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 135 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 136 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 137 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 138 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 139 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 140 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 141 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 142 }; 143 144 /* Connections for: lin_lin_tx */ 145 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[8] = { 146 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 147 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 148 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 149 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 150 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 151 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 152 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 153 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 154 }; 155 156 /* Connections for: pass_sar_ext_mux_en */ 157 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 158 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 159 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 160 }; 161 162 /* Connections for: pass_sar_ext_mux_sel */ 163 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[4] = { 164 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 165 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 166 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 167 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 168 }; 169 170 /* Connections for: pass_sarmux_pads */ 171 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[34] = { 172 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 173 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 174 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 175 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 176 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 177 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 178 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 179 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 180 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 181 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 182 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 183 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 184 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 185 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 186 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 187 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 188 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 189 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 190 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 191 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 192 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 193 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 194 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 195 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 196 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 197 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 198 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 199 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 200 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 201 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 202 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 203 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 204 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 205 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 206 }; 207 208 /* Connections for: peri_tr_io_input */ 209 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 210 to know the index of the input or output trigger line. Store that in the channel_num field 211 instead. */ 212 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[12] = { 213 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 214 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 215 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 216 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 217 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 218 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 219 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 220 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 221 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 222 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 223 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 224 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 225 }; 226 227 /* Connections for: peri_tr_io_output */ 228 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 229 to know the index of the input or output trigger line. Store that in the channel_num field 230 instead. */ 231 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 232 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 233 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 234 }; 235 236 /* Connections for: scb_i2c_scl */ 237 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[7] = { 238 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 239 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 240 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 241 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 242 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 243 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 244 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 245 }; 246 247 /* Connections for: scb_i2c_sda */ 248 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10] = { 249 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 250 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 251 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 252 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 253 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 254 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 255 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 256 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 257 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 258 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 259 }; 260 261 /* Connections for: scb_spi_m_clk */ 262 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6] = { 263 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 264 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 265 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 266 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 267 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 268 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 269 }; 270 271 /* Connections for: scb_spi_m_miso */ 272 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[9] = { 273 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 274 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 275 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 276 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 277 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 278 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 279 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 280 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 281 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 282 }; 283 284 /* Connections for: scb_spi_m_mosi */ 285 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[9] = { 286 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 287 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 288 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 289 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 290 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 291 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 292 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 293 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 294 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 295 }; 296 297 /* Connections for: scb_spi_m_select0 */ 298 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7] = { 299 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 300 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 301 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 302 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 303 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 304 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 305 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 306 }; 307 308 /* Connections for: scb_spi_m_select1 */ 309 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5] = { 310 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 311 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 312 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 313 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 314 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 315 }; 316 317 /* Connections for: scb_spi_m_select2 */ 318 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[7] = { 319 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 320 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 321 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 322 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 323 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 324 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 325 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 326 }; 327 328 /* Connections for: scb_spi_m_select3 */ 329 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3] = { 330 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 331 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 332 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 333 }; 334 335 /* Connections for: scb_spi_s_clk */ 336 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6] = { 337 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 338 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 339 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 340 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 341 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 342 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 343 }; 344 345 /* Connections for: scb_spi_s_miso */ 346 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[9] = { 347 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 348 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 349 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 350 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 351 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 352 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 353 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 354 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 355 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 356 }; 357 358 /* Connections for: scb_spi_s_mosi */ 359 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[9] = { 360 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 361 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 362 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 363 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 364 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 365 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 366 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 367 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 368 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 369 }; 370 371 /* Connections for: scb_spi_s_select0 */ 372 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7] = { 373 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 374 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 375 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 376 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 377 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 378 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 379 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 380 }; 381 382 /* Connections for: scb_spi_s_select1 */ 383 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5] = { 384 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 385 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 386 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 387 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 388 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 389 }; 390 391 /* Connections for: scb_spi_s_select2 */ 392 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[7] = { 393 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 394 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 395 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 396 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 397 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 398 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 399 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 400 }; 401 402 /* Connections for: scb_spi_s_select3 */ 403 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3] = { 404 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 405 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 406 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 407 }; 408 409 /* Connections for: scb_uart_cts */ 410 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7] = { 411 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 412 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 413 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 414 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 415 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 416 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 417 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 418 }; 419 420 /* Connections for: scb_uart_rts */ 421 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6] = { 422 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 423 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 424 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 425 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 426 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 427 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 428 }; 429 430 /* Connections for: scb_uart_rx */ 431 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9] = { 432 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 433 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 434 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 435 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 436 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 437 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 438 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 439 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 440 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 441 }; 442 443 /* Connections for: scb_uart_tx */ 444 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9] = { 445 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 446 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 447 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 448 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 449 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 450 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 451 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 452 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 453 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 454 }; 455 456 /* Connections for: tcpwm_line */ 457 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[64] = { 458 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 459 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 460 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 461 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 462 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 463 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 464 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 465 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 466 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 467 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 468 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 469 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 470 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 471 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 472 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 473 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 474 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 475 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 476 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 477 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 478 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 479 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 480 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 481 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 482 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 483 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 484 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 485 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 486 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 487 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 488 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 489 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 490 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 491 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 492 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 493 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 494 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 495 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 496 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 497 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 498 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 499 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 500 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 501 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 502 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 503 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 504 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 505 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 506 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 507 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 508 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 509 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 510 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 511 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 512 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 513 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 514 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 515 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 516 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 517 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 518 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 519 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 520 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 521 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 522 }; 523 524 /* Connections for: tcpwm_line_compl */ 525 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[64] = { 526 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 527 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 528 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 529 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 530 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 531 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 532 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 533 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 534 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 535 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 536 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 537 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 538 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 539 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 540 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 541 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 542 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 543 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 544 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 545 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 546 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 547 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 548 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 549 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 550 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 551 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 552 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 553 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 554 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 555 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 556 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 557 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 558 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 559 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 560 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 561 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 562 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 563 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 564 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 565 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 566 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 567 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 568 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 569 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 570 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 571 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 572 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 573 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 574 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 575 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 576 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 577 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 578 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 579 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 580 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 581 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 582 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 583 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 584 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 585 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 586 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 587 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 588 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 589 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 590 }; 591 592 /* Connections for: tcpwm_tr_one_cnt_in */ 593 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[122] = { 594 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 595 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 596 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 597 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 598 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 599 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 600 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 601 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 602 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 603 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 604 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 605 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 606 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 607 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 608 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 609 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 610 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 611 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 612 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 613 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 614 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 615 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 616 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 617 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 618 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 619 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 620 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 621 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 622 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 623 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 624 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 625 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 626 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 627 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 628 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 629 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 630 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 631 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 632 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 633 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 634 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 635 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 636 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 637 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 638 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 639 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 640 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 641 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 642 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 643 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 644 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 645 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 646 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 647 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 648 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 649 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 650 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 651 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 652 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 653 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 654 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 655 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 656 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 657 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 658 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 659 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 660 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 661 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 662 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 663 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 664 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 665 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 666 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 667 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 668 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 669 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 670 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 671 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 672 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 673 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 674 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 675 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 676 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 677 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 678 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 679 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 680 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 681 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 682 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 683 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 684 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 685 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 686 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 687 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 688 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 689 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 690 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 691 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 692 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 693 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 694 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 695 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 696 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 697 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 698 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 699 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 700 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 701 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 702 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 703 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 704 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 705 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 706 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 707 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 708 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 709 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 710 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 711 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 712 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 713 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 714 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 715 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 716 }; 717 718 #endif 719
