1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_176_lqfp.c 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 176-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE1M_176_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe1m_176_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[12] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 1u, P4_4, P4_4_CANFD0_TTCAN_RX1}, 39 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 40 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 41 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 42 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 43 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 44 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 45 {1u, 2u, P20_4, P20_4_CANFD1_TTCAN_RX2}, 46 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 47 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 48 }; 49 50 /* Connections for: canfd_ttcan_tx */ 51 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[12] = { 52 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 53 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 54 {0u, 1u, P4_3, P4_3_CANFD0_TTCAN_TX1}, 55 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 56 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 57 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 58 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 59 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 60 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 61 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 62 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 63 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 64 }; 65 66 /* Connections for: cpuss_cal_sup_nz */ 67 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3] = { 68 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 69 {0u, 0u, P21_7, P21_7_CPUSS_CAL_SUP_NZ}, 70 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 71 }; 72 73 /* Connections for: cpuss_clk_fm_pump */ 74 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 75 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 76 }; 77 78 /* Connections for: cpuss_fault_out */ 79 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8] = { 80 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 81 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 82 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 83 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 84 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 85 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 86 {0u, 2u, P23_2, P23_2_CPUSS_FAULT_OUT2}, 87 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 88 }; 89 90 /* Connections for: cpuss_swj_swclk_tclk */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 92 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 93 }; 94 95 /* Connections for: cpuss_swj_swdio_tms */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 97 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 98 }; 99 100 /* Connections for: cpuss_swj_swdoe_tdi */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 102 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 103 }; 104 105 /* Connections for: cpuss_swj_swo_tdo */ 106 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 107 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 108 }; 109 110 /* Connections for: cpuss_swj_trstn */ 111 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 112 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 113 }; 114 115 /* Connections for: cpuss_trace_clock */ 116 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 117 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 118 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 119 }; 120 121 /* Connections for: cpuss_trace_data */ 122 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 123 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 124 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 125 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 126 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 127 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 128 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 129 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 130 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 131 }; 132 133 /* Connections for: lin_lin_en */ 134 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[15] = { 135 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 136 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 137 {0u, 5u, P2_5, P2_5_LIN0_LIN_EN5}, 138 {0u, 1u, P4_2, P4_2_LIN0_LIN_EN1}, 139 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 140 {0u, 2u, P5_5, P5_5_LIN0_LIN_EN2}, 141 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 142 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 143 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 144 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 145 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 146 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 147 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 148 {0u, 0u, P21_7, P21_7_LIN0_LIN_EN0}, 149 {0u, 7u, P22_7, P22_7_LIN0_LIN_EN7}, 150 }; 151 152 /* Connections for: lin_lin_rx */ 153 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[15] = { 154 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 155 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 156 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 157 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 158 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 159 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 160 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 161 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 162 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 163 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 164 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 165 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 166 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 167 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 168 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 169 }; 170 171 /* Connections for: lin_lin_tx */ 172 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[15] = { 173 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 174 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 175 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 176 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 177 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 178 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 179 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 180 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 181 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 182 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 183 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 184 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 185 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 186 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 187 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 188 }; 189 190 /* Connections for: pass_sar_ext_mux_en */ 191 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3] = { 192 {0u, 0u, P4_3, P4_3_PASS0_SAR_EXT_MUX_EN0}, 193 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 194 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 195 }; 196 197 /* Connections for: pass_sar_ext_mux_sel */ 198 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9] = { 199 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 200 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 201 {0u, 2u, P4_2, P4_2_PASS0_SAR_EXT_MUX_SEL2}, 202 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 203 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 204 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 205 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 206 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 207 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 208 }; 209 210 /* Connections for: pass_sarmux_pads */ 211 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[64] = { 212 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 213 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 214 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 215 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 216 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 217 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 218 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 219 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 220 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 221 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 222 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 223 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 224 {0u, 12u, P7_4, HSIOM_SEL_GPIO}, 225 {0u, 13u, P7_5, HSIOM_SEL_GPIO}, 226 {0u, 14u, P7_6, HSIOM_SEL_GPIO}, 227 {0u, 15u, P7_7, HSIOM_SEL_GPIO}, 228 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 229 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 230 {0u, 18u, P8_3, HSIOM_SEL_GPIO}, 231 {0u, 19u, P8_4, HSIOM_SEL_GPIO}, 232 {0u, 20u, P9_0, HSIOM_SEL_GPIO}, 233 {0u, 21u, P9_1, HSIOM_SEL_GPIO}, 234 {0u, 22u, P9_2, HSIOM_SEL_GPIO}, 235 {0u, 23u, P9_3, HSIOM_SEL_GPIO}, 236 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 237 {1u, 1u, P10_5, HSIOM_SEL_GPIO}, 238 {1u, 2u, P10_6, HSIOM_SEL_GPIO}, 239 {1u, 3u, P10_7, HSIOM_SEL_GPIO}, 240 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 241 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 242 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 243 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 244 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 245 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 246 {1u, 10u, P12_6, HSIOM_SEL_GPIO}, 247 {1u, 11u, P12_7, HSIOM_SEL_GPIO}, 248 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 249 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 250 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 251 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 252 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 253 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 254 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 255 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 256 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 257 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 258 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 259 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 260 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 261 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 262 {1u, 26u, P14_6, HSIOM_SEL_GPIO}, 263 {1u, 27u, P14_7, HSIOM_SEL_GPIO}, 264 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 265 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 266 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 267 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 268 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 269 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 270 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 271 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 272 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 273 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 274 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 275 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 276 }; 277 278 /* Connections for: peri_tr_io_input */ 279 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 280 to know the index of the input or output trigger line. Store that in the channel_num field 281 instead. */ 282 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[32] = { 283 {0u, 0u, P1_2, P1_2_PERI_TR_IO_INPUT0}, 284 {0u, 1u, P1_3, P1_3_PERI_TR_IO_INPUT1}, 285 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 286 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 287 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 288 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 289 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 290 {0u, 7u, P2_5, P2_5_PERI_TR_IO_INPUT7}, 291 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 292 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 293 {0u, 12u, P4_2, P4_2_PERI_TR_IO_INPUT12}, 294 {0u, 13u, P4_3, P4_3_PERI_TR_IO_INPUT13}, 295 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 296 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 297 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 298 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 299 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 300 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 301 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 302 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 303 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 304 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 305 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 306 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 307 {0u, 24u, P14_6, P14_6_PERI_TR_IO_INPUT24}, 308 {0u, 25u, P14_7, P14_7_PERI_TR_IO_INPUT25}, 309 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 310 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 311 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 312 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 313 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 314 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 315 }; 316 317 /* Connections for: peri_tr_io_output */ 318 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 319 to know the index of the input or output trigger line. Store that in the channel_num field 320 instead. */ 321 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6] = { 322 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 323 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 324 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 325 {0u, 1u, P8_4, P8_4_PERI_TR_IO_OUTPUT1}, 326 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 327 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 328 }; 329 330 /* Connections for: scb_i2c_scl */ 331 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17] = { 332 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 333 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 334 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 335 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 336 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 337 {5u, 0u, P4_2, P4_2_SCB5_I2C_SCL}, 338 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 339 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 340 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 341 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 342 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 343 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 344 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 345 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 346 {1u, 0u, P20_5, P20_5_SCB1_I2C_SCL}, 347 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 348 {7u, 0u, P23_2, P23_2_SCB7_I2C_SCL}, 349 }; 350 351 /* Connections for: scb_i2c_sda */ 352 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17] = { 353 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 354 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 355 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 356 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 357 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 358 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 359 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 360 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 361 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 362 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 363 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 364 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 365 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 366 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 367 {1u, 0u, P20_4, P20_4_SCB1_I2C_SDA}, 368 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 369 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 370 }; 371 372 /* Connections for: scb_spi_m_clk */ 373 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16] = { 374 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 375 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 376 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 377 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 378 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 379 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 380 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 381 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 382 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 383 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 384 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 385 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 386 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 387 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 388 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 389 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 390 }; 391 392 /* Connections for: scb_spi_m_miso */ 393 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[16] = { 394 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 395 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 396 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 397 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 398 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 399 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 400 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 401 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 402 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 403 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 404 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 405 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 406 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 407 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 408 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 409 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 410 }; 411 412 /* Connections for: scb_spi_m_mosi */ 413 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[16] = { 414 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 415 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 416 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 417 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 418 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 419 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 420 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 421 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 422 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 423 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 424 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 425 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 426 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 427 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 428 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 429 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 430 }; 431 432 /* Connections for: scb_spi_m_select0 */ 433 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16] = { 434 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 435 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 436 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 437 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 438 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 439 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 440 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 441 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 442 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 443 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 444 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 445 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 446 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 447 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 448 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 449 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 450 }; 451 452 /* Connections for: scb_spi_m_select1 */ 453 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[15] = { 454 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 455 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 456 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 457 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 458 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 459 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 460 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 461 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 462 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 463 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 464 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 465 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 466 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 467 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 468 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 469 }; 470 471 /* Connections for: scb_spi_m_select2 */ 472 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[15] = { 473 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 474 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 475 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 476 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 477 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 478 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 479 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 480 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 481 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 482 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 483 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 484 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 485 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 486 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 487 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 488 }; 489 490 /* Connections for: scb_spi_m_select3 */ 491 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = { 492 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 493 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 494 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 495 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 496 }; 497 498 /* Connections for: scb_spi_s_clk */ 499 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16] = { 500 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 501 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 502 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 503 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 504 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 505 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 506 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 507 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 508 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 509 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 510 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 511 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 512 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 513 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 514 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 515 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 516 }; 517 518 /* Connections for: scb_spi_s_miso */ 519 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[16] = { 520 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 521 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 522 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 523 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 524 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 525 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 526 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 527 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 528 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 529 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 530 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 531 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 532 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 533 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 534 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 535 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 536 }; 537 538 /* Connections for: scb_spi_s_mosi */ 539 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[16] = { 540 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 541 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 542 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 543 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 544 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 545 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 546 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 547 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 548 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 549 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 550 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 551 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 552 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 553 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 554 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 555 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 556 }; 557 558 /* Connections for: scb_spi_s_select0 */ 559 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16] = { 560 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 561 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 562 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 563 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 564 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 565 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 566 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 567 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 568 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 569 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 570 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 571 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 572 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 573 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 574 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 575 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 576 }; 577 578 /* Connections for: scb_spi_s_select1 */ 579 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[15] = { 580 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 581 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 582 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 583 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 584 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 585 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 586 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 587 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 588 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 589 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 590 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 591 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 592 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 593 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 594 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 595 }; 596 597 /* Connections for: scb_spi_s_select2 */ 598 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[15] = { 599 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 600 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 601 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 602 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 603 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 604 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 605 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 606 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 607 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 608 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 609 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 610 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 611 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 612 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 613 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 614 }; 615 616 /* Connections for: scb_spi_s_select3 */ 617 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = { 618 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 619 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 620 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 621 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 622 }; 623 624 /* Connections for: scb_uart_cts */ 625 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15] = { 626 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 627 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 628 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 629 {5u, 0u, P4_3, P4_3_SCB5_UART_CTS}, 630 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 631 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 632 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 633 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 634 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 635 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 636 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 637 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 638 {1u, 0u, P20_6, P20_6_SCB1_UART_CTS}, 639 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 640 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 641 }; 642 643 /* Connections for: scb_uart_rts */ 644 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15] = { 645 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 646 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 647 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 648 {5u, 0u, P4_2, P4_2_SCB5_UART_RTS}, 649 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 650 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 651 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 652 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 653 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 654 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 655 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 656 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 657 {1u, 0u, P20_5, P20_5_SCB1_UART_RTS}, 658 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 659 {7u, 0u, P23_2, P23_2_SCB7_UART_RTS}, 660 }; 661 662 /* Connections for: scb_uart_rx */ 663 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15] = { 664 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 665 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 666 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 667 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 668 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 669 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 670 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 671 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 672 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 673 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 674 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 675 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 676 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 677 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 678 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 679 }; 680 681 /* Connections for: scb_uart_tx */ 682 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15] = { 683 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 684 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 685 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 686 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 687 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 688 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 689 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 690 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 691 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 692 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 693 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 694 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 695 {1u, 0u, P20_4, P20_4_SCB1_UART_TX}, 696 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 697 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 698 }; 699 700 /* Connections for: tcpwm_line */ 701 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[157] = { 702 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 703 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 704 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 705 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 706 {0u, 12u, P1_0, P1_0_TCPWM0_LINE12}, 707 {0u, 11u, P1_1, P1_1_TCPWM0_LINE11}, 708 {0u, 10u, P1_2, P1_2_TCPWM0_LINE10}, 709 {0u, 8u, P1_3, P1_3_TCPWM0_LINE8}, 710 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 711 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 712 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 713 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 714 {0u, 3u, P2_4, P2_4_TCPWM0_LINE3}, 715 {0u, 2u, P2_5, P2_5_TCPWM0_LINE2}, 716 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 717 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 718 {1u, 3u, P3_2, P3_2_TCPWM0_LINE259}, 719 {1u, 2u, P3_3, P3_3_TCPWM0_LINE258}, 720 {1u, 1u, P3_4, P3_4_TCPWM0_LINE257}, 721 {1u, 0u, P3_5, P3_5_TCPWM0_LINE256}, 722 {0u, 4u, P4_0, P4_0_TCPWM0_LINE4}, 723 {0u, 5u, P4_1, P4_1_TCPWM0_LINE5}, 724 {0u, 6u, P4_2, P4_2_TCPWM0_LINE6}, 725 {0u, 7u, P4_3, P4_3_TCPWM0_LINE7}, 726 {0u, 8u, P4_4, P4_4_TCPWM0_LINE8}, 727 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 728 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 729 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 730 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 731 {0u, 13u, P5_4, P5_4_TCPWM0_LINE13}, 732 {0u, 14u, P5_5, P5_5_TCPWM0_LINE14}, 733 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 734 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 735 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 736 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 737 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 738 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 739 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 740 {0u, 3u, P6_7, P6_7_TCPWM0_LINE3}, 741 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 742 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 743 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 744 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 745 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 746 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 747 {1u, 7u, P7_6, P7_6_TCPWM0_LINE263}, 748 {0u, 18u, P7_7, P7_7_TCPWM0_LINE18}, 749 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 750 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 751 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 752 {0u, 22u, P8_3, P8_3_TCPWM0_LINE22}, 753 {0u, 23u, P8_4, P8_4_TCPWM0_LINE23}, 754 {0u, 24u, P9_0, P9_0_TCPWM0_LINE24}, 755 {0u, 25u, P9_1, P9_1_TCPWM0_LINE25}, 756 {0u, 26u, P9_2, P9_2_TCPWM0_LINE26}, 757 {0u, 27u, P9_3, P9_3_TCPWM0_LINE27}, 758 {0u, 28u, P10_0, P10_0_TCPWM0_LINE28}, 759 {0u, 29u, P10_1, P10_1_TCPWM0_LINE29}, 760 {0u, 30u, P10_2, P10_2_TCPWM0_LINE30}, 761 {0u, 31u, P10_3, P10_3_TCPWM0_LINE31}, 762 {0u, 32u, P10_4, P10_4_TCPWM0_LINE32}, 763 {0u, 33u, P10_5, P10_5_TCPWM0_LINE33}, 764 {0u, 34u, P10_6, P10_6_TCPWM0_LINE34}, 765 {0u, 35u, P10_7, P10_7_TCPWM0_LINE35}, 766 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 767 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 768 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 769 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 770 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 771 {0u, 41u, P12_5, P12_5_TCPWM0_LINE41}, 772 {0u, 42u, P12_6, P12_6_TCPWM0_LINE42}, 773 {0u, 43u, P12_7, P12_7_TCPWM0_LINE43}, 774 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 775 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 776 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 777 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 778 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 779 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 780 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 781 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 782 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 783 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 784 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 785 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 786 {0u, 52u, P14_4, P14_4_TCPWM0_LINE52}, 787 {0u, 53u, P14_5, P14_5_TCPWM0_LINE53}, 788 {0u, 54u, P14_6, P14_6_TCPWM0_LINE54}, 789 {0u, 55u, P14_7, P14_7_TCPWM0_LINE55}, 790 {0u, 56u, P15_0, P15_0_TCPWM0_LINE56}, 791 {0u, 57u, P15_1, P15_1_TCPWM0_LINE57}, 792 {0u, 58u, P15_2, P15_2_TCPWM0_LINE58}, 793 {0u, 59u, P15_3, P15_3_TCPWM0_LINE59}, 794 {0u, 60u, P16_0, P16_0_TCPWM0_LINE60}, 795 {2u, 0u, P16_0, P16_0_TCPWM0_LINE512}, 796 {0u, 61u, P16_1, P16_1_TCPWM0_LINE61}, 797 {0u, 62u, P16_2, P16_2_TCPWM0_LINE62}, 798 {2u, 1u, P16_2, P16_2_TCPWM0_LINE513}, 799 {0u, 62u, P16_3, P16_3_TCPWM0_LINE62}, 800 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 801 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 802 {2u, 2u, P17_1, P17_1_TCPWM0_LINE514}, 803 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 804 {0u, 58u, P17_3, P17_3_TCPWM0_LINE58}, 805 {2u, 3u, P17_3, P17_3_TCPWM0_LINE515}, 806 {0u, 57u, P17_4, P17_4_TCPWM0_LINE57}, 807 {0u, 56u, P17_5, P17_5_TCPWM0_LINE56}, 808 {1u, 4u, P17_6, P17_6_TCPWM0_LINE260}, 809 {1u, 5u, P17_7, P17_7_TCPWM0_LINE261}, 810 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 811 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 812 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 813 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 814 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 815 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 816 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 817 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 818 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 819 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 820 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 821 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 822 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 823 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 824 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 825 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 826 {0u, 29u, P19_4, P19_4_TCPWM0_LINE29}, 827 {0u, 30u, P20_0, P20_0_TCPWM0_LINE30}, 828 {0u, 49u, P20_1, P20_1_TCPWM0_LINE49}, 829 {0u, 48u, P20_2, P20_2_TCPWM0_LINE48}, 830 {0u, 47u, P20_3, P20_3_TCPWM0_LINE47}, 831 {0u, 46u, P20_4, P20_4_TCPWM0_LINE46}, 832 {0u, 45u, P20_5, P20_5_TCPWM0_LINE45}, 833 {0u, 44u, P20_6, P20_6_TCPWM0_LINE44}, 834 {0u, 43u, P20_7, P20_7_TCPWM0_LINE43}, 835 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 836 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 837 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 838 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 839 {0u, 38u, P21_4, P21_4_TCPWM0_LINE38}, 840 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 841 {0u, 36u, P21_6, P21_6_TCPWM0_LINE36}, 842 {0u, 35u, P21_7, P21_7_TCPWM0_LINE35}, 843 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 844 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 845 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 846 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 847 {0u, 30u, P22_4, P22_4_TCPWM0_LINE30}, 848 {0u, 29u, P22_5, P22_5_TCPWM0_LINE29}, 849 {0u, 28u, P22_6, P22_6_TCPWM0_LINE28}, 850 {0u, 27u, P22_7, P22_7_TCPWM0_LINE27}, 851 {1u, 8u, P23_0, P23_0_TCPWM0_LINE264}, 852 {1u, 9u, P23_1, P23_1_TCPWM0_LINE265}, 853 {1u, 10u, P23_2, P23_2_TCPWM0_LINE266}, 854 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 855 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 856 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 857 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 858 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 859 }; 860 861 /* Connections for: tcpwm_line_compl */ 862 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[157] = { 863 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 864 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 865 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 866 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 867 {0u, 13u, P1_0, P1_0_TCPWM0_LINE_COMPL13}, 868 {0u, 12u, P1_1, P1_1_TCPWM0_LINE_COMPL12}, 869 {0u, 11u, P1_2, P1_2_TCPWM0_LINE_COMPL11}, 870 {0u, 10u, P1_3, P1_3_TCPWM0_LINE_COMPL10}, 871 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 872 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 873 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 874 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 875 {0u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL4}, 876 {0u, 3u, P2_5, P2_5_TCPWM0_LINE_COMPL3}, 877 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 878 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 879 {0u, 0u, P3_2, P3_2_TCPWM0_LINE_COMPL0}, 880 {1u, 3u, P3_3, P3_3_TCPWM0_LINE_COMPL259}, 881 {1u, 2u, P3_4, P3_4_TCPWM0_LINE_COMPL258}, 882 {1u, 1u, P3_5, P3_5_TCPWM0_LINE_COMPL257}, 883 {1u, 0u, P4_0, P4_0_TCPWM0_LINE_COMPL256}, 884 {0u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL4}, 885 {0u, 5u, P4_2, P4_2_TCPWM0_LINE_COMPL5}, 886 {0u, 6u, P4_3, P4_3_TCPWM0_LINE_COMPL6}, 887 {0u, 7u, P4_4, P4_4_TCPWM0_LINE_COMPL7}, 888 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 889 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 890 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 891 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 892 {0u, 12u, P5_4, P5_4_TCPWM0_LINE_COMPL12}, 893 {0u, 13u, P5_5, P5_5_TCPWM0_LINE_COMPL13}, 894 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 895 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 896 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 897 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 898 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 899 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 900 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 901 {1u, 3u, P6_7, P6_7_TCPWM0_LINE_COMPL259}, 902 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 903 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 904 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 905 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 906 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 907 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 908 {0u, 17u, P7_6, P7_6_TCPWM0_LINE_COMPL17}, 909 {1u, 7u, P7_7, P7_7_TCPWM0_LINE_COMPL263}, 910 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 911 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 912 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 913 {0u, 21u, P8_3, P8_3_TCPWM0_LINE_COMPL21}, 914 {0u, 22u, P8_4, P8_4_TCPWM0_LINE_COMPL22}, 915 {0u, 23u, P9_0, P9_0_TCPWM0_LINE_COMPL23}, 916 {0u, 24u, P9_1, P9_1_TCPWM0_LINE_COMPL24}, 917 {0u, 25u, P9_2, P9_2_TCPWM0_LINE_COMPL25}, 918 {0u, 26u, P9_3, P9_3_TCPWM0_LINE_COMPL26}, 919 {0u, 27u, P10_0, P10_0_TCPWM0_LINE_COMPL27}, 920 {0u, 28u, P10_1, P10_1_TCPWM0_LINE_COMPL28}, 921 {0u, 29u, P10_2, P10_2_TCPWM0_LINE_COMPL29}, 922 {0u, 30u, P10_3, P10_3_TCPWM0_LINE_COMPL30}, 923 {0u, 31u, P10_4, P10_4_TCPWM0_LINE_COMPL31}, 924 {0u, 32u, P10_5, P10_5_TCPWM0_LINE_COMPL32}, 925 {0u, 33u, P10_6, P10_6_TCPWM0_LINE_COMPL33}, 926 {0u, 34u, P10_7, P10_7_TCPWM0_LINE_COMPL34}, 927 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 928 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 929 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 930 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 931 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 932 {0u, 40u, P12_5, P12_5_TCPWM0_LINE_COMPL40}, 933 {0u, 41u, P12_6, P12_6_TCPWM0_LINE_COMPL41}, 934 {0u, 42u, P12_7, P12_7_TCPWM0_LINE_COMPL42}, 935 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 936 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 937 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 938 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 939 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 940 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 941 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 942 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 943 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 944 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 945 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 946 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 947 {0u, 51u, P14_4, P14_4_TCPWM0_LINE_COMPL51}, 948 {0u, 52u, P14_5, P14_5_TCPWM0_LINE_COMPL52}, 949 {0u, 53u, P14_6, P14_6_TCPWM0_LINE_COMPL53}, 950 {0u, 54u, P14_7, P14_7_TCPWM0_LINE_COMPL54}, 951 {0u, 55u, P15_0, P15_0_TCPWM0_LINE_COMPL55}, 952 {0u, 56u, P15_1, P15_1_TCPWM0_LINE_COMPL56}, 953 {0u, 57u, P15_2, P15_2_TCPWM0_LINE_COMPL57}, 954 {0u, 58u, P15_3, P15_3_TCPWM0_LINE_COMPL58}, 955 {0u, 59u, P16_0, P16_0_TCPWM0_LINE_COMPL59}, 956 {0u, 60u, P16_1, P16_1_TCPWM0_LINE_COMPL60}, 957 {2u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL512}, 958 {0u, 61u, P16_2, P16_2_TCPWM0_LINE_COMPL61}, 959 {0u, 62u, P16_3, P16_3_TCPWM0_LINE_COMPL62}, 960 {2u, 1u, P16_3, P16_3_TCPWM0_LINE_COMPL513}, 961 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 962 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 963 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 964 {2u, 2u, P17_2, P17_2_TCPWM0_LINE_COMPL514}, 965 {0u, 59u, P17_3, P17_3_TCPWM0_LINE_COMPL59}, 966 {0u, 58u, P17_4, P17_4_TCPWM0_LINE_COMPL58}, 967 {2u, 3u, P17_4, P17_4_TCPWM0_LINE_COMPL515}, 968 {0u, 57u, P17_5, P17_5_TCPWM0_LINE_COMPL57}, 969 {0u, 56u, P17_6, P17_6_TCPWM0_LINE_COMPL56}, 970 {1u, 4u, P17_7, P17_7_TCPWM0_LINE_COMPL260}, 971 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 972 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 973 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 974 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 975 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 976 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 977 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 978 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 979 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 980 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 981 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 982 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 983 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 984 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 985 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 986 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 987 {0u, 28u, P19_4, P19_4_TCPWM0_LINE_COMPL28}, 988 {0u, 29u, P20_0, P20_0_TCPWM0_LINE_COMPL29}, 989 {0u, 30u, P20_1, P20_1_TCPWM0_LINE_COMPL30}, 990 {0u, 49u, P20_2, P20_2_TCPWM0_LINE_COMPL49}, 991 {0u, 48u, P20_3, P20_3_TCPWM0_LINE_COMPL48}, 992 {0u, 47u, P20_4, P20_4_TCPWM0_LINE_COMPL47}, 993 {0u, 46u, P20_5, P20_5_TCPWM0_LINE_COMPL46}, 994 {0u, 45u, P20_6, P20_6_TCPWM0_LINE_COMPL45}, 995 {0u, 44u, P20_7, P20_7_TCPWM0_LINE_COMPL44}, 996 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 997 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 998 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 999 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 1000 {0u, 39u, P21_4, P21_4_TCPWM0_LINE_COMPL39}, 1001 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 1002 {0u, 37u, P21_6, P21_6_TCPWM0_LINE_COMPL37}, 1003 {0u, 36u, P21_7, P21_7_TCPWM0_LINE_COMPL36}, 1004 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 1005 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 1006 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 1007 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 1008 {0u, 31u, P22_4, P22_4_TCPWM0_LINE_COMPL31}, 1009 {0u, 30u, P22_5, P22_5_TCPWM0_LINE_COMPL30}, 1010 {0u, 29u, P22_6, P22_6_TCPWM0_LINE_COMPL29}, 1011 {0u, 28u, P22_7, P22_7_TCPWM0_LINE_COMPL28}, 1012 {0u, 27u, P23_0, P23_0_TCPWM0_LINE_COMPL27}, 1013 {1u, 8u, P23_1, P23_1_TCPWM0_LINE_COMPL264}, 1014 {1u, 9u, P23_2, P23_2_TCPWM0_LINE_COMPL265}, 1015 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 1016 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 1017 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 1018 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 1019 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 1020 }; 1021 1022 /* Connections for: tcpwm_tr_one_cnt_in */ 1023 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[306] = { 1024 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 1025 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 1026 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 1027 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 1028 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 1029 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 1030 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 1031 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 1032 {0u, 36u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN36}, 1033 {0u, 40u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN40}, 1034 {0u, 33u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN33}, 1035 {0u, 37u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN37}, 1036 {0u, 30u, P1_2, P1_2_TCPWM0_TR_ONE_CNT_IN30}, 1037 {0u, 34u, P1_2, P1_2_TCPWM0_TR_ONE_CNT_IN34}, 1038 {0u, 24u, P1_3, P1_3_TCPWM0_TR_ONE_CNT_IN24}, 1039 {0u, 31u, P1_3, P1_3_TCPWM0_TR_ONE_CNT_IN31}, 1040 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 1041 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 1042 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 1043 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 1044 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 1045 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 1046 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 1047 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 1048 {0u, 9u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN9}, 1049 {0u, 13u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN13}, 1050 {0u, 6u, P2_5, P2_5_TCPWM0_TR_ONE_CNT_IN6}, 1051 {0u, 10u, P2_5, P2_5_TCPWM0_TR_ONE_CNT_IN10}, 1052 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 1053 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 1054 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 1055 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 1056 {0u, 1u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1}, 1057 {3u, 9u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN777}, 1058 {3u, 6u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN774}, 1059 {3u, 10u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN778}, 1060 {3u, 3u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN771}, 1061 {3u, 7u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN775}, 1062 {3u, 0u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN768}, 1063 {3u, 4u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN772}, 1064 {0u, 12u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN12}, 1065 {3u, 1u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN769}, 1066 {0u, 13u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN13}, 1067 {0u, 15u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN15}, 1068 {0u, 16u, P4_2, P4_2_TCPWM0_TR_ONE_CNT_IN16}, 1069 {0u, 18u, P4_2, P4_2_TCPWM0_TR_ONE_CNT_IN18}, 1070 {0u, 19u, P4_3, P4_3_TCPWM0_TR_ONE_CNT_IN19}, 1071 {0u, 21u, P4_3, P4_3_TCPWM0_TR_ONE_CNT_IN21}, 1072 {0u, 22u, P4_4, P4_4_TCPWM0_TR_ONE_CNT_IN22}, 1073 {0u, 24u, P4_4, P4_4_TCPWM0_TR_ONE_CNT_IN24}, 1074 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 1075 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 1076 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 1077 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 1078 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 1079 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 1080 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 1081 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 1082 {0u, 37u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN37}, 1083 {0u, 39u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN39}, 1084 {0u, 40u, P5_5, P5_5_TCPWM0_TR_ONE_CNT_IN40}, 1085 {0u, 42u, P5_5, P5_5_TCPWM0_TR_ONE_CNT_IN42}, 1086 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 1087 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 1088 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 1089 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 1090 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 1091 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 1092 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 1093 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 1094 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 1095 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 1096 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 1097 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 1098 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 1099 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 1100 {0u, 9u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN9}, 1101 {3u, 10u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN778}, 1102 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 1103 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 1104 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 1105 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 1106 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 1107 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 1108 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 1109 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 1110 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 1111 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 1112 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 1113 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 1114 {0u, 52u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN52}, 1115 {3u, 21u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN789}, 1116 {0u, 54u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN54}, 1117 {3u, 22u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN790}, 1118 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 1119 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 1120 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 1121 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 1122 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 1123 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 1124 {0u, 64u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN64}, 1125 {0u, 66u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN66}, 1126 {0u, 67u, P8_4, P8_4_TCPWM0_TR_ONE_CNT_IN67}, 1127 {0u, 69u, P8_4, P8_4_TCPWM0_TR_ONE_CNT_IN69}, 1128 {0u, 70u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN70}, 1129 {0u, 72u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN72}, 1130 {0u, 73u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN73}, 1131 {0u, 75u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN75}, 1132 {0u, 76u, P9_2, P9_2_TCPWM0_TR_ONE_CNT_IN76}, 1133 {0u, 78u, P9_2, P9_2_TCPWM0_TR_ONE_CNT_IN78}, 1134 {0u, 79u, P9_3, P9_3_TCPWM0_TR_ONE_CNT_IN79}, 1135 {0u, 81u, P9_3, P9_3_TCPWM0_TR_ONE_CNT_IN81}, 1136 {0u, 82u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN82}, 1137 {0u, 84u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN84}, 1138 {0u, 85u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN85}, 1139 {0u, 87u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN87}, 1140 {0u, 88u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN88}, 1141 {0u, 90u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN90}, 1142 {0u, 91u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN91}, 1143 {0u, 93u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN93}, 1144 {0u, 94u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN94}, 1145 {0u, 96u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN96}, 1146 {0u, 97u, P10_5, P10_5_TCPWM0_TR_ONE_CNT_IN97}, 1147 {0u, 99u, P10_5, P10_5_TCPWM0_TR_ONE_CNT_IN99}, 1148 {0u, 100u, P10_6, P10_6_TCPWM0_TR_ONE_CNT_IN100}, 1149 {0u, 102u, P10_6, P10_6_TCPWM0_TR_ONE_CNT_IN102}, 1150 {0u, 103u, P10_7, P10_7_TCPWM0_TR_ONE_CNT_IN103}, 1151 {0u, 105u, P10_7, P10_7_TCPWM0_TR_ONE_CNT_IN105}, 1152 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 1153 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 1154 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 1155 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 1156 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 1157 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 1158 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1159 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1160 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1161 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1162 {0u, 121u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN121}, 1163 {0u, 123u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN123}, 1164 {0u, 124u, P12_6, P12_6_TCPWM0_TR_ONE_CNT_IN124}, 1165 {0u, 126u, P12_6, P12_6_TCPWM0_TR_ONE_CNT_IN126}, 1166 {0u, 127u, P12_7, P12_7_TCPWM0_TR_ONE_CNT_IN127}, 1167 {0u, 129u, P12_7, P12_7_TCPWM0_TR_ONE_CNT_IN129}, 1168 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1169 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1170 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1171 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1172 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1173 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1174 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1175 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1176 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1177 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1178 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1179 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1180 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1181 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1182 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1183 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1184 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1185 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1186 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1187 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1188 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 1189 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 1190 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 1191 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 1192 {0u, 154u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN154}, 1193 {0u, 156u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN156}, 1194 {0u, 157u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN157}, 1195 {0u, 159u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN159}, 1196 {0u, 160u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN160}, 1197 {0u, 162u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN162}, 1198 {0u, 163u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN163}, 1199 {0u, 165u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN165}, 1200 {0u, 166u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN166}, 1201 {0u, 168u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN168}, 1202 {0u, 169u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN169}, 1203 {0u, 171u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN171}, 1204 {0u, 172u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN172}, 1205 {0u, 174u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN174}, 1206 {0u, 175u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN175}, 1207 {0u, 177u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN177}, 1208 {0u, 178u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN178}, 1209 {0u, 180u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN180}, 1210 {0u, 181u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN181}, 1211 {0u, 183u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN183}, 1212 {0u, 184u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN184}, 1213 {0u, 186u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN186}, 1214 {0u, 186u, P16_3, P16_3_TCPWM0_TR_ONE_CNT_IN186}, 1215 {0u, 187u, P16_3, P16_3_TCPWM0_TR_ONE_CNT_IN187}, 1216 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 1217 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 1218 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 1219 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 1220 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 1221 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 1222 {0u, 174u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN174}, 1223 {0u, 178u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN178}, 1224 {0u, 171u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN171}, 1225 {0u, 175u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN175}, 1226 {0u, 168u, P17_5, P17_5_TCPWM0_TR_ONE_CNT_IN168}, 1227 {0u, 172u, P17_5, P17_5_TCPWM0_TR_ONE_CNT_IN172}, 1228 {0u, 169u, P17_6, P17_6_TCPWM0_TR_ONE_CNT_IN169}, 1229 {3u, 12u, P17_6, P17_6_TCPWM0_TR_ONE_CNT_IN780}, 1230 {3u, 13u, P17_7, P17_7_TCPWM0_TR_ONE_CNT_IN781}, 1231 {3u, 15u, P17_7, P17_7_TCPWM0_TR_ONE_CNT_IN783}, 1232 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1233 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1234 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1235 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1236 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1237 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1238 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1239 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1240 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1241 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1242 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1243 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1244 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1245 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1246 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1247 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1248 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1249 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1250 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1251 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1252 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1253 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1254 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1255 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1256 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1257 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1258 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1259 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1260 {0u, 85u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN85}, 1261 {0u, 87u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN87}, 1262 {6u, 6u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN1542}, 1263 {0u, 88u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN88}, 1264 {0u, 90u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN90}, 1265 {6u, 7u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN1543}, 1266 {0u, 91u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN91}, 1267 {0u, 147u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN147}, 1268 {6u, 9u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN1545}, 1269 {0u, 144u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN144}, 1270 {0u, 148u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN148}, 1271 {6u, 10u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN1546}, 1272 {0u, 141u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN141}, 1273 {0u, 145u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN145}, 1274 {0u, 138u, P20_4, P20_4_TCPWM0_TR_ONE_CNT_IN138}, 1275 {0u, 142u, P20_4, P20_4_TCPWM0_TR_ONE_CNT_IN142}, 1276 {0u, 135u, P20_5, P20_5_TCPWM0_TR_ONE_CNT_IN135}, 1277 {0u, 139u, P20_5, P20_5_TCPWM0_TR_ONE_CNT_IN139}, 1278 {0u, 132u, P20_6, P20_6_TCPWM0_TR_ONE_CNT_IN132}, 1279 {0u, 136u, P20_6, P20_6_TCPWM0_TR_ONE_CNT_IN136}, 1280 {0u, 129u, P20_7, P20_7_TCPWM0_TR_ONE_CNT_IN129}, 1281 {0u, 133u, P20_7, P20_7_TCPWM0_TR_ONE_CNT_IN133}, 1282 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1283 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1284 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1285 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1286 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1287 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1288 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1289 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1290 {0u, 114u, P21_4, P21_4_TCPWM0_TR_ONE_CNT_IN114}, 1291 {0u, 118u, P21_4, P21_4_TCPWM0_TR_ONE_CNT_IN118}, 1292 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1293 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1294 {0u, 108u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN108}, 1295 {0u, 112u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN112}, 1296 {0u, 105u, P21_7, P21_7_TCPWM0_TR_ONE_CNT_IN105}, 1297 {0u, 109u, P21_7, P21_7_TCPWM0_TR_ONE_CNT_IN109}, 1298 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 1299 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 1300 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1301 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1302 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1303 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1304 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1305 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1306 {0u, 90u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN90}, 1307 {0u, 94u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN94}, 1308 {0u, 87u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN87}, 1309 {0u, 91u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN91}, 1310 {0u, 84u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN84}, 1311 {0u, 88u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN88}, 1312 {0u, 81u, P22_7, P22_7_TCPWM0_TR_ONE_CNT_IN81}, 1313 {0u, 85u, P22_7, P22_7_TCPWM0_TR_ONE_CNT_IN85}, 1314 {0u, 82u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN82}, 1315 {3u, 24u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN792}, 1316 {3u, 25u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN793}, 1317 {3u, 27u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN795}, 1318 {3u, 28u, P23_2, P23_2_TCPWM0_TR_ONE_CNT_IN796}, 1319 {3u, 30u, P23_2, P23_2_TCPWM0_TR_ONE_CNT_IN798}, 1320 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1321 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1322 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1323 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1324 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1325 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1326 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1327 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1328 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1329 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1330 }; 1331 1332 #endif 1333
