1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_144_lqfp.h 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 144-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TVIIBE1M_144_LQFP_H_ 28 #define _CYHAL_TVIIBE1M_144_LQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_tviibe1m_144_lqfp TVIIBE1M 144-LQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the TVIIBE1M 144-LQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 144-LQFP package for the TVIIBE1M series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 61 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 62 63 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 64 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 65 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 66 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 67 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 68 69 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 70 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 71 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 72 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 73 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 74 75 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 76 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 77 78 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 79 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 80 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 81 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 82 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 83 84 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 85 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 86 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 87 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 88 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 89 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 90 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 91 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 92 93 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 94 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 95 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 96 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 97 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 98 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 99 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 100 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 101 102 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 103 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 104 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 105 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 106 107 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 108 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 109 110 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 111 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 112 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 113 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 114 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 115 116 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 117 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 118 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 119 120 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 121 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 122 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 123 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 124 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 125 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 126 127 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 128 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 129 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 130 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 131 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 132 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 133 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 134 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 135 136 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 137 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 138 P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2 139 P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3 140 P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4 141 P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5 142 143 P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0 144 P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1 145 P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2 146 P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3 147 148 P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0), //!< Port 16 Pin 0 149 P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1), //!< Port 16 Pin 1 150 P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2), //!< Port 16 Pin 2 151 152 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 153 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 154 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 155 P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3 156 P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4 157 158 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 159 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 160 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 161 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 162 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 163 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 164 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 165 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 166 167 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 168 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 169 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 170 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 171 P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4 172 173 P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0 174 P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1 175 P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2 176 P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3 177 178 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 179 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 180 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 181 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 182 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 183 P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6 184 185 P22_0 = CYHAL_GET_GPIO(CYHAL_PORT_22, 0), //!< Port 22 Pin 0 186 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 187 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 188 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 189 P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4 190 P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5 191 P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6 192 193 P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0 194 P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1 195 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 196 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 197 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 198 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 199 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 200 } cyhal_gpio_tviibe1m_144_lqfp_t; 201 202 /** Create generic name for the series/package specific type. */ 203 typedef cyhal_gpio_tviibe1m_144_lqfp_t cyhal_gpio_t; 204 205 /* Connection type definition */ 206 /** Represents an association between a pin and a resource */ 207 typedef struct 208 { 209 uint8_t block_num; //!< The block number of the resource with this connection 210 uint8_t channel_num; //!< The channel number of the block with this connection 211 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 212 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 213 } cyhal_resource_pin_mapping_t; 214 215 /* Pin connections */ 216 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 217 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 218 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 219 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[10]; 220 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 221 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 222 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 223 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[11]; 224 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 225 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 226 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 227 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2]; 228 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 229 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 230 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 231 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 232 /** Indicates that a pin map exists for cpuss_fault_out*/ 233 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 234 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 235 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[7]; 236 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 237 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 238 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 239 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 240 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 241 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 242 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 243 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 244 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 245 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 246 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 247 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 248 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 249 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 250 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 251 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 252 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 253 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 254 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 255 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 256 /** Indicates that a pin map exists for cpuss_trace_clock*/ 257 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 258 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 259 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 260 /** Indicates that a pin map exists for cpuss_trace_data*/ 261 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 262 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 263 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 264 /** Indicates that a pin map exists for lin_lin_en*/ 265 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 266 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 267 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[10]; 268 /** Indicates that a pin map exists for lin_lin_rx*/ 269 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 270 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 271 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[15]; 272 /** Indicates that a pin map exists for lin_lin_tx*/ 273 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 274 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 275 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[15]; 276 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 277 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 278 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 279 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2]; 280 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 281 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 282 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 283 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[8]; 284 /** Indicates that a pin map exists for pass_sarmux_pads*/ 285 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 286 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 287 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[54]; 288 /** Indicates that a pin map exists for peri_tr_io_input*/ 289 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 290 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 291 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[25]; 292 /** Indicates that a pin map exists for peri_tr_io_output*/ 293 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 294 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 295 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[5]; 296 /** Indicates that a pin map exists for scb_i2c_scl*/ 297 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 298 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 299 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; 300 /** Indicates that a pin map exists for scb_i2c_sda*/ 301 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 302 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 303 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[16]; 304 /** Indicates that a pin map exists for scb_spi_m_clk*/ 305 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 306 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 307 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12]; 308 /** Indicates that a pin map exists for scb_spi_m_miso*/ 309 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 310 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 311 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[16]; 312 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 313 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 314 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 315 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15]; 316 /** Indicates that a pin map exists for scb_spi_m_select0*/ 317 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 318 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 319 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13]; 320 /** Indicates that a pin map exists for scb_spi_m_select1*/ 321 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 322 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 323 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[12]; 324 /** Indicates that a pin map exists for scb_spi_m_select2*/ 325 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 326 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 327 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11]; 328 /** Indicates that a pin map exists for scb_spi_m_select3*/ 329 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 330 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 331 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; 332 /** Indicates that a pin map exists for scb_spi_s_clk*/ 333 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 334 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 335 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12]; 336 /** Indicates that a pin map exists for scb_spi_s_miso*/ 337 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 338 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 339 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[16]; 340 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 341 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 342 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 343 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15]; 344 /** Indicates that a pin map exists for scb_spi_s_select0*/ 345 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 346 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 347 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13]; 348 /** Indicates that a pin map exists for scb_spi_s_select1*/ 349 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 350 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 351 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[12]; 352 /** Indicates that a pin map exists for scb_spi_s_select2*/ 353 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 354 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 355 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11]; 356 /** Indicates that a pin map exists for scb_spi_s_select3*/ 357 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 358 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 359 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; 360 /** Indicates that a pin map exists for scb_uart_cts*/ 361 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 362 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 363 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[13]; 364 /** Indicates that a pin map exists for scb_uart_rts*/ 365 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 366 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 367 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12]; 368 /** Indicates that a pin map exists for scb_uart_rx*/ 369 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 370 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 371 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15]; 372 /** Indicates that a pin map exists for scb_uart_tx*/ 373 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 374 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 375 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[14]; 376 /** Indicates that a pin map exists for tcpwm_line*/ 377 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 378 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 379 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[127]; 380 /** Indicates that a pin map exists for tcpwm_line_compl*/ 381 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 382 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 383 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[126]; 384 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 385 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 386 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 387 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[246]; 388 389 #if defined(__cplusplus) 390 } 391 #endif /* __cplusplus */ 392 393 /** \} group_hal_impl_pin_package */ 394 395 #endif /* _CYHAL_TVIIBE1M_144_LQFP_H_ */ 396 397 398 /* [] END OF FILE */ 399
