1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_144_lqfp.c 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 144-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_TVIIBE1M_144_LQFP_H_) 31 #include "pin_packages/cyhal_tviibe1m_144_lqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[10] = { 36 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 38 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 39 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 40 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 41 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 42 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 43 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 44 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 45 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 46 }; 47 48 /* Connections for: canfd_ttcan_tx */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[11] = { 50 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 51 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 52 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 53 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 54 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 55 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 56 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 57 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 58 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 59 {1u, 1u, P22_0, P22_0_CANFD1_TTCAN_TX1}, 60 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 61 }; 62 63 /* Connections for: cpuss_cal_sup_nz */ 64 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 65 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 66 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 67 }; 68 69 /* Connections for: cpuss_clk_fm_pump */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 71 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 72 }; 73 74 /* Connections for: cpuss_fault_out */ 75 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[7] = { 76 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 77 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 78 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 79 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 80 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 81 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 82 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 83 }; 84 85 /* Connections for: cpuss_swj_swclk_tclk */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 87 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 88 }; 89 90 /* Connections for: cpuss_swj_swdio_tms */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 92 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 93 }; 94 95 /* Connections for: cpuss_swj_swdoe_tdi */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 97 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 98 }; 99 100 /* Connections for: cpuss_swj_swo_tdo */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 102 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 103 }; 104 105 /* Connections for: cpuss_swj_trstn */ 106 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 107 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 108 }; 109 110 /* Connections for: cpuss_trace_clock */ 111 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 112 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 113 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 114 }; 115 116 /* Connections for: cpuss_trace_data */ 117 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 118 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 119 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 120 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 121 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 122 {0u, 0u, P22_0, P22_0_CPUSS_TRACE_DATA0}, 123 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 124 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 125 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 126 }; 127 128 /* Connections for: lin_lin_en */ 129 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[10] = { 130 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 131 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 132 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 133 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 134 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 135 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 136 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 137 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 138 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 139 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 140 }; 141 142 /* Connections for: lin_lin_rx */ 143 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[15] = { 144 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 145 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 146 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 147 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 148 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 149 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 150 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 151 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 152 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 153 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 154 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 155 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 156 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 157 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 158 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 159 }; 160 161 /* Connections for: lin_lin_tx */ 162 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[15] = { 163 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 164 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 165 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 166 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 167 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 168 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 169 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 170 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 171 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 172 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 173 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 174 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 175 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 176 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 177 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 178 }; 179 180 /* Connections for: pass_sar_ext_mux_en */ 181 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 182 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 183 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 184 }; 185 186 /* Connections for: pass_sar_ext_mux_sel */ 187 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[8] = { 188 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 189 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 190 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 191 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 192 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 193 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 194 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 195 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 196 }; 197 198 /* Connections for: pass_sarmux_pads */ 199 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[54] = { 200 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 201 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 202 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 203 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 204 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 205 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 206 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 207 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 208 {0u, 8u, P7_0, HSIOM_SEL_GPIO}, 209 {0u, 9u, P7_1, HSIOM_SEL_GPIO}, 210 {0u, 10u, P7_2, HSIOM_SEL_GPIO}, 211 {0u, 11u, P7_3, HSIOM_SEL_GPIO}, 212 {0u, 12u, P7_4, HSIOM_SEL_GPIO}, 213 {0u, 13u, P7_5, HSIOM_SEL_GPIO}, 214 {0u, 14u, P7_6, HSIOM_SEL_GPIO}, 215 {0u, 15u, P7_7, HSIOM_SEL_GPIO}, 216 {0u, 16u, P8_1, HSIOM_SEL_GPIO}, 217 {0u, 17u, P8_2, HSIOM_SEL_GPIO}, 218 {0u, 18u, P8_3, HSIOM_SEL_GPIO}, 219 {0u, 20u, P9_0, HSIOM_SEL_GPIO}, 220 {0u, 21u, P9_1, HSIOM_SEL_GPIO}, 221 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 222 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 223 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 224 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 225 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 226 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 227 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 228 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 229 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 230 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 231 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 232 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 233 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 234 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 235 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 236 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 237 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 238 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 239 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 240 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 241 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 242 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 243 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 244 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 245 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 246 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 247 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 248 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 249 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 250 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 251 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 252 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 253 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 254 }; 255 256 /* Connections for: peri_tr_io_input */ 257 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 258 to know the index of the input or output trigger line. Store that in the channel_num field 259 instead. */ 260 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[25] = { 261 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 262 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 263 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 264 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 265 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 266 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 267 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 268 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 269 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 270 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 271 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 272 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 273 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 274 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 275 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 276 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 277 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 278 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 279 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 280 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 281 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 282 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 283 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 284 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 285 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 286 }; 287 288 /* Connections for: peri_tr_io_output */ 289 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 290 to know the index of the input or output trigger line. Store that in the channel_num field 291 instead. */ 292 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[5] = { 293 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 294 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 295 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 296 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 297 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 298 }; 299 300 /* Connections for: scb_i2c_scl */ 301 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = { 302 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 303 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 304 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 305 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 306 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 307 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 308 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 309 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 310 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 311 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 312 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 313 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 314 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 315 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 316 }; 317 318 /* Connections for: scb_i2c_sda */ 319 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[16] = { 320 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 321 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 322 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 323 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 324 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 325 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 326 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 327 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 328 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 329 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 330 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 331 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 332 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 333 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 334 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 335 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 336 }; 337 338 /* Connections for: scb_spi_m_clk */ 339 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12] = { 340 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 341 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 342 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 343 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 344 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 345 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 346 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 347 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 348 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 349 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 350 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 351 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 352 }; 353 354 /* Connections for: scb_spi_m_miso */ 355 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[16] = { 356 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 357 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 358 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 359 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 360 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 361 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 362 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 363 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 364 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 365 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 366 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 367 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 368 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 369 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 370 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 371 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 372 }; 373 374 /* Connections for: scb_spi_m_mosi */ 375 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15] = { 376 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 377 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 378 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 379 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 380 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 381 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 382 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 383 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 384 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 385 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 386 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 387 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 388 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 389 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 390 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 391 }; 392 393 /* Connections for: scb_spi_m_select0 */ 394 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13] = { 395 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 396 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 397 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 398 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 399 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 400 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 401 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 402 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 403 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 404 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 405 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 406 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 407 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 408 }; 409 410 /* Connections for: scb_spi_m_select1 */ 411 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[12] = { 412 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 413 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 414 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 415 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 416 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 417 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 418 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 419 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 420 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 421 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 422 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 423 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 424 }; 425 426 /* Connections for: scb_spi_m_select2 */ 427 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11] = { 428 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 429 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 430 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 431 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 432 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 433 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 434 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 435 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 436 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 437 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 438 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 439 }; 440 441 /* Connections for: scb_spi_m_select3 */ 442 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = { 443 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 444 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 445 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 446 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 447 }; 448 449 /* Connections for: scb_spi_s_clk */ 450 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12] = { 451 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 452 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 453 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 454 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 455 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 456 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 457 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 458 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 459 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 460 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 461 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 462 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 463 }; 464 465 /* Connections for: scb_spi_s_miso */ 466 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[16] = { 467 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 468 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 469 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 470 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 471 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 472 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 473 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 474 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 475 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 476 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 477 {3u, 0u, P17_1, P17_1_SCB3_SPI_MISO}, 478 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 479 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 480 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 481 {6u, 0u, P22_0, P22_0_SCB6_SPI_MISO}, 482 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 483 }; 484 485 /* Connections for: scb_spi_s_mosi */ 486 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15] = { 487 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 488 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 489 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 490 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 491 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 492 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 493 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 494 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 495 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 496 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 497 {3u, 0u, P17_2, P17_2_SCB3_SPI_MOSI}, 498 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 499 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 500 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 501 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 502 }; 503 504 /* Connections for: scb_spi_s_select0 */ 505 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13] = { 506 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 507 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 508 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 509 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 510 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 511 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 512 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 513 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 514 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 515 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 516 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 517 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 518 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 519 }; 520 521 /* Connections for: scb_spi_s_select1 */ 522 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[12] = { 523 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 524 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 525 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 526 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 527 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 528 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 529 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 530 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 531 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 532 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 533 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 534 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 535 }; 536 537 /* Connections for: scb_spi_s_select2 */ 538 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11] = { 539 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 540 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 541 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 542 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 543 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 544 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 545 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 546 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 547 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 548 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 549 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 550 }; 551 552 /* Connections for: scb_spi_s_select3 */ 553 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = { 554 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 555 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 556 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 557 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 558 }; 559 560 /* Connections for: scb_uart_cts */ 561 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[13] = { 562 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 563 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 564 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 565 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 566 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 567 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 568 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 569 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 570 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 571 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 572 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 573 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 574 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 575 }; 576 577 /* Connections for: scb_uart_rts */ 578 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12] = { 579 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 580 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 581 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 582 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 583 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 584 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 585 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 586 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 587 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 588 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 589 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 590 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 591 }; 592 593 /* Connections for: scb_uart_rx */ 594 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15] = { 595 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 596 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 597 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 598 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 599 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 600 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 601 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 602 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 603 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 604 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 605 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 606 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 607 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 608 {6u, 0u, P22_0, P22_0_SCB6_UART_RX}, 609 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 610 }; 611 612 /* Connections for: scb_uart_tx */ 613 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[14] = { 614 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 615 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 616 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 617 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 618 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 619 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 620 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 621 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 622 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 623 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 624 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 625 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 626 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 627 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 628 }; 629 630 /* Connections for: tcpwm_line */ 631 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[127] = { 632 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 633 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 634 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 635 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 636 {0u, 12u, P1_0, P1_0_TCPWM0_LINE12}, 637 {0u, 11u, P1_1, P1_1_TCPWM0_LINE11}, 638 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 639 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 640 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 641 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 642 {0u, 3u, P2_4, P2_4_TCPWM0_LINE3}, 643 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 644 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 645 {1u, 3u, P3_2, P3_2_TCPWM0_LINE259}, 646 {1u, 2u, P3_3, P3_3_TCPWM0_LINE258}, 647 {1u, 1u, P3_4, P3_4_TCPWM0_LINE257}, 648 {0u, 4u, P4_0, P4_0_TCPWM0_LINE4}, 649 {0u, 5u, P4_1, P4_1_TCPWM0_LINE5}, 650 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 651 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 652 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 653 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 654 {0u, 13u, P5_4, P5_4_TCPWM0_LINE13}, 655 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 656 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 657 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 658 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 659 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 660 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 661 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 662 {0u, 3u, P6_7, P6_7_TCPWM0_LINE3}, 663 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 664 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 665 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 666 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 667 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 668 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 669 {1u, 7u, P7_6, P7_6_TCPWM0_LINE263}, 670 {0u, 18u, P7_7, P7_7_TCPWM0_LINE18}, 671 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 672 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 673 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 674 {0u, 22u, P8_3, P8_3_TCPWM0_LINE22}, 675 {0u, 24u, P9_0, P9_0_TCPWM0_LINE24}, 676 {0u, 25u, P9_1, P9_1_TCPWM0_LINE25}, 677 {0u, 28u, P10_0, P10_0_TCPWM0_LINE28}, 678 {0u, 29u, P10_1, P10_1_TCPWM0_LINE29}, 679 {0u, 30u, P10_2, P10_2_TCPWM0_LINE30}, 680 {0u, 31u, P10_3, P10_3_TCPWM0_LINE31}, 681 {0u, 32u, P10_4, P10_4_TCPWM0_LINE32}, 682 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 683 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 684 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 685 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 686 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 687 {0u, 41u, P12_5, P12_5_TCPWM0_LINE41}, 688 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 689 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 690 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 691 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 692 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 693 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 694 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 695 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 696 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 697 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 698 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 699 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 700 {0u, 52u, P14_4, P14_4_TCPWM0_LINE52}, 701 {0u, 53u, P14_5, P14_5_TCPWM0_LINE53}, 702 {0u, 56u, P15_0, P15_0_TCPWM0_LINE56}, 703 {0u, 57u, P15_1, P15_1_TCPWM0_LINE57}, 704 {0u, 58u, P15_2, P15_2_TCPWM0_LINE58}, 705 {0u, 59u, P15_3, P15_3_TCPWM0_LINE59}, 706 {0u, 60u, P16_0, P16_0_TCPWM0_LINE60}, 707 {2u, 0u, P16_0, P16_0_TCPWM0_LINE512}, 708 {0u, 61u, P16_1, P16_1_TCPWM0_LINE61}, 709 {0u, 62u, P16_2, P16_2_TCPWM0_LINE62}, 710 {2u, 1u, P16_2, P16_2_TCPWM0_LINE513}, 711 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 712 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 713 {2u, 2u, P17_1, P17_1_TCPWM0_LINE514}, 714 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 715 {0u, 58u, P17_3, P17_3_TCPWM0_LINE58}, 716 {2u, 3u, P17_3, P17_3_TCPWM0_LINE515}, 717 {0u, 57u, P17_4, P17_4_TCPWM0_LINE57}, 718 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 719 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 720 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 721 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 722 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 723 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 724 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 725 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 726 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 727 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 728 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 729 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 730 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 731 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 732 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 733 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 734 {0u, 29u, P19_4, P19_4_TCPWM0_LINE29}, 735 {0u, 30u, P20_0, P20_0_TCPWM0_LINE30}, 736 {0u, 49u, P20_1, P20_1_TCPWM0_LINE49}, 737 {0u, 48u, P20_2, P20_2_TCPWM0_LINE48}, 738 {0u, 47u, P20_3, P20_3_TCPWM0_LINE47}, 739 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 740 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 741 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 742 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 743 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 744 {0u, 36u, P21_6, P21_6_TCPWM0_LINE36}, 745 {0u, 34u, P22_0, P22_0_TCPWM0_LINE34}, 746 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 747 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 748 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 749 {0u, 30u, P22_4, P22_4_TCPWM0_LINE30}, 750 {0u, 29u, P22_5, P22_5_TCPWM0_LINE29}, 751 {0u, 28u, P22_6, P22_6_TCPWM0_LINE28}, 752 {1u, 8u, P23_0, P23_0_TCPWM0_LINE264}, 753 {1u, 9u, P23_1, P23_1_TCPWM0_LINE265}, 754 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 755 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 756 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 757 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 758 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 759 }; 760 761 /* Connections for: tcpwm_line_compl */ 762 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[126] = { 763 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 764 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 765 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 766 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 767 {0u, 13u, P1_0, P1_0_TCPWM0_LINE_COMPL13}, 768 {0u, 12u, P1_1, P1_1_TCPWM0_LINE_COMPL12}, 769 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 770 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 771 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 772 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 773 {0u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL4}, 774 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 775 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 776 {0u, 0u, P3_2, P3_2_TCPWM0_LINE_COMPL0}, 777 {1u, 3u, P3_3, P3_3_TCPWM0_LINE_COMPL259}, 778 {1u, 2u, P3_4, P3_4_TCPWM0_LINE_COMPL258}, 779 {1u, 0u, P4_0, P4_0_TCPWM0_LINE_COMPL256}, 780 {0u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL4}, 781 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 782 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 783 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 784 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 785 {0u, 12u, P5_4, P5_4_TCPWM0_LINE_COMPL12}, 786 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 787 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 788 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 789 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 790 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 791 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 792 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 793 {1u, 3u, P6_7, P6_7_TCPWM0_LINE_COMPL259}, 794 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 795 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 796 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 797 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 798 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 799 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 800 {0u, 17u, P7_6, P7_6_TCPWM0_LINE_COMPL17}, 801 {1u, 7u, P7_7, P7_7_TCPWM0_LINE_COMPL263}, 802 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 803 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 804 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 805 {0u, 21u, P8_3, P8_3_TCPWM0_LINE_COMPL21}, 806 {0u, 23u, P9_0, P9_0_TCPWM0_LINE_COMPL23}, 807 {0u, 24u, P9_1, P9_1_TCPWM0_LINE_COMPL24}, 808 {0u, 27u, P10_0, P10_0_TCPWM0_LINE_COMPL27}, 809 {0u, 28u, P10_1, P10_1_TCPWM0_LINE_COMPL28}, 810 {0u, 29u, P10_2, P10_2_TCPWM0_LINE_COMPL29}, 811 {0u, 30u, P10_3, P10_3_TCPWM0_LINE_COMPL30}, 812 {0u, 31u, P10_4, P10_4_TCPWM0_LINE_COMPL31}, 813 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 814 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 815 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 816 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 817 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 818 {0u, 40u, P12_5, P12_5_TCPWM0_LINE_COMPL40}, 819 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 820 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 821 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 822 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 823 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 824 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 825 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 826 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 827 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 828 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 829 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 830 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 831 {0u, 51u, P14_4, P14_4_TCPWM0_LINE_COMPL51}, 832 {0u, 52u, P14_5, P14_5_TCPWM0_LINE_COMPL52}, 833 {0u, 55u, P15_0, P15_0_TCPWM0_LINE_COMPL55}, 834 {0u, 56u, P15_1, P15_1_TCPWM0_LINE_COMPL56}, 835 {0u, 57u, P15_2, P15_2_TCPWM0_LINE_COMPL57}, 836 {0u, 58u, P15_3, P15_3_TCPWM0_LINE_COMPL58}, 837 {0u, 59u, P16_0, P16_0_TCPWM0_LINE_COMPL59}, 838 {0u, 60u, P16_1, P16_1_TCPWM0_LINE_COMPL60}, 839 {2u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL512}, 840 {0u, 61u, P16_2, P16_2_TCPWM0_LINE_COMPL61}, 841 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 842 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 843 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 844 {2u, 2u, P17_2, P17_2_TCPWM0_LINE_COMPL514}, 845 {0u, 59u, P17_3, P17_3_TCPWM0_LINE_COMPL59}, 846 {0u, 58u, P17_4, P17_4_TCPWM0_LINE_COMPL58}, 847 {2u, 3u, P17_4, P17_4_TCPWM0_LINE_COMPL515}, 848 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 849 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 850 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 851 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 852 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 853 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 854 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 855 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 856 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 857 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 858 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 859 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 860 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 861 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 862 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 863 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 864 {0u, 28u, P19_4, P19_4_TCPWM0_LINE_COMPL28}, 865 {0u, 29u, P20_0, P20_0_TCPWM0_LINE_COMPL29}, 866 {0u, 30u, P20_1, P20_1_TCPWM0_LINE_COMPL30}, 867 {0u, 49u, P20_2, P20_2_TCPWM0_LINE_COMPL49}, 868 {0u, 48u, P20_3, P20_3_TCPWM0_LINE_COMPL48}, 869 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 870 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 871 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 872 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 873 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 874 {0u, 37u, P21_6, P21_6_TCPWM0_LINE_COMPL37}, 875 {0u, 35u, P22_0, P22_0_TCPWM0_LINE_COMPL35}, 876 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 877 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 878 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 879 {0u, 31u, P22_4, P22_4_TCPWM0_LINE_COMPL31}, 880 {0u, 30u, P22_5, P22_5_TCPWM0_LINE_COMPL30}, 881 {0u, 29u, P22_6, P22_6_TCPWM0_LINE_COMPL29}, 882 {0u, 27u, P23_0, P23_0_TCPWM0_LINE_COMPL27}, 883 {1u, 8u, P23_1, P23_1_TCPWM0_LINE_COMPL264}, 884 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 885 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 886 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 887 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 888 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 889 }; 890 891 /* Connections for: tcpwm_tr_one_cnt_in */ 892 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[246] = { 893 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 894 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 895 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 896 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 897 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 898 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 899 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 900 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 901 {0u, 36u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN36}, 902 {0u, 40u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN40}, 903 {0u, 33u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN33}, 904 {0u, 37u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN37}, 905 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 906 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 907 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 908 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 909 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 910 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 911 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 912 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 913 {0u, 9u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN9}, 914 {0u, 13u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN13}, 915 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 916 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 917 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 918 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 919 {0u, 1u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1}, 920 {3u, 9u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN777}, 921 {3u, 6u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN774}, 922 {3u, 10u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN778}, 923 {3u, 3u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN771}, 924 {3u, 7u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN775}, 925 {0u, 12u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN12}, 926 {3u, 1u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN769}, 927 {0u, 13u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN13}, 928 {0u, 15u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN15}, 929 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 930 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 931 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 932 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 933 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 934 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 935 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 936 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 937 {0u, 37u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN37}, 938 {0u, 39u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN39}, 939 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 940 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 941 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 942 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 943 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 944 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 945 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 946 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 947 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 948 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 949 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 950 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 951 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 952 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 953 {0u, 9u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN9}, 954 {3u, 10u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN778}, 955 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 956 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 957 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 958 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 959 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 960 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 961 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 962 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 963 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 964 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 965 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 966 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 967 {0u, 52u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN52}, 968 {3u, 21u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN789}, 969 {0u, 54u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN54}, 970 {3u, 22u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN790}, 971 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 972 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 973 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 974 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 975 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 976 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 977 {0u, 64u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN64}, 978 {0u, 66u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN66}, 979 {0u, 70u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN70}, 980 {0u, 72u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN72}, 981 {0u, 73u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN73}, 982 {0u, 75u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN75}, 983 {0u, 82u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN82}, 984 {0u, 84u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN84}, 985 {0u, 85u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN85}, 986 {0u, 87u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN87}, 987 {0u, 88u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN88}, 988 {0u, 90u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN90}, 989 {0u, 91u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN91}, 990 {0u, 93u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN93}, 991 {0u, 94u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN94}, 992 {0u, 96u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN96}, 993 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 994 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 995 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 996 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 997 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 998 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 999 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1000 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1001 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1002 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1003 {0u, 121u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN121}, 1004 {0u, 123u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN123}, 1005 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1006 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1007 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1008 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1009 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1010 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1011 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1012 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1013 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1014 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1015 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1016 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1017 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1018 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1019 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1020 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1021 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1022 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1023 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1024 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1025 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 1026 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 1027 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 1028 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 1029 {0u, 154u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN154}, 1030 {0u, 156u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN156}, 1031 {0u, 157u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN157}, 1032 {0u, 159u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN159}, 1033 {0u, 166u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN166}, 1034 {0u, 168u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN168}, 1035 {0u, 169u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN169}, 1036 {0u, 171u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN171}, 1037 {0u, 172u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN172}, 1038 {0u, 174u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN174}, 1039 {0u, 175u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN175}, 1040 {0u, 177u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN177}, 1041 {0u, 178u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN178}, 1042 {0u, 180u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN180}, 1043 {0u, 181u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN181}, 1044 {0u, 183u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN183}, 1045 {0u, 184u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN184}, 1046 {0u, 186u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN186}, 1047 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 1048 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 1049 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 1050 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 1051 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 1052 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 1053 {0u, 174u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN174}, 1054 {0u, 178u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN178}, 1055 {0u, 171u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN171}, 1056 {0u, 175u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN175}, 1057 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1058 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1059 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1060 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1061 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1062 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1063 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1064 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1065 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1066 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1067 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1068 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1069 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1070 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1071 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1072 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1073 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1074 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1075 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1076 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1077 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1078 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1079 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1080 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1081 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1082 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1083 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1084 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1085 {0u, 85u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN85}, 1086 {0u, 87u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN87}, 1087 {6u, 6u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN1542}, 1088 {0u, 88u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN88}, 1089 {0u, 90u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN90}, 1090 {6u, 7u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN1543}, 1091 {0u, 91u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN91}, 1092 {0u, 147u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN147}, 1093 {6u, 9u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN1545}, 1094 {0u, 144u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN144}, 1095 {0u, 148u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN148}, 1096 {6u, 10u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN1546}, 1097 {0u, 141u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN141}, 1098 {0u, 145u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN145}, 1099 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1100 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1101 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1102 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1103 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1104 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1105 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1106 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1107 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1108 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1109 {0u, 108u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN108}, 1110 {0u, 112u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN112}, 1111 {0u, 102u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN102}, 1112 {0u, 106u, P22_0, P22_0_TCPWM0_TR_ONE_CNT_IN106}, 1113 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1114 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1115 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1116 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1117 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1118 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1119 {0u, 90u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN90}, 1120 {0u, 94u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN94}, 1121 {0u, 87u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN87}, 1122 {0u, 91u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN91}, 1123 {0u, 84u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN84}, 1124 {0u, 88u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN88}, 1125 {0u, 82u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN82}, 1126 {3u, 24u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN792}, 1127 {3u, 25u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN793}, 1128 {3u, 27u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN795}, 1129 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1130 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1131 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1132 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1133 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1134 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1135 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1136 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1137 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1138 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1139 }; 1140 1141 #endif 1142
