1 /***************************************************************************//** 2 * \file cyhal_tviibe1m_100_lqfp.h 3 * 4 * \brief 5 * TVIIBE1M device GPIO HAL header for 100-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TVIIBE1M_100_LQFP_H_ 28 #define _CYHAL_TVIIBE1M_100_LQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_tviibe1m_100_lqfp TVIIBE1M 100-LQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the TVIIBE1M 100-LQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 100-LQFP package for the TVIIBE1M series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 61 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 62 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 63 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 64 65 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 66 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 67 68 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 69 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 70 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 71 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 72 73 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 74 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 75 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 76 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 77 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 78 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 79 80 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 81 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 82 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 83 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 84 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 85 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 86 87 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 88 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 89 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 90 91 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 92 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 93 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 94 95 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 96 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 97 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 98 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 99 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 100 101 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 102 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 103 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 104 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 105 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 106 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 107 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 108 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 109 110 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 111 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 112 P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2 113 P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3 114 115 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 116 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 117 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 118 119 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 120 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 121 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 122 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 123 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 124 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 125 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 126 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 127 128 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 129 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 130 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 131 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 132 133 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 134 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 135 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 136 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 137 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 138 139 P22_0 = CYHAL_GET_GPIO(CYHAL_PORT_22, 0), //!< Port 22 Pin 0 140 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 141 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 142 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 143 144 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 145 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 146 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 147 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 148 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 149 } cyhal_gpio_tviibe1m_100_lqfp_t; 150 151 /** Create generic name for the series/package specific type. */ 152 typedef cyhal_gpio_tviibe1m_100_lqfp_t cyhal_gpio_t; 153 154 /* Connection type definition */ 155 /** Represents an association between a pin and a resource */ 156 typedef struct 157 { 158 uint8_t block_num; //!< The block number of the resource with this connection 159 uint8_t channel_num; //!< The channel number of the block with this connection 160 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 161 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 162 } cyhal_resource_pin_mapping_t; 163 164 /* Pin connections */ 165 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 166 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 167 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 168 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[9]; 169 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 170 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 171 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 172 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[9]; 173 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 174 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 175 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 176 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2]; 177 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 178 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 179 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 180 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 181 /** Indicates that a pin map exists for cpuss_fault_out*/ 182 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 183 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 184 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5]; 185 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 186 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 187 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 188 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 189 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 190 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 191 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 192 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 193 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 194 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 195 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 196 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 197 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 198 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 199 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 200 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 201 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 202 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 203 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 204 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 205 /** Indicates that a pin map exists for cpuss_trace_clock*/ 206 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 207 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 208 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 209 /** Indicates that a pin map exists for cpuss_trace_data*/ 210 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 211 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 212 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 213 /** Indicates that a pin map exists for lin_lin_en*/ 214 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 215 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 216 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[8]; 217 /** Indicates that a pin map exists for lin_lin_rx*/ 218 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 219 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 220 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[12]; 221 /** Indicates that a pin map exists for lin_lin_tx*/ 222 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 223 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 224 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[9]; 225 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 226 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 227 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 228 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2]; 229 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 230 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 231 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 232 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[5]; 233 /** Indicates that a pin map exists for pass_sarmux_pads*/ 234 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 235 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 236 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[39]; 237 /** Indicates that a pin map exists for peri_tr_io_input*/ 238 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 239 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 240 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[14]; 241 /** Indicates that a pin map exists for peri_tr_io_output*/ 242 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 243 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 244 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4]; 245 /** Indicates that a pin map exists for scb_i2c_scl*/ 246 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 247 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 248 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10]; 249 /** Indicates that a pin map exists for scb_i2c_sda*/ 250 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 251 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 252 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; 253 /** Indicates that a pin map exists for scb_spi_m_clk*/ 254 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 255 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 256 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; 257 /** Indicates that a pin map exists for scb_spi_m_miso*/ 258 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 259 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 260 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; 261 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 262 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 263 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 264 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; 265 /** Indicates that a pin map exists for scb_spi_m_select0*/ 266 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 267 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 268 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10]; 269 /** Indicates that a pin map exists for scb_spi_m_select1*/ 270 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 271 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 272 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[6]; 273 /** Indicates that a pin map exists for scb_spi_m_select2*/ 274 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 275 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 276 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; 277 /** Indicates that a pin map exists for scb_spi_m_select3*/ 278 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 279 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 280 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3]; 281 /** Indicates that a pin map exists for scb_spi_s_clk*/ 282 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 283 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 284 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; 285 /** Indicates that a pin map exists for scb_spi_s_miso*/ 286 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 287 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 288 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; 289 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 290 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 291 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 292 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; 293 /** Indicates that a pin map exists for scb_spi_s_select0*/ 294 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 295 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 296 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10]; 297 /** Indicates that a pin map exists for scb_spi_s_select1*/ 298 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 299 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 300 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[6]; 301 /** Indicates that a pin map exists for scb_spi_s_select2*/ 302 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 303 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 304 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; 305 /** Indicates that a pin map exists for scb_spi_s_select3*/ 306 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 307 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 308 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3]; 309 /** Indicates that a pin map exists for scb_uart_cts*/ 310 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 311 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 312 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; 313 /** Indicates that a pin map exists for scb_uart_rts*/ 314 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 315 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 316 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9]; 317 /** Indicates that a pin map exists for scb_uart_rx*/ 318 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 319 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 320 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; 321 /** Indicates that a pin map exists for scb_uart_tx*/ 322 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 323 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 324 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; 325 /** Indicates that a pin map exists for tcpwm_line*/ 326 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 327 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 328 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80]; 329 /** Indicates that a pin map exists for tcpwm_line_compl*/ 330 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 331 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 332 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80]; 333 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 334 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 335 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 336 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[154]; 337 338 #if defined(__cplusplus) 339 } 340 #endif /* __cplusplus */ 341 342 /** \} group_hal_impl_pin_package */ 343 344 #endif /* _CYHAL_TVIIBE1M_100_LQFP_H_ */ 345 346 347 /* [] END OF FILE */ 348
