1 /***************************************************************************//**
2 * \file cyhal_triggers_xmc7100.h
3 *
4 * \brief
5 * XMC7100 family HAL triggers header
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYHAL_TRIGGERS_XMC7100_H_
28 #define _CYHAL_TRIGGERS_XMC7100_H_
29 
30 /**
31  * \addtogroup group_hal_impl_triggers_xmc7100 XMC7100
32  * \ingroup group_hal_impl_triggers
33  * \{
34  * Trigger connections for xmc7100
35  */
36 
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif /* __cplusplus */
40 
41 /** \cond INTERNAL */
42 /** @brief Name of each input trigger. */
43 typedef enum
44 {
45     _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero
46     _CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = 1, //!< audioss[0].tr_i2s_rx_req
47     _CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = 2, //!< audioss[1].tr_i2s_rx_req
48     _CYHAL_TRIGGER_AUDIOSS2_TR_I2S_RX_REQ = 3, //!< audioss[2].tr_i2s_rx_req
49     _CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = 4, //!< audioss[0].tr_i2s_tx_req
50     _CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = 5, //!< audioss[1].tr_i2s_tx_req
51     _CYHAL_TRIGGER_AUDIOSS2_TR_I2S_TX_REQ = 6, //!< audioss[2].tr_i2s_tx_req
52     _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 7, //!< canfd[0].tr_dbg_dma_req[0]
53     _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = 8, //!< canfd[0].tr_dbg_dma_req[1]
54     _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = 9, //!< canfd[0].tr_dbg_dma_req[2]
55     _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3 = 10, //!< canfd[0].tr_dbg_dma_req[3]
56     _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = 11, //!< canfd[1].tr_dbg_dma_req[0]
57     _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = 12, //!< canfd[1].tr_dbg_dma_req[1]
58     _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = 13, //!< canfd[1].tr_dbg_dma_req[2]
59     _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3 = 14, //!< canfd[1].tr_dbg_dma_req[3]
60     _CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 15, //!< canfd[0].tr_fifo0[0]
61     _CYHAL_TRIGGER_CANFD0_TR_FIFO01 = 16, //!< canfd[0].tr_fifo0[1]
62     _CYHAL_TRIGGER_CANFD0_TR_FIFO02 = 17, //!< canfd[0].tr_fifo0[2]
63     _CYHAL_TRIGGER_CANFD0_TR_FIFO03 = 18, //!< canfd[0].tr_fifo0[3]
64     _CYHAL_TRIGGER_CANFD1_TR_FIFO00 = 19, //!< canfd[1].tr_fifo0[0]
65     _CYHAL_TRIGGER_CANFD1_TR_FIFO01 = 20, //!< canfd[1].tr_fifo0[1]
66     _CYHAL_TRIGGER_CANFD1_TR_FIFO02 = 21, //!< canfd[1].tr_fifo0[2]
67     _CYHAL_TRIGGER_CANFD1_TR_FIFO03 = 22, //!< canfd[1].tr_fifo0[3]
68     _CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 23, //!< canfd[0].tr_fifo1[0]
69     _CYHAL_TRIGGER_CANFD0_TR_FIFO11 = 24, //!< canfd[0].tr_fifo1[1]
70     _CYHAL_TRIGGER_CANFD0_TR_FIFO12 = 25, //!< canfd[0].tr_fifo1[2]
71     _CYHAL_TRIGGER_CANFD0_TR_FIFO13 = 26, //!< canfd[0].tr_fifo1[3]
72     _CYHAL_TRIGGER_CANFD1_TR_FIFO10 = 27, //!< canfd[1].tr_fifo1[0]
73     _CYHAL_TRIGGER_CANFD1_TR_FIFO11 = 28, //!< canfd[1].tr_fifo1[1]
74     _CYHAL_TRIGGER_CANFD1_TR_FIFO12 = 29, //!< canfd[1].tr_fifo1[2]
75     _CYHAL_TRIGGER_CANFD1_TR_FIFO13 = 30, //!< canfd[1].tr_fifo1[3]
76     _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 31, //!< canfd[0].tr_tmp_rtp_out[0]
77     _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = 32, //!< canfd[0].tr_tmp_rtp_out[1]
78     _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = 33, //!< canfd[0].tr_tmp_rtp_out[2]
79     _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3 = 34, //!< canfd[0].tr_tmp_rtp_out[3]
80     _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = 35, //!< canfd[1].tr_tmp_rtp_out[0]
81     _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = 36, //!< canfd[1].tr_tmp_rtp_out[1]
82     _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = 37, //!< canfd[1].tr_tmp_rtp_out[2]
83     _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3 = 38, //!< canfd[1].tr_tmp_rtp_out[3]
84     _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 39, //!< cpuss.cti_tr_out[0]
85     _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 40, //!< cpuss.cti_tr_out[1]
86     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 41, //!< cpuss.dmac_tr_out[0]
87     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 42, //!< cpuss.dmac_tr_out[1]
88     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = 43, //!< cpuss.dmac_tr_out[2]
89     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = 44, //!< cpuss.dmac_tr_out[3]
90     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4 = 45, //!< cpuss.dmac_tr_out[4]
91     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5 = 46, //!< cpuss.dmac_tr_out[5]
92     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6 = 47, //!< cpuss.dmac_tr_out[6]
93     _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7 = 48, //!< cpuss.dmac_tr_out[7]
94     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 49, //!< cpuss.dw0_tr_out[0]
95     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 50, //!< cpuss.dw0_tr_out[1]
96     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 51, //!< cpuss.dw0_tr_out[2]
97     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 52, //!< cpuss.dw0_tr_out[3]
98     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 53, //!< cpuss.dw0_tr_out[4]
99     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 54, //!< cpuss.dw0_tr_out[5]
100     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 55, //!< cpuss.dw0_tr_out[6]
101     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 56, //!< cpuss.dw0_tr_out[7]
102     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 57, //!< cpuss.dw0_tr_out[8]
103     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 58, //!< cpuss.dw0_tr_out[9]
104     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 59, //!< cpuss.dw0_tr_out[10]
105     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 60, //!< cpuss.dw0_tr_out[11]
106     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 61, //!< cpuss.dw0_tr_out[12]
107     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 62, //!< cpuss.dw0_tr_out[13]
108     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 63, //!< cpuss.dw0_tr_out[14]
109     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 64, //!< cpuss.dw0_tr_out[15]
110     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 65, //!< cpuss.dw0_tr_out[16]
111     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 66, //!< cpuss.dw0_tr_out[17]
112     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 67, //!< cpuss.dw0_tr_out[18]
113     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 68, //!< cpuss.dw0_tr_out[19]
114     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 69, //!< cpuss.dw0_tr_out[20]
115     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 70, //!< cpuss.dw0_tr_out[21]
116     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 71, //!< cpuss.dw0_tr_out[22]
117     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 72, //!< cpuss.dw0_tr_out[23]
118     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 73, //!< cpuss.dw0_tr_out[24]
119     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 74, //!< cpuss.dw0_tr_out[25]
120     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 75, //!< cpuss.dw0_tr_out[26]
121     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 76, //!< cpuss.dw0_tr_out[27]
122     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 77, //!< cpuss.dw0_tr_out[28]
123     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = 78, //!< cpuss.dw0_tr_out[29]
124     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = 79, //!< cpuss.dw0_tr_out[30]
125     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = 80, //!< cpuss.dw0_tr_out[31]
126     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = 81, //!< cpuss.dw0_tr_out[32]
127     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = 82, //!< cpuss.dw0_tr_out[33]
128     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = 83, //!< cpuss.dw0_tr_out[34]
129     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = 84, //!< cpuss.dw0_tr_out[35]
130     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = 85, //!< cpuss.dw0_tr_out[36]
131     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = 86, //!< cpuss.dw0_tr_out[37]
132     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = 87, //!< cpuss.dw0_tr_out[38]
133     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = 88, //!< cpuss.dw0_tr_out[39]
134     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = 89, //!< cpuss.dw0_tr_out[40]
135     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = 90, //!< cpuss.dw0_tr_out[41]
136     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = 91, //!< cpuss.dw0_tr_out[42]
137     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = 92, //!< cpuss.dw0_tr_out[43]
138     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = 93, //!< cpuss.dw0_tr_out[44]
139     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = 94, //!< cpuss.dw0_tr_out[45]
140     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = 95, //!< cpuss.dw0_tr_out[46]
141     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = 96, //!< cpuss.dw0_tr_out[47]
142     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = 97, //!< cpuss.dw0_tr_out[48]
143     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = 98, //!< cpuss.dw0_tr_out[49]
144     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = 99, //!< cpuss.dw0_tr_out[50]
145     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = 100, //!< cpuss.dw0_tr_out[51]
146     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = 101, //!< cpuss.dw0_tr_out[52]
147     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = 102, //!< cpuss.dw0_tr_out[53]
148     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = 103, //!< cpuss.dw0_tr_out[54]
149     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = 104, //!< cpuss.dw0_tr_out[55]
150     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = 105, //!< cpuss.dw0_tr_out[56]
151     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = 106, //!< cpuss.dw0_tr_out[57]
152     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = 107, //!< cpuss.dw0_tr_out[58]
153     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = 108, //!< cpuss.dw0_tr_out[59]
154     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = 109, //!< cpuss.dw0_tr_out[60]
155     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = 110, //!< cpuss.dw0_tr_out[61]
156     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = 111, //!< cpuss.dw0_tr_out[62]
157     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = 112, //!< cpuss.dw0_tr_out[63]
158     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = 113, //!< cpuss.dw0_tr_out[64]
159     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = 114, //!< cpuss.dw0_tr_out[65]
160     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = 115, //!< cpuss.dw0_tr_out[66]
161     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = 116, //!< cpuss.dw0_tr_out[67]
162     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = 117, //!< cpuss.dw0_tr_out[68]
163     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = 118, //!< cpuss.dw0_tr_out[69]
164     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = 119, //!< cpuss.dw0_tr_out[70]
165     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = 120, //!< cpuss.dw0_tr_out[71]
166     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = 121, //!< cpuss.dw0_tr_out[72]
167     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = 122, //!< cpuss.dw0_tr_out[73]
168     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = 123, //!< cpuss.dw0_tr_out[74]
169     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = 124, //!< cpuss.dw0_tr_out[75]
170     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = 125, //!< cpuss.dw0_tr_out[76]
171     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = 126, //!< cpuss.dw0_tr_out[77]
172     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = 127, //!< cpuss.dw0_tr_out[78]
173     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = 128, //!< cpuss.dw0_tr_out[79]
174     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = 129, //!< cpuss.dw0_tr_out[80]
175     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = 130, //!< cpuss.dw0_tr_out[81]
176     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = 131, //!< cpuss.dw0_tr_out[82]
177     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = 132, //!< cpuss.dw0_tr_out[83]
178     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = 133, //!< cpuss.dw0_tr_out[84]
179     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = 134, //!< cpuss.dw0_tr_out[85]
180     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = 135, //!< cpuss.dw0_tr_out[86]
181     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = 136, //!< cpuss.dw0_tr_out[87]
182     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = 137, //!< cpuss.dw0_tr_out[88]
183     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89 = 138, //!< cpuss.dw0_tr_out[89]
184     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90 = 139, //!< cpuss.dw0_tr_out[90]
185     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91 = 140, //!< cpuss.dw0_tr_out[91]
186     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT92 = 141, //!< cpuss.dw0_tr_out[92]
187     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT93 = 142, //!< cpuss.dw0_tr_out[93]
188     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT94 = 143, //!< cpuss.dw0_tr_out[94]
189     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT95 = 144, //!< cpuss.dw0_tr_out[95]
190     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT96 = 145, //!< cpuss.dw0_tr_out[96]
191     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT97 = 146, //!< cpuss.dw0_tr_out[97]
192     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT98 = 147, //!< cpuss.dw0_tr_out[98]
193     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT99 = 148, //!< cpuss.dw0_tr_out[99]
194     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 149, //!< cpuss.dw1_tr_out[0]
195     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 150, //!< cpuss.dw1_tr_out[1]
196     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 151, //!< cpuss.dw1_tr_out[2]
197     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 152, //!< cpuss.dw1_tr_out[3]
198     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 153, //!< cpuss.dw1_tr_out[4]
199     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 154, //!< cpuss.dw1_tr_out[5]
200     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 155, //!< cpuss.dw1_tr_out[6]
201     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 156, //!< cpuss.dw1_tr_out[7]
202     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 157, //!< cpuss.dw1_tr_out[8]
203     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 158, //!< cpuss.dw1_tr_out[9]
204     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 159, //!< cpuss.dw1_tr_out[10]
205     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 160, //!< cpuss.dw1_tr_out[11]
206     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 161, //!< cpuss.dw1_tr_out[12]
207     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 162, //!< cpuss.dw1_tr_out[13]
208     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 163, //!< cpuss.dw1_tr_out[14]
209     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 164, //!< cpuss.dw1_tr_out[15]
210     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 165, //!< cpuss.dw1_tr_out[16]
211     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 166, //!< cpuss.dw1_tr_out[17]
212     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 167, //!< cpuss.dw1_tr_out[18]
213     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 168, //!< cpuss.dw1_tr_out[19]
214     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 169, //!< cpuss.dw1_tr_out[20]
215     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 170, //!< cpuss.dw1_tr_out[21]
216     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 171, //!< cpuss.dw1_tr_out[22]
217     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 172, //!< cpuss.dw1_tr_out[23]
218     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 173, //!< cpuss.dw1_tr_out[24]
219     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 174, //!< cpuss.dw1_tr_out[25]
220     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 175, //!< cpuss.dw1_tr_out[26]
221     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 176, //!< cpuss.dw1_tr_out[27]
222     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 177, //!< cpuss.dw1_tr_out[28]
223     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = 178, //!< cpuss.dw1_tr_out[29]
224     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = 179, //!< cpuss.dw1_tr_out[30]
225     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = 180, //!< cpuss.dw1_tr_out[31]
226     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = 181, //!< cpuss.dw1_tr_out[32]
227     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33 = 182, //!< cpuss.dw1_tr_out[33]
228     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34 = 183, //!< cpuss.dw1_tr_out[34]
229     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35 = 184, //!< cpuss.dw1_tr_out[35]
230     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36 = 185, //!< cpuss.dw1_tr_out[36]
231     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37 = 186, //!< cpuss.dw1_tr_out[37]
232     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38 = 187, //!< cpuss.dw1_tr_out[38]
233     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39 = 188, //!< cpuss.dw1_tr_out[39]
234     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40 = 189, //!< cpuss.dw1_tr_out[40]
235     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41 = 190, //!< cpuss.dw1_tr_out[41]
236     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42 = 191, //!< cpuss.dw1_tr_out[42]
237     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43 = 192, //!< cpuss.dw1_tr_out[43]
238     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT44 = 193, //!< cpuss.dw1_tr_out[44]
239     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT45 = 194, //!< cpuss.dw1_tr_out[45]
240     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT46 = 195, //!< cpuss.dw1_tr_out[46]
241     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT47 = 196, //!< cpuss.dw1_tr_out[47]
242     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT48 = 197, //!< cpuss.dw1_tr_out[48]
243     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT49 = 198, //!< cpuss.dw1_tr_out[49]
244     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT50 = 199, //!< cpuss.dw1_tr_out[50]
245     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT51 = 200, //!< cpuss.dw1_tr_out[51]
246     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT52 = 201, //!< cpuss.dw1_tr_out[52]
247     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT53 = 202, //!< cpuss.dw1_tr_out[53]
248     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT54 = 203, //!< cpuss.dw1_tr_out[54]
249     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT55 = 204, //!< cpuss.dw1_tr_out[55]
250     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT56 = 205, //!< cpuss.dw1_tr_out[56]
251     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT57 = 206, //!< cpuss.dw1_tr_out[57]
252     _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 207, //!< cpuss.tr_fault[0]
253     _CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 208, //!< cpuss.tr_fault[1]
254     _CYHAL_TRIGGER_CPUSS_TR_FAULT2 = 209, //!< cpuss.tr_fault[2]
255     _CYHAL_TRIGGER_CPUSS_TR_FAULT3 = 210, //!< cpuss.tr_fault[3]
256     _CYHAL_TRIGGER_EVTGEN0_TR_OUT0 = 211, //!< evtgen[0].tr_out[0]
257     _CYHAL_TRIGGER_EVTGEN0_TR_OUT1 = 212, //!< evtgen[0].tr_out[1]
258     _CYHAL_TRIGGER_EVTGEN0_TR_OUT2 = 213, //!< evtgen[0].tr_out[2]
259     _CYHAL_TRIGGER_EVTGEN0_TR_OUT3 = 214, //!< evtgen[0].tr_out[3]
260     _CYHAL_TRIGGER_EVTGEN0_TR_OUT4 = 215, //!< evtgen[0].tr_out[4]
261     _CYHAL_TRIGGER_EVTGEN0_TR_OUT5 = 216, //!< evtgen[0].tr_out[5]
262     _CYHAL_TRIGGER_EVTGEN0_TR_OUT6 = 217, //!< evtgen[0].tr_out[6]
263     _CYHAL_TRIGGER_EVTGEN0_TR_OUT7 = 218, //!< evtgen[0].tr_out[7]
264     _CYHAL_TRIGGER_EVTGEN0_TR_OUT8 = 219, //!< evtgen[0].tr_out[8]
265     _CYHAL_TRIGGER_EVTGEN0_TR_OUT9 = 220, //!< evtgen[0].tr_out[9]
266     _CYHAL_TRIGGER_EVTGEN0_TR_OUT10 = 221, //!< evtgen[0].tr_out[10]
267     _CYHAL_TRIGGER_EVTGEN0_TR_OUT11 = 222, //!< evtgen[0].tr_out[11]
268     _CYHAL_TRIGGER_EVTGEN0_TR_OUT12 = 223, //!< evtgen[0].tr_out[12]
269     _CYHAL_TRIGGER_EVTGEN0_TR_OUT13 = 224, //!< evtgen[0].tr_out[13]
270     _CYHAL_TRIGGER_EVTGEN0_TR_OUT14 = 225, //!< evtgen[0].tr_out[14]
271     _CYHAL_TRIGGER_EVTGEN0_TR_OUT15 = 226, //!< evtgen[0].tr_out[15]
272     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 = 227, //!< pass[0].tr_sar_ch_done[0]
273     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 = 228, //!< pass[0].tr_sar_ch_done[1]
274     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 = 229, //!< pass[0].tr_sar_ch_done[2]
275     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 = 230, //!< pass[0].tr_sar_ch_done[3]
276     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 = 231, //!< pass[0].tr_sar_ch_done[4]
277     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 = 232, //!< pass[0].tr_sar_ch_done[5]
278     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 = 233, //!< pass[0].tr_sar_ch_done[6]
279     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 = 234, //!< pass[0].tr_sar_ch_done[7]
280     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 = 235, //!< pass[0].tr_sar_ch_done[8]
281     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 = 236, //!< pass[0].tr_sar_ch_done[9]
282     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 = 237, //!< pass[0].tr_sar_ch_done[10]
283     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 = 238, //!< pass[0].tr_sar_ch_done[11]
284     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 = 239, //!< pass[0].tr_sar_ch_done[12]
285     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 = 240, //!< pass[0].tr_sar_ch_done[13]
286     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 = 241, //!< pass[0].tr_sar_ch_done[14]
287     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 = 242, //!< pass[0].tr_sar_ch_done[15]
288     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 = 243, //!< pass[0].tr_sar_ch_done[16]
289     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 = 244, //!< pass[0].tr_sar_ch_done[17]
290     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 = 245, //!< pass[0].tr_sar_ch_done[18]
291     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 = 246, //!< pass[0].tr_sar_ch_done[19]
292     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 = 247, //!< pass[0].tr_sar_ch_done[20]
293     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 = 248, //!< pass[0].tr_sar_ch_done[21]
294     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 = 249, //!< pass[0].tr_sar_ch_done[22]
295     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 = 250, //!< pass[0].tr_sar_ch_done[23]
296     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24 = 251, //!< pass[0].tr_sar_ch_done[24]
297     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25 = 252, //!< pass[0].tr_sar_ch_done[25]
298     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26 = 253, //!< pass[0].tr_sar_ch_done[26]
299     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27 = 254, //!< pass[0].tr_sar_ch_done[27]
300     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28 = 255, //!< pass[0].tr_sar_ch_done[28]
301     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29 = 256, //!< pass[0].tr_sar_ch_done[29]
302     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30 = 257, //!< pass[0].tr_sar_ch_done[30]
303     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31 = 258, //!< pass[0].tr_sar_ch_done[31]
304     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 = 259, //!< pass[0].tr_sar_ch_done[32]
305     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 = 260, //!< pass[0].tr_sar_ch_done[33]
306     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 = 261, //!< pass[0].tr_sar_ch_done[34]
307     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 = 262, //!< pass[0].tr_sar_ch_done[35]
308     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 = 263, //!< pass[0].tr_sar_ch_done[36]
309     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 = 264, //!< pass[0].tr_sar_ch_done[37]
310     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 = 265, //!< pass[0].tr_sar_ch_done[38]
311     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 = 266, //!< pass[0].tr_sar_ch_done[39]
312     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 = 267, //!< pass[0].tr_sar_ch_done[40]
313     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 = 268, //!< pass[0].tr_sar_ch_done[41]
314     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 = 269, //!< pass[0].tr_sar_ch_done[42]
315     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 = 270, //!< pass[0].tr_sar_ch_done[43]
316     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 = 271, //!< pass[0].tr_sar_ch_done[44]
317     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 = 272, //!< pass[0].tr_sar_ch_done[45]
318     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 = 273, //!< pass[0].tr_sar_ch_done[46]
319     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 = 274, //!< pass[0].tr_sar_ch_done[47]
320     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 = 275, //!< pass[0].tr_sar_ch_done[48]
321     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 = 276, //!< pass[0].tr_sar_ch_done[49]
322     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 = 277, //!< pass[0].tr_sar_ch_done[50]
323     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 = 278, //!< pass[0].tr_sar_ch_done[51]
324     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 = 279, //!< pass[0].tr_sar_ch_done[52]
325     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 = 280, //!< pass[0].tr_sar_ch_done[53]
326     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 = 281, //!< pass[0].tr_sar_ch_done[54]
327     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 = 282, //!< pass[0].tr_sar_ch_done[55]
328     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 = 283, //!< pass[0].tr_sar_ch_done[56]
329     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 = 284, //!< pass[0].tr_sar_ch_done[57]
330     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 = 285, //!< pass[0].tr_sar_ch_done[58]
331     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 = 286, //!< pass[0].tr_sar_ch_done[59]
332     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 = 287, //!< pass[0].tr_sar_ch_done[60]
333     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 = 288, //!< pass[0].tr_sar_ch_done[61]
334     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 = 289, //!< pass[0].tr_sar_ch_done[62]
335     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 = 290, //!< pass[0].tr_sar_ch_done[63]
336     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 = 291, //!< pass[0].tr_sar_ch_done[64]
337     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 = 292, //!< pass[0].tr_sar_ch_done[65]
338     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 = 293, //!< pass[0].tr_sar_ch_done[66]
339     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 = 294, //!< pass[0].tr_sar_ch_done[67]
340     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 = 295, //!< pass[0].tr_sar_ch_done[68]
341     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 = 296, //!< pass[0].tr_sar_ch_done[69]
342     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 = 297, //!< pass[0].tr_sar_ch_done[70]
343     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 = 298, //!< pass[0].tr_sar_ch_done[71]
344     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = 299, //!< pass[0].tr_sar_ch_rangevio[0]
345     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = 300, //!< pass[0].tr_sar_ch_rangevio[1]
346     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = 301, //!< pass[0].tr_sar_ch_rangevio[2]
347     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = 302, //!< pass[0].tr_sar_ch_rangevio[3]
348     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = 303, //!< pass[0].tr_sar_ch_rangevio[4]
349     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = 304, //!< pass[0].tr_sar_ch_rangevio[5]
350     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = 305, //!< pass[0].tr_sar_ch_rangevio[6]
351     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = 306, //!< pass[0].tr_sar_ch_rangevio[7]
352     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = 307, //!< pass[0].tr_sar_ch_rangevio[8]
353     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = 308, //!< pass[0].tr_sar_ch_rangevio[9]
354     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = 309, //!< pass[0].tr_sar_ch_rangevio[10]
355     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = 310, //!< pass[0].tr_sar_ch_rangevio[11]
356     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = 311, //!< pass[0].tr_sar_ch_rangevio[12]
357     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = 312, //!< pass[0].tr_sar_ch_rangevio[13]
358     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = 313, //!< pass[0].tr_sar_ch_rangevio[14]
359     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = 314, //!< pass[0].tr_sar_ch_rangevio[15]
360     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = 315, //!< pass[0].tr_sar_ch_rangevio[16]
361     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = 316, //!< pass[0].tr_sar_ch_rangevio[17]
362     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = 317, //!< pass[0].tr_sar_ch_rangevio[18]
363     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = 318, //!< pass[0].tr_sar_ch_rangevio[19]
364     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = 319, //!< pass[0].tr_sar_ch_rangevio[20]
365     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = 320, //!< pass[0].tr_sar_ch_rangevio[21]
366     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = 321, //!< pass[0].tr_sar_ch_rangevio[22]
367     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = 322, //!< pass[0].tr_sar_ch_rangevio[23]
368     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO24 = 323, //!< pass[0].tr_sar_ch_rangevio[24]
369     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO25 = 324, //!< pass[0].tr_sar_ch_rangevio[25]
370     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO26 = 325, //!< pass[0].tr_sar_ch_rangevio[26]
371     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO27 = 326, //!< pass[0].tr_sar_ch_rangevio[27]
372     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO28 = 327, //!< pass[0].tr_sar_ch_rangevio[28]
373     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO29 = 328, //!< pass[0].tr_sar_ch_rangevio[29]
374     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO30 = 329, //!< pass[0].tr_sar_ch_rangevio[30]
375     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO31 = 330, //!< pass[0].tr_sar_ch_rangevio[31]
376     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = 331, //!< pass[0].tr_sar_ch_rangevio[32]
377     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = 332, //!< pass[0].tr_sar_ch_rangevio[33]
378     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = 333, //!< pass[0].tr_sar_ch_rangevio[34]
379     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = 334, //!< pass[0].tr_sar_ch_rangevio[35]
380     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = 335, //!< pass[0].tr_sar_ch_rangevio[36]
381     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = 336, //!< pass[0].tr_sar_ch_rangevio[37]
382     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = 337, //!< pass[0].tr_sar_ch_rangevio[38]
383     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = 338, //!< pass[0].tr_sar_ch_rangevio[39]
384     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = 339, //!< pass[0].tr_sar_ch_rangevio[40]
385     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = 340, //!< pass[0].tr_sar_ch_rangevio[41]
386     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = 341, //!< pass[0].tr_sar_ch_rangevio[42]
387     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = 342, //!< pass[0].tr_sar_ch_rangevio[43]
388     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = 343, //!< pass[0].tr_sar_ch_rangevio[44]
389     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = 344, //!< pass[0].tr_sar_ch_rangevio[45]
390     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = 345, //!< pass[0].tr_sar_ch_rangevio[46]
391     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = 346, //!< pass[0].tr_sar_ch_rangevio[47]
392     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = 347, //!< pass[0].tr_sar_ch_rangevio[48]
393     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = 348, //!< pass[0].tr_sar_ch_rangevio[49]
394     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = 349, //!< pass[0].tr_sar_ch_rangevio[50]
395     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = 350, //!< pass[0].tr_sar_ch_rangevio[51]
396     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = 351, //!< pass[0].tr_sar_ch_rangevio[52]
397     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = 352, //!< pass[0].tr_sar_ch_rangevio[53]
398     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = 353, //!< pass[0].tr_sar_ch_rangevio[54]
399     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = 354, //!< pass[0].tr_sar_ch_rangevio[55]
400     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = 355, //!< pass[0].tr_sar_ch_rangevio[56]
401     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = 356, //!< pass[0].tr_sar_ch_rangevio[57]
402     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = 357, //!< pass[0].tr_sar_ch_rangevio[58]
403     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = 358, //!< pass[0].tr_sar_ch_rangevio[59]
404     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = 359, //!< pass[0].tr_sar_ch_rangevio[60]
405     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = 360, //!< pass[0].tr_sar_ch_rangevio[61]
406     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = 361, //!< pass[0].tr_sar_ch_rangevio[62]
407     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = 362, //!< pass[0].tr_sar_ch_rangevio[63]
408     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = 363, //!< pass[0].tr_sar_ch_rangevio[64]
409     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = 364, //!< pass[0].tr_sar_ch_rangevio[65]
410     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = 365, //!< pass[0].tr_sar_ch_rangevio[66]
411     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = 366, //!< pass[0].tr_sar_ch_rangevio[67]
412     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = 367, //!< pass[0].tr_sar_ch_rangevio[68]
413     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = 368, //!< pass[0].tr_sar_ch_rangevio[69]
414     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = 369, //!< pass[0].tr_sar_ch_rangevio[70]
415     _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = 370, //!< pass[0].tr_sar_ch_rangevio[71]
416     _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 = 371, //!< pass[0].tr_sar_gen_out[0]
417     _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 = 372, //!< pass[0].tr_sar_gen_out[1]
418     _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 = 373, //!< pass[0].tr_sar_gen_out[2]
419     _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 = 374, //!< pass[0].tr_sar_gen_out[3]
420     _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 = 375, //!< pass[0].tr_sar_gen_out[4]
421     _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 = 376, //!< pass[0].tr_sar_gen_out[5]
422     _CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 377, //!< peri.tr_io_input[0]
423     _CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 378, //!< peri.tr_io_input[1]
424     _CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 379, //!< peri.tr_io_input[2]
425     _CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 380, //!< peri.tr_io_input[3]
426     _CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 381, //!< peri.tr_io_input[4]
427     _CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 382, //!< peri.tr_io_input[5]
428     _CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 383, //!< peri.tr_io_input[6]
429     _CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 384, //!< peri.tr_io_input[7]
430     _CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 385, //!< peri.tr_io_input[8]
431     _CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 386, //!< peri.tr_io_input[9]
432     _CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 387, //!< peri.tr_io_input[10]
433     _CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 388, //!< peri.tr_io_input[11]
434     _CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 389, //!< peri.tr_io_input[12]
435     _CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 390, //!< peri.tr_io_input[13]
436     _CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 391, //!< peri.tr_io_input[14]
437     _CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 392, //!< peri.tr_io_input[15]
438     _CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 393, //!< peri.tr_io_input[16]
439     _CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 394, //!< peri.tr_io_input[17]
440     _CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 395, //!< peri.tr_io_input[18]
441     _CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 396, //!< peri.tr_io_input[19]
442     _CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 397, //!< peri.tr_io_input[20]
443     _CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 398, //!< peri.tr_io_input[21]
444     _CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 399, //!< peri.tr_io_input[22]
445     _CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 400, //!< peri.tr_io_input[23]
446     _CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 401, //!< peri.tr_io_input[24]
447     _CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 402, //!< peri.tr_io_input[25]
448     _CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 403, //!< peri.tr_io_input[26]
449     _CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 404, //!< peri.tr_io_input[27]
450     _CYHAL_TRIGGER_PERI_TR_IO_INPUT28 = 405, //!< peri.tr_io_input[28]
451     _CYHAL_TRIGGER_PERI_TR_IO_INPUT29 = 406, //!< peri.tr_io_input[29]
452     _CYHAL_TRIGGER_PERI_TR_IO_INPUT30 = 407, //!< peri.tr_io_input[30]
453     _CYHAL_TRIGGER_PERI_TR_IO_INPUT31 = 408, //!< peri.tr_io_input[31]
454     _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 409, //!< scb[0].tr_i2c_scl_filtered
455     _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 410, //!< scb[1].tr_i2c_scl_filtered
456     _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 411, //!< scb[2].tr_i2c_scl_filtered
457     _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 412, //!< scb[3].tr_i2c_scl_filtered
458     _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 413, //!< scb[4].tr_i2c_scl_filtered
459     _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 414, //!< scb[5].tr_i2c_scl_filtered
460     _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 415, //!< scb[6].tr_i2c_scl_filtered
461     _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 416, //!< scb[7].tr_i2c_scl_filtered
462     _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 417, //!< scb[8].tr_i2c_scl_filtered
463     _CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = 418, //!< scb[9].tr_i2c_scl_filtered
464     _CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = 419, //!< scb[10].tr_i2c_scl_filtered
465     _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 420, //!< scb[0].tr_rx_req
466     _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 421, //!< scb[1].tr_rx_req
467     _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 422, //!< scb[2].tr_rx_req
468     _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 423, //!< scb[3].tr_rx_req
469     _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 424, //!< scb[4].tr_rx_req
470     _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 425, //!< scb[5].tr_rx_req
471     _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 426, //!< scb[6].tr_rx_req
472     _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 427, //!< scb[7].tr_rx_req
473     _CYHAL_TRIGGER_SCB8_TR_RX_REQ = 428, //!< scb[8].tr_rx_req
474     _CYHAL_TRIGGER_SCB9_TR_RX_REQ = 429, //!< scb[9].tr_rx_req
475     _CYHAL_TRIGGER_SCB10_TR_RX_REQ = 430, //!< scb[10].tr_rx_req
476     _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 431, //!< scb[0].tr_tx_req
477     _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 432, //!< scb[1].tr_tx_req
478     _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 433, //!< scb[2].tr_tx_req
479     _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 434, //!< scb[3].tr_tx_req
480     _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 435, //!< scb[4].tr_tx_req
481     _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 436, //!< scb[5].tr_tx_req
482     _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 437, //!< scb[6].tr_tx_req
483     _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 438, //!< scb[7].tr_tx_req
484     _CYHAL_TRIGGER_SCB8_TR_TX_REQ = 439, //!< scb[8].tr_tx_req
485     _CYHAL_TRIGGER_SCB9_TR_TX_REQ = 440, //!< scb[9].tr_tx_req
486     _CYHAL_TRIGGER_SCB10_TR_TX_REQ = 441, //!< scb[10].tr_tx_req
487     _CYHAL_TRIGGER_SMIF0_TR_RX_REQ = 442, //!< smif[0].tr_rx_req
488     _CYHAL_TRIGGER_SMIF0_TR_TX_REQ = 443, //!< smif[0].tr_tx_req
489     _CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 444, //!< tcpwm[0].tr_out0[0]
490     _CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 445, //!< tcpwm[0].tr_out0[1]
491     _CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 446, //!< tcpwm[0].tr_out0[2]
492     _CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 447, //!< tcpwm[0].tr_out0[3]
493     _CYHAL_TRIGGER_TCPWM0_TR_OUT04 = 448, //!< tcpwm[0].tr_out0[4]
494     _CYHAL_TRIGGER_TCPWM0_TR_OUT05 = 449, //!< tcpwm[0].tr_out0[5]
495     _CYHAL_TRIGGER_TCPWM0_TR_OUT06 = 450, //!< tcpwm[0].tr_out0[6]
496     _CYHAL_TRIGGER_TCPWM0_TR_OUT07 = 451, //!< tcpwm[0].tr_out0[7]
497     _CYHAL_TRIGGER_TCPWM0_TR_OUT08 = 452, //!< tcpwm[0].tr_out0[8]
498     _CYHAL_TRIGGER_TCPWM0_TR_OUT09 = 453, //!< tcpwm[0].tr_out0[9]
499     _CYHAL_TRIGGER_TCPWM0_TR_OUT010 = 454, //!< tcpwm[0].tr_out0[10]
500     _CYHAL_TRIGGER_TCPWM0_TR_OUT011 = 455, //!< tcpwm[0].tr_out0[11]
501     _CYHAL_TRIGGER_TCPWM0_TR_OUT012 = 456, //!< tcpwm[0].tr_out0[12]
502     _CYHAL_TRIGGER_TCPWM0_TR_OUT013 = 457, //!< tcpwm[0].tr_out0[13]
503     _CYHAL_TRIGGER_TCPWM0_TR_OUT014 = 458, //!< tcpwm[0].tr_out0[14]
504     _CYHAL_TRIGGER_TCPWM0_TR_OUT015 = 459, //!< tcpwm[0].tr_out0[15]
505     _CYHAL_TRIGGER_TCPWM0_TR_OUT016 = 460, //!< tcpwm[0].tr_out0[16]
506     _CYHAL_TRIGGER_TCPWM0_TR_OUT017 = 461, //!< tcpwm[0].tr_out0[17]
507     _CYHAL_TRIGGER_TCPWM0_TR_OUT018 = 462, //!< tcpwm[0].tr_out0[18]
508     _CYHAL_TRIGGER_TCPWM0_TR_OUT019 = 463, //!< tcpwm[0].tr_out0[19]
509     _CYHAL_TRIGGER_TCPWM0_TR_OUT020 = 464, //!< tcpwm[0].tr_out0[20]
510     _CYHAL_TRIGGER_TCPWM0_TR_OUT021 = 465, //!< tcpwm[0].tr_out0[21]
511     _CYHAL_TRIGGER_TCPWM0_TR_OUT022 = 466, //!< tcpwm[0].tr_out0[22]
512     _CYHAL_TRIGGER_TCPWM0_TR_OUT023 = 467, //!< tcpwm[0].tr_out0[23]
513     _CYHAL_TRIGGER_TCPWM0_TR_OUT024 = 468, //!< tcpwm[0].tr_out0[24]
514     _CYHAL_TRIGGER_TCPWM0_TR_OUT025 = 469, //!< tcpwm[0].tr_out0[25]
515     _CYHAL_TRIGGER_TCPWM0_TR_OUT026 = 470, //!< tcpwm[0].tr_out0[26]
516     _CYHAL_TRIGGER_TCPWM0_TR_OUT027 = 471, //!< tcpwm[0].tr_out0[27]
517     _CYHAL_TRIGGER_TCPWM0_TR_OUT028 = 472, //!< tcpwm[0].tr_out0[28]
518     _CYHAL_TRIGGER_TCPWM0_TR_OUT029 = 473, //!< tcpwm[0].tr_out0[29]
519     _CYHAL_TRIGGER_TCPWM0_TR_OUT030 = 474, //!< tcpwm[0].tr_out0[30]
520     _CYHAL_TRIGGER_TCPWM0_TR_OUT031 = 475, //!< tcpwm[0].tr_out0[31]
521     _CYHAL_TRIGGER_TCPWM0_TR_OUT032 = 476, //!< tcpwm[0].tr_out0[32]
522     _CYHAL_TRIGGER_TCPWM0_TR_OUT033 = 477, //!< tcpwm[0].tr_out0[33]
523     _CYHAL_TRIGGER_TCPWM0_TR_OUT034 = 478, //!< tcpwm[0].tr_out0[34]
524     _CYHAL_TRIGGER_TCPWM0_TR_OUT035 = 479, //!< tcpwm[0].tr_out0[35]
525     _CYHAL_TRIGGER_TCPWM0_TR_OUT036 = 480, //!< tcpwm[0].tr_out0[36]
526     _CYHAL_TRIGGER_TCPWM0_TR_OUT037 = 481, //!< tcpwm[0].tr_out0[37]
527     _CYHAL_TRIGGER_TCPWM0_TR_OUT038 = 482, //!< tcpwm[0].tr_out0[38]
528     _CYHAL_TRIGGER_TCPWM0_TR_OUT039 = 483, //!< tcpwm[0].tr_out0[39]
529     _CYHAL_TRIGGER_TCPWM0_TR_OUT040 = 484, //!< tcpwm[0].tr_out0[40]
530     _CYHAL_TRIGGER_TCPWM0_TR_OUT041 = 485, //!< tcpwm[0].tr_out0[41]
531     _CYHAL_TRIGGER_TCPWM0_TR_OUT042 = 486, //!< tcpwm[0].tr_out0[42]
532     _CYHAL_TRIGGER_TCPWM0_TR_OUT043 = 487, //!< tcpwm[0].tr_out0[43]
533     _CYHAL_TRIGGER_TCPWM0_TR_OUT044 = 488, //!< tcpwm[0].tr_out0[44]
534     _CYHAL_TRIGGER_TCPWM0_TR_OUT045 = 489, //!< tcpwm[0].tr_out0[45]
535     _CYHAL_TRIGGER_TCPWM0_TR_OUT046 = 490, //!< tcpwm[0].tr_out0[46]
536     _CYHAL_TRIGGER_TCPWM0_TR_OUT047 = 491, //!< tcpwm[0].tr_out0[47]
537     _CYHAL_TRIGGER_TCPWM0_TR_OUT048 = 492, //!< tcpwm[0].tr_out0[48]
538     _CYHAL_TRIGGER_TCPWM0_TR_OUT049 = 493, //!< tcpwm[0].tr_out0[49]
539     _CYHAL_TRIGGER_TCPWM0_TR_OUT050 = 494, //!< tcpwm[0].tr_out0[50]
540     _CYHAL_TRIGGER_TCPWM0_TR_OUT051 = 495, //!< tcpwm[0].tr_out0[51]
541     _CYHAL_TRIGGER_TCPWM0_TR_OUT052 = 496, //!< tcpwm[0].tr_out0[52]
542     _CYHAL_TRIGGER_TCPWM0_TR_OUT053 = 497, //!< tcpwm[0].tr_out0[53]
543     _CYHAL_TRIGGER_TCPWM0_TR_OUT054 = 498, //!< tcpwm[0].tr_out0[54]
544     _CYHAL_TRIGGER_TCPWM0_TR_OUT055 = 499, //!< tcpwm[0].tr_out0[55]
545     _CYHAL_TRIGGER_TCPWM0_TR_OUT056 = 500, //!< tcpwm[0].tr_out0[56]
546     _CYHAL_TRIGGER_TCPWM0_TR_OUT057 = 501, //!< tcpwm[0].tr_out0[57]
547     _CYHAL_TRIGGER_TCPWM0_TR_OUT058 = 502, //!< tcpwm[0].tr_out0[58]
548     _CYHAL_TRIGGER_TCPWM0_TR_OUT059 = 503, //!< tcpwm[0].tr_out0[59]
549     _CYHAL_TRIGGER_TCPWM0_TR_OUT060 = 504, //!< tcpwm[0].tr_out0[60]
550     _CYHAL_TRIGGER_TCPWM0_TR_OUT061 = 505, //!< tcpwm[0].tr_out0[61]
551     _CYHAL_TRIGGER_TCPWM0_TR_OUT062 = 506, //!< tcpwm[0].tr_out0[62]
552     _CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 507, //!< tcpwm[0].tr_out0[256]
553     _CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 508, //!< tcpwm[0].tr_out0[257]
554     _CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 509, //!< tcpwm[0].tr_out0[258]
555     _CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 510, //!< tcpwm[0].tr_out0[259]
556     _CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 511, //!< tcpwm[0].tr_out0[260]
557     _CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 512, //!< tcpwm[0].tr_out0[261]
558     _CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 513, //!< tcpwm[0].tr_out0[262]
559     _CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 514, //!< tcpwm[0].tr_out0[263]
560     _CYHAL_TRIGGER_TCPWM0_TR_OUT0264 = 515, //!< tcpwm[0].tr_out0[264]
561     _CYHAL_TRIGGER_TCPWM0_TR_OUT0265 = 516, //!< tcpwm[0].tr_out0[265]
562     _CYHAL_TRIGGER_TCPWM0_TR_OUT0266 = 517, //!< tcpwm[0].tr_out0[266]
563     _CYHAL_TRIGGER_TCPWM0_TR_OUT0267 = 518, //!< tcpwm[0].tr_out0[267]
564     _CYHAL_TRIGGER_TCPWM0_TR_OUT0512 = 519, //!< tcpwm[0].tr_out0[512]
565     _CYHAL_TRIGGER_TCPWM0_TR_OUT0513 = 520, //!< tcpwm[0].tr_out0[513]
566     _CYHAL_TRIGGER_TCPWM0_TR_OUT0514 = 521, //!< tcpwm[0].tr_out0[514]
567     _CYHAL_TRIGGER_TCPWM0_TR_OUT0515 = 522, //!< tcpwm[0].tr_out0[515]
568     _CYHAL_TRIGGER_TCPWM0_TR_OUT0516 = 523, //!< tcpwm[0].tr_out0[516]
569     _CYHAL_TRIGGER_TCPWM0_TR_OUT0517 = 524, //!< tcpwm[0].tr_out0[517]
570     _CYHAL_TRIGGER_TCPWM0_TR_OUT0518 = 525, //!< tcpwm[0].tr_out0[518]
571     _CYHAL_TRIGGER_TCPWM0_TR_OUT0519 = 526, //!< tcpwm[0].tr_out0[519]
572     _CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 527, //!< tcpwm[0].tr_out1[0]
573     _CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 528, //!< tcpwm[0].tr_out1[1]
574     _CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 529, //!< tcpwm[0].tr_out1[2]
575     _CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 530, //!< tcpwm[0].tr_out1[3]
576     _CYHAL_TRIGGER_TCPWM0_TR_OUT14 = 531, //!< tcpwm[0].tr_out1[4]
577     _CYHAL_TRIGGER_TCPWM0_TR_OUT15 = 532, //!< tcpwm[0].tr_out1[5]
578     _CYHAL_TRIGGER_TCPWM0_TR_OUT16 = 533, //!< tcpwm[0].tr_out1[6]
579     _CYHAL_TRIGGER_TCPWM0_TR_OUT17 = 534, //!< tcpwm[0].tr_out1[7]
580     _CYHAL_TRIGGER_TCPWM0_TR_OUT18 = 535, //!< tcpwm[0].tr_out1[8]
581     _CYHAL_TRIGGER_TCPWM0_TR_OUT19 = 536, //!< tcpwm[0].tr_out1[9]
582     _CYHAL_TRIGGER_TCPWM0_TR_OUT110 = 537, //!< tcpwm[0].tr_out1[10]
583     _CYHAL_TRIGGER_TCPWM0_TR_OUT111 = 538, //!< tcpwm[0].tr_out1[11]
584     _CYHAL_TRIGGER_TCPWM0_TR_OUT112 = 539, //!< tcpwm[0].tr_out1[12]
585     _CYHAL_TRIGGER_TCPWM0_TR_OUT113 = 540, //!< tcpwm[0].tr_out1[13]
586     _CYHAL_TRIGGER_TCPWM0_TR_OUT114 = 541, //!< tcpwm[0].tr_out1[14]
587     _CYHAL_TRIGGER_TCPWM0_TR_OUT115 = 542, //!< tcpwm[0].tr_out1[15]
588     _CYHAL_TRIGGER_TCPWM0_TR_OUT116 = 543, //!< tcpwm[0].tr_out1[16]
589     _CYHAL_TRIGGER_TCPWM0_TR_OUT117 = 544, //!< tcpwm[0].tr_out1[17]
590     _CYHAL_TRIGGER_TCPWM0_TR_OUT118 = 545, //!< tcpwm[0].tr_out1[18]
591     _CYHAL_TRIGGER_TCPWM0_TR_OUT119 = 546, //!< tcpwm[0].tr_out1[19]
592     _CYHAL_TRIGGER_TCPWM0_TR_OUT120 = 547, //!< tcpwm[0].tr_out1[20]
593     _CYHAL_TRIGGER_TCPWM0_TR_OUT121 = 548, //!< tcpwm[0].tr_out1[21]
594     _CYHAL_TRIGGER_TCPWM0_TR_OUT122 = 549, //!< tcpwm[0].tr_out1[22]
595     _CYHAL_TRIGGER_TCPWM0_TR_OUT123 = 550, //!< tcpwm[0].tr_out1[23]
596     _CYHAL_TRIGGER_TCPWM0_TR_OUT124 = 551, //!< tcpwm[0].tr_out1[24]
597     _CYHAL_TRIGGER_TCPWM0_TR_OUT125 = 552, //!< tcpwm[0].tr_out1[25]
598     _CYHAL_TRIGGER_TCPWM0_TR_OUT126 = 553, //!< tcpwm[0].tr_out1[26]
599     _CYHAL_TRIGGER_TCPWM0_TR_OUT127 = 554, //!< tcpwm[0].tr_out1[27]
600     _CYHAL_TRIGGER_TCPWM0_TR_OUT128 = 555, //!< tcpwm[0].tr_out1[28]
601     _CYHAL_TRIGGER_TCPWM0_TR_OUT129 = 556, //!< tcpwm[0].tr_out1[29]
602     _CYHAL_TRIGGER_TCPWM0_TR_OUT130 = 557, //!< tcpwm[0].tr_out1[30]
603     _CYHAL_TRIGGER_TCPWM0_TR_OUT131 = 558, //!< tcpwm[0].tr_out1[31]
604     _CYHAL_TRIGGER_TCPWM0_TR_OUT132 = 559, //!< tcpwm[0].tr_out1[32]
605     _CYHAL_TRIGGER_TCPWM0_TR_OUT133 = 560, //!< tcpwm[0].tr_out1[33]
606     _CYHAL_TRIGGER_TCPWM0_TR_OUT134 = 561, //!< tcpwm[0].tr_out1[34]
607     _CYHAL_TRIGGER_TCPWM0_TR_OUT135 = 562, //!< tcpwm[0].tr_out1[35]
608     _CYHAL_TRIGGER_TCPWM0_TR_OUT136 = 563, //!< tcpwm[0].tr_out1[36]
609     _CYHAL_TRIGGER_TCPWM0_TR_OUT137 = 564, //!< tcpwm[0].tr_out1[37]
610     _CYHAL_TRIGGER_TCPWM0_TR_OUT138 = 565, //!< tcpwm[0].tr_out1[38]
611     _CYHAL_TRIGGER_TCPWM0_TR_OUT139 = 566, //!< tcpwm[0].tr_out1[39]
612     _CYHAL_TRIGGER_TCPWM0_TR_OUT140 = 567, //!< tcpwm[0].tr_out1[40]
613     _CYHAL_TRIGGER_TCPWM0_TR_OUT141 = 568, //!< tcpwm[0].tr_out1[41]
614     _CYHAL_TRIGGER_TCPWM0_TR_OUT142 = 569, //!< tcpwm[0].tr_out1[42]
615     _CYHAL_TRIGGER_TCPWM0_TR_OUT143 = 570, //!< tcpwm[0].tr_out1[43]
616     _CYHAL_TRIGGER_TCPWM0_TR_OUT144 = 571, //!< tcpwm[0].tr_out1[44]
617     _CYHAL_TRIGGER_TCPWM0_TR_OUT145 = 572, //!< tcpwm[0].tr_out1[45]
618     _CYHAL_TRIGGER_TCPWM0_TR_OUT146 = 573, //!< tcpwm[0].tr_out1[46]
619     _CYHAL_TRIGGER_TCPWM0_TR_OUT147 = 574, //!< tcpwm[0].tr_out1[47]
620     _CYHAL_TRIGGER_TCPWM0_TR_OUT148 = 575, //!< tcpwm[0].tr_out1[48]
621     _CYHAL_TRIGGER_TCPWM0_TR_OUT149 = 576, //!< tcpwm[0].tr_out1[49]
622     _CYHAL_TRIGGER_TCPWM0_TR_OUT150 = 577, //!< tcpwm[0].tr_out1[50]
623     _CYHAL_TRIGGER_TCPWM0_TR_OUT151 = 578, //!< tcpwm[0].tr_out1[51]
624     _CYHAL_TRIGGER_TCPWM0_TR_OUT152 = 579, //!< tcpwm[0].tr_out1[52]
625     _CYHAL_TRIGGER_TCPWM0_TR_OUT153 = 580, //!< tcpwm[0].tr_out1[53]
626     _CYHAL_TRIGGER_TCPWM0_TR_OUT154 = 581, //!< tcpwm[0].tr_out1[54]
627     _CYHAL_TRIGGER_TCPWM0_TR_OUT155 = 582, //!< tcpwm[0].tr_out1[55]
628     _CYHAL_TRIGGER_TCPWM0_TR_OUT156 = 583, //!< tcpwm[0].tr_out1[56]
629     _CYHAL_TRIGGER_TCPWM0_TR_OUT157 = 584, //!< tcpwm[0].tr_out1[57]
630     _CYHAL_TRIGGER_TCPWM0_TR_OUT158 = 585, //!< tcpwm[0].tr_out1[58]
631     _CYHAL_TRIGGER_TCPWM0_TR_OUT159 = 586, //!< tcpwm[0].tr_out1[59]
632     _CYHAL_TRIGGER_TCPWM0_TR_OUT160 = 587, //!< tcpwm[0].tr_out1[60]
633     _CYHAL_TRIGGER_TCPWM0_TR_OUT161 = 588, //!< tcpwm[0].tr_out1[61]
634     _CYHAL_TRIGGER_TCPWM0_TR_OUT162 = 589, //!< tcpwm[0].tr_out1[62]
635     _CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 590, //!< tcpwm[0].tr_out1[256]
636     _CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 591, //!< tcpwm[0].tr_out1[257]
637     _CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 592, //!< tcpwm[0].tr_out1[258]
638     _CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 593, //!< tcpwm[0].tr_out1[259]
639     _CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 594, //!< tcpwm[0].tr_out1[260]
640     _CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 595, //!< tcpwm[0].tr_out1[261]
641     _CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 596, //!< tcpwm[0].tr_out1[262]
642     _CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 597, //!< tcpwm[0].tr_out1[263]
643     _CYHAL_TRIGGER_TCPWM0_TR_OUT1264 = 598, //!< tcpwm[0].tr_out1[264]
644     _CYHAL_TRIGGER_TCPWM0_TR_OUT1265 = 599, //!< tcpwm[0].tr_out1[265]
645     _CYHAL_TRIGGER_TCPWM0_TR_OUT1266 = 600, //!< tcpwm[0].tr_out1[266]
646     _CYHAL_TRIGGER_TCPWM0_TR_OUT1267 = 601, //!< tcpwm[0].tr_out1[267]
647     _CYHAL_TRIGGER_TCPWM0_TR_OUT1512 = 602, //!< tcpwm[0].tr_out1[512]
648     _CYHAL_TRIGGER_TCPWM0_TR_OUT1513 = 603, //!< tcpwm[0].tr_out1[513]
649     _CYHAL_TRIGGER_TCPWM0_TR_OUT1514 = 604, //!< tcpwm[0].tr_out1[514]
650     _CYHAL_TRIGGER_TCPWM0_TR_OUT1515 = 605, //!< tcpwm[0].tr_out1[515]
651     _CYHAL_TRIGGER_TCPWM0_TR_OUT1516 = 606, //!< tcpwm[0].tr_out1[516]
652     _CYHAL_TRIGGER_TCPWM0_TR_OUT1517 = 607, //!< tcpwm[0].tr_out1[517]
653     _CYHAL_TRIGGER_TCPWM0_TR_OUT1518 = 608, //!< tcpwm[0].tr_out1[518]
654     _CYHAL_TRIGGER_TCPWM0_TR_OUT1519 = 609, //!< tcpwm[0].tr_out1[519]
655     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 = 610, //!< tr_group[10].output[0]
656     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 = 611, //!< tr_group[10].output[1]
657     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 = 612, //!< tr_group[10].output[2]
658     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 = 613, //!< tr_group[10].output[3]
659     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 = 614, //!< tr_group[10].output[4]
660     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT0 = 615, //!< tr_group[11].output[0]
661     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT1 = 616, //!< tr_group[11].output[1]
662     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT2 = 617, //!< tr_group[11].output[2]
663     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT3 = 618, //!< tr_group[11].output[3]
664     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT4 = 619, //!< tr_group[11].output[4]
665     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT0 = 620, //!< tr_group[12].output[0]
666     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT1 = 621, //!< tr_group[12].output[1]
667     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT2 = 622, //!< tr_group[12].output[2]
668     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT3 = 623, //!< tr_group[12].output[3]
669     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT4 = 624, //!< tr_group[12].output[4]
670 } _cyhal_trigger_source_xmc7100_t;
671 
672 /** Typedef for internal device family specific trigger source to generic trigger source */
673 typedef _cyhal_trigger_source_xmc7100_t cyhal_internal_source_t;
674 
675 /** @brief Get a public source signal type (cyhal_trigger_source_xmc7100_t) given an internal source signal and signal type */
676 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type)    ((src) << 1 | (type))
677 /** @brief Get an internal source signal (_cyhal_trigger_source_xmc7100_t) given a public source signal. */
678 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src)      ((cyhal_internal_source_t)((src) >> 1))
679 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */
680 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src)        ((cyhal_signal_type_t)((src) & 1))
681 /** \endcond */
682 
683 /** @brief Name of each input trigger. */
684 typedef enum
685 {
686     CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero
687     CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero
688     CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_i2s_rx_req
689     CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[1].tr_i2s_rx_req
690     CYHAL_TRIGGER_AUDIOSS2_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS2_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[2].tr_i2s_rx_req
691     CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_i2s_tx_req
692     CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[1].tr_i2s_tx_req
693     CYHAL_TRIGGER_AUDIOSS2_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS2_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[2].tr_i2s_tx_req
694     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[0]
695     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[1]
696     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[2]
697     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[3]
698     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[0]
699     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[1]
700     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[2]
701     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[3]
702     CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[0]
703     CYHAL_TRIGGER_CANFD0_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[1]
704     CYHAL_TRIGGER_CANFD0_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[2]
705     CYHAL_TRIGGER_CANFD0_TR_FIFO03 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO03, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[3]
706     CYHAL_TRIGGER_CANFD1_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[0]
707     CYHAL_TRIGGER_CANFD1_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[1]
708     CYHAL_TRIGGER_CANFD1_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[2]
709     CYHAL_TRIGGER_CANFD1_TR_FIFO03 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO03, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[3]
710     CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[0]
711     CYHAL_TRIGGER_CANFD0_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[1]
712     CYHAL_TRIGGER_CANFD0_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[2]
713     CYHAL_TRIGGER_CANFD0_TR_FIFO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO13, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[3]
714     CYHAL_TRIGGER_CANFD1_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[0]
715     CYHAL_TRIGGER_CANFD1_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[1]
716     CYHAL_TRIGGER_CANFD1_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[2]
717     CYHAL_TRIGGER_CANFD1_TR_FIFO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO13, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[3]
718     CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[0]
719     CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[1]
720     CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[2]
721     CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[3]
722     CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[0]
723     CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[1]
724     CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[2]
725     CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[3]
726     CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[0]
727     CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[1]
728     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[0]
729     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[1]
730     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[2]
731     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[3]
732     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[4]
733     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[5]
734     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[6]
735     CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[7]
736     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0]
737     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1]
738     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2]
739     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3]
740     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4]
741     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5]
742     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6]
743     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7]
744     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8]
745     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9]
746     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10]
747     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11]
748     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12]
749     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13]
750     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14]
751     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15]
752     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[16]
753     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[17]
754     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[18]
755     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[19]
756     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[20]
757     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[21]
758     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[22]
759     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[23]
760     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[24]
761     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[25]
762     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[26]
763     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[27]
764     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[28]
765     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[29]
766     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[30]
767     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[31]
768     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[32]
769     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[33]
770     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[34]
771     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[35]
772     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[36]
773     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[37]
774     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[38]
775     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[39]
776     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[40]
777     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[41]
778     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[42]
779     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[43]
780     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[44]
781     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[45]
782     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[46]
783     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[47]
784     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[48]
785     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[49]
786     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[50]
787     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[51]
788     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[52]
789     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[53]
790     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[54]
791     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[55]
792     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[56]
793     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[57]
794     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[58]
795     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[59]
796     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[60]
797     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[61]
798     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[62]
799     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[63]
800     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[64]
801     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[65]
802     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[66]
803     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[67]
804     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[68]
805     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[69]
806     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[70]
807     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[71]
808     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[72]
809     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[73]
810     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[74]
811     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[75]
812     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[76]
813     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[77]
814     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[78]
815     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[79]
816     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[80]
817     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[81]
818     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[82]
819     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[83]
820     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[84]
821     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[85]
822     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[86]
823     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[87]
824     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[88]
825     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[89]
826     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[90]
827     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[91]
828     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT92 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT92, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[92]
829     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT93 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT93, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[93]
830     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT94 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT94, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[94]
831     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT95 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT95, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[95]
832     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT96 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT96, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[96]
833     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT97 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT97, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[97]
834     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT98 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT98, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[98]
835     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT99 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT99, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[99]
836     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0]
837     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1]
838     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2]
839     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3]
840     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4]
841     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5]
842     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6]
843     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7]
844     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8]
845     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9]
846     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10]
847     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11]
848     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12]
849     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13]
850     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14]
851     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15]
852     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[16]
853     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[17]
854     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[18]
855     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[19]
856     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[20]
857     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[21]
858     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[22]
859     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[23]
860     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[24]
861     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[25]
862     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[26]
863     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[27]
864     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[28]
865     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[29]
866     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[30]
867     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[31]
868     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[32]
869     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[33]
870     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[34]
871     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[35]
872     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[36]
873     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[37]
874     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[38]
875     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[39]
876     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[40]
877     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[41]
878     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[42]
879     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[43]
880     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[44]
881     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[45]
882     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[46]
883     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[47]
884     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT48, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[48]
885     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT49, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[49]
886     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT50, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[50]
887     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT51, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[51]
888     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT52, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[52]
889     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT53, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[53]
890     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT54, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[54]
891     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT55, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[55]
892     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT56, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[56]
893     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT57, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[57]
894     CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0]
895     CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[1]
896     CYHAL_TRIGGER_CPUSS_TR_FAULT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[2]
897     CYHAL_TRIGGER_CPUSS_TR_FAULT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[3]
898     CYHAL_TRIGGER_EVTGEN0_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[0]
899     CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[0]
900     CYHAL_TRIGGER_EVTGEN0_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[1]
901     CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[1]
902     CYHAL_TRIGGER_EVTGEN0_TR_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[2]
903     CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[2]
904     CYHAL_TRIGGER_EVTGEN0_TR_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[3]
905     CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[3]
906     CYHAL_TRIGGER_EVTGEN0_TR_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[4]
907     CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[4]
908     CYHAL_TRIGGER_EVTGEN0_TR_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[5]
909     CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[5]
910     CYHAL_TRIGGER_EVTGEN0_TR_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[6]
911     CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[6]
912     CYHAL_TRIGGER_EVTGEN0_TR_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[7]
913     CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[7]
914     CYHAL_TRIGGER_EVTGEN0_TR_OUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[8]
915     CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[8]
916     CYHAL_TRIGGER_EVTGEN0_TR_OUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[9]
917     CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[9]
918     CYHAL_TRIGGER_EVTGEN0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[10]
919     CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[10]
920     CYHAL_TRIGGER_EVTGEN0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[11]
921     CYHAL_TRIGGER_EVTGEN0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[11]
922     CYHAL_TRIGGER_EVTGEN0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[12]
923     CYHAL_TRIGGER_EVTGEN0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[12]
924     CYHAL_TRIGGER_EVTGEN0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[13]
925     CYHAL_TRIGGER_EVTGEN0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[13]
926     CYHAL_TRIGGER_EVTGEN0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[14]
927     CYHAL_TRIGGER_EVTGEN0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[14]
928     CYHAL_TRIGGER_EVTGEN0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[15]
929     CYHAL_TRIGGER_EVTGEN0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[15]
930     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[0]
931     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[0]
932     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[1]
933     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[1]
934     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[2]
935     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[2]
936     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[3]
937     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[3]
938     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[4]
939     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[4]
940     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[5]
941     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[5]
942     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[6]
943     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[6]
944     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[7]
945     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[7]
946     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[8]
947     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[8]
948     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[9]
949     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[9]
950     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[10]
951     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[10]
952     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[11]
953     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[11]
954     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[12]
955     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[12]
956     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[13]
957     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[13]
958     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[14]
959     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[14]
960     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[15]
961     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[15]
962     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[16]
963     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[16]
964     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[17]
965     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[17]
966     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[18]
967     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[18]
968     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[19]
969     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[19]
970     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[20]
971     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[20]
972     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[21]
973     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[21]
974     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[22]
975     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[22]
976     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[23]
977     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[23]
978     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[24]
979     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[24]
980     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[25]
981     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[25]
982     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[26]
983     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[26]
984     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[27]
985     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[27]
986     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[28]
987     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[28]
988     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[29]
989     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[29]
990     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[30]
991     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[30]
992     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[31]
993     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[31]
994     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[32]
995     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[32]
996     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[33]
997     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[33]
998     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[34]
999     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[34]
1000     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[35]
1001     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[35]
1002     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[36]
1003     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[36]
1004     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[37]
1005     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[37]
1006     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[38]
1007     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[38]
1008     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[39]
1009     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[39]
1010     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[40]
1011     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[40]
1012     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[41]
1013     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[41]
1014     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[42]
1015     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[42]
1016     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[43]
1017     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[43]
1018     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[44]
1019     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[44]
1020     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[45]
1021     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[45]
1022     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[46]
1023     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[46]
1024     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[47]
1025     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[47]
1026     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[48]
1027     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[48]
1028     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[49]
1029     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[49]
1030     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[50]
1031     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[50]
1032     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[51]
1033     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[51]
1034     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[52]
1035     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[52]
1036     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[53]
1037     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[53]
1038     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[54]
1039     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[54]
1040     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[55]
1041     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[55]
1042     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[56]
1043     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[56]
1044     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[57]
1045     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[57]
1046     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[58]
1047     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[58]
1048     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[59]
1049     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[59]
1050     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[60]
1051     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[60]
1052     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[61]
1053     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[61]
1054     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[62]
1055     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[62]
1056     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[63]
1057     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[63]
1058     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[64]
1059     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[64]
1060     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[65]
1061     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[65]
1062     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[66]
1063     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[66]
1064     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[67]
1065     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[67]
1066     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[68]
1067     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[68]
1068     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[69]
1069     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[69]
1070     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[70]
1071     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[70]
1072     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[71]
1073     CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[71]
1074     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[0]
1075     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[1]
1076     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[2]
1077     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[3]
1078     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[4]
1079     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[5]
1080     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[6]
1081     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[7]
1082     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[8]
1083     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[9]
1084     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[10]
1085     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[11]
1086     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[12]
1087     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[13]
1088     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[14]
1089     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[15]
1090     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[16]
1091     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[17]
1092     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[18]
1093     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[19]
1094     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[20]
1095     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[21]
1096     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[22]
1097     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[23]
1098     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO24, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[24]
1099     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO25, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[25]
1100     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO26, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[26]
1101     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO27, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[27]
1102     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO28, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[28]
1103     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO29, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[29]
1104     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO30, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[30]
1105     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO31, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[31]
1106     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[32]
1107     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[33]
1108     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[34]
1109     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[35]
1110     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[36]
1111     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[37]
1112     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[38]
1113     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[39]
1114     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[40]
1115     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[41]
1116     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[42]
1117     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[43]
1118     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[44]
1119     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[45]
1120     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[46]
1121     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[47]
1122     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[48]
1123     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[49]
1124     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[50]
1125     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[51]
1126     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[52]
1127     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[53]
1128     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[54]
1129     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[55]
1130     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[56]
1131     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[57]
1132     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[58]
1133     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[59]
1134     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[60]
1135     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[61]
1136     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[62]
1137     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[63]
1138     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[64]
1139     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[65]
1140     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[66]
1141     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[67]
1142     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[68]
1143     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[69]
1144     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[70]
1145     CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[71]
1146     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[0]
1147     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[0]
1148     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[1]
1149     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[1]
1150     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[2]
1151     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[2]
1152     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[3]
1153     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[3]
1154     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[4]
1155     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[4]
1156     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[5]
1157     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[5]
1158     CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[0]
1159     CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[0]
1160     CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[1]
1161     CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[1]
1162     CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[2]
1163     CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[2]
1164     CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[3]
1165     CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[3]
1166     CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[4]
1167     CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[4]
1168     CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[5]
1169     CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[5]
1170     CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[6]
1171     CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[6]
1172     CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[7]
1173     CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[7]
1174     CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[8]
1175     CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[8]
1176     CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[9]
1177     CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[9]
1178     CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[10]
1179     CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[10]
1180     CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[11]
1181     CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[11]
1182     CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[12]
1183     CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[12]
1184     CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[13]
1185     CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[13]
1186     CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[14]
1187     CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[14]
1188     CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[15]
1189     CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[15]
1190     CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[16]
1191     CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[16]
1192     CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[17]
1193     CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[17]
1194     CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[18]
1195     CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[18]
1196     CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[19]
1197     CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[19]
1198     CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[20]
1199     CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[20]
1200     CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[21]
1201     CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[21]
1202     CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[22]
1203     CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[22]
1204     CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[23]
1205     CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[23]
1206     CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[24]
1207     CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[24]
1208     CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[25]
1209     CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[25]
1210     CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[26]
1211     CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[26]
1212     CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[27]
1213     CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[27]
1214     CYHAL_TRIGGER_PERI_TR_IO_INPUT28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[28]
1215     CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[28]
1216     CYHAL_TRIGGER_PERI_TR_IO_INPUT29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[29]
1217     CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[29]
1218     CYHAL_TRIGGER_PERI_TR_IO_INPUT30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[30]
1219     CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[30]
1220     CYHAL_TRIGGER_PERI_TR_IO_INPUT31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[31]
1221     CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[31]
1222     CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered
1223     CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered
1224     CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered
1225     CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered
1226     CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered
1227     CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered
1228     CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered
1229     CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered
1230     CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_i2c_scl_filtered
1231     CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_i2c_scl_filtered
1232     CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_i2c_scl_filtered
1233     CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req
1234     CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req
1235     CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req
1236     CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req
1237     CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req
1238     CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req
1239     CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req
1240     CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req
1241     CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_rx_req
1242     CYHAL_TRIGGER_SCB9_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_rx_req
1243     CYHAL_TRIGGER_SCB10_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_rx_req
1244     CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req
1245     CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req
1246     CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req
1247     CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req
1248     CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req
1249     CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req
1250     CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req
1251     CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req
1252     CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_tx_req
1253     CYHAL_TRIGGER_SCB9_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_tx_req
1254     CYHAL_TRIGGER_SCB10_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_tx_req
1255     CYHAL_TRIGGER_SMIF0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif[0].tr_rx_req
1256     CYHAL_TRIGGER_SMIF0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif[0].tr_tx_req
1257     CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0]
1258     CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0]
1259     CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1]
1260     CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1]
1261     CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2]
1262     CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2]
1263     CYHAL_TRIGGER_TCPWM0_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[3]
1264     CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[3]
1265     CYHAL_TRIGGER_TCPWM0_TR_OUT04_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[4]
1266     CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[4]
1267     CYHAL_TRIGGER_TCPWM0_TR_OUT05_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[5]
1268     CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[5]
1269     CYHAL_TRIGGER_TCPWM0_TR_OUT06_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[6]
1270     CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[6]
1271     CYHAL_TRIGGER_TCPWM0_TR_OUT07_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[7]
1272     CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[7]
1273     CYHAL_TRIGGER_TCPWM0_TR_OUT08_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT08, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[8]
1274     CYHAL_TRIGGER_TCPWM0_TR_OUT08_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT08, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[8]
1275     CYHAL_TRIGGER_TCPWM0_TR_OUT09_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT09, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[9]
1276     CYHAL_TRIGGER_TCPWM0_TR_OUT09_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT09, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[9]
1277     CYHAL_TRIGGER_TCPWM0_TR_OUT010_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT010, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[10]
1278     CYHAL_TRIGGER_TCPWM0_TR_OUT010_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT010, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[10]
1279     CYHAL_TRIGGER_TCPWM0_TR_OUT011_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT011, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[11]
1280     CYHAL_TRIGGER_TCPWM0_TR_OUT011_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT011, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[11]
1281     CYHAL_TRIGGER_TCPWM0_TR_OUT012_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT012, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[12]
1282     CYHAL_TRIGGER_TCPWM0_TR_OUT012_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT012, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[12]
1283     CYHAL_TRIGGER_TCPWM0_TR_OUT013_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT013, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[13]
1284     CYHAL_TRIGGER_TCPWM0_TR_OUT013_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT013, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[13]
1285     CYHAL_TRIGGER_TCPWM0_TR_OUT014_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT014, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[14]
1286     CYHAL_TRIGGER_TCPWM0_TR_OUT014_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT014, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[14]
1287     CYHAL_TRIGGER_TCPWM0_TR_OUT015_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT015, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[15]
1288     CYHAL_TRIGGER_TCPWM0_TR_OUT015_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT015, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[15]
1289     CYHAL_TRIGGER_TCPWM0_TR_OUT016_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT016, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[16]
1290     CYHAL_TRIGGER_TCPWM0_TR_OUT016_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT016, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[16]
1291     CYHAL_TRIGGER_TCPWM0_TR_OUT017_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT017, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[17]
1292     CYHAL_TRIGGER_TCPWM0_TR_OUT017_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT017, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[17]
1293     CYHAL_TRIGGER_TCPWM0_TR_OUT018_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT018, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[18]
1294     CYHAL_TRIGGER_TCPWM0_TR_OUT018_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT018, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[18]
1295     CYHAL_TRIGGER_TCPWM0_TR_OUT019_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT019, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[19]
1296     CYHAL_TRIGGER_TCPWM0_TR_OUT019_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT019, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[19]
1297     CYHAL_TRIGGER_TCPWM0_TR_OUT020_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT020, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[20]
1298     CYHAL_TRIGGER_TCPWM0_TR_OUT020_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT020, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[20]
1299     CYHAL_TRIGGER_TCPWM0_TR_OUT021_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT021, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[21]
1300     CYHAL_TRIGGER_TCPWM0_TR_OUT021_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT021, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[21]
1301     CYHAL_TRIGGER_TCPWM0_TR_OUT022_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT022, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[22]
1302     CYHAL_TRIGGER_TCPWM0_TR_OUT022_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT022, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[22]
1303     CYHAL_TRIGGER_TCPWM0_TR_OUT023_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT023, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[23]
1304     CYHAL_TRIGGER_TCPWM0_TR_OUT023_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT023, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[23]
1305     CYHAL_TRIGGER_TCPWM0_TR_OUT024_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT024, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[24]
1306     CYHAL_TRIGGER_TCPWM0_TR_OUT024_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT024, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[24]
1307     CYHAL_TRIGGER_TCPWM0_TR_OUT025_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT025, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[25]
1308     CYHAL_TRIGGER_TCPWM0_TR_OUT025_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT025, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[25]
1309     CYHAL_TRIGGER_TCPWM0_TR_OUT026_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT026, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[26]
1310     CYHAL_TRIGGER_TCPWM0_TR_OUT026_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT026, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[26]
1311     CYHAL_TRIGGER_TCPWM0_TR_OUT027_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT027, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[27]
1312     CYHAL_TRIGGER_TCPWM0_TR_OUT027_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT027, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[27]
1313     CYHAL_TRIGGER_TCPWM0_TR_OUT028_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT028, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[28]
1314     CYHAL_TRIGGER_TCPWM0_TR_OUT028_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT028, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[28]
1315     CYHAL_TRIGGER_TCPWM0_TR_OUT029_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT029, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[29]
1316     CYHAL_TRIGGER_TCPWM0_TR_OUT029_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT029, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[29]
1317     CYHAL_TRIGGER_TCPWM0_TR_OUT030_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT030, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[30]
1318     CYHAL_TRIGGER_TCPWM0_TR_OUT030_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT030, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[30]
1319     CYHAL_TRIGGER_TCPWM0_TR_OUT031_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT031, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[31]
1320     CYHAL_TRIGGER_TCPWM0_TR_OUT031_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT031, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[31]
1321     CYHAL_TRIGGER_TCPWM0_TR_OUT032_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT032, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[32]
1322     CYHAL_TRIGGER_TCPWM0_TR_OUT032_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT032, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[32]
1323     CYHAL_TRIGGER_TCPWM0_TR_OUT033_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT033, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[33]
1324     CYHAL_TRIGGER_TCPWM0_TR_OUT033_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT033, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[33]
1325     CYHAL_TRIGGER_TCPWM0_TR_OUT034_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT034, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[34]
1326     CYHAL_TRIGGER_TCPWM0_TR_OUT034_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT034, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[34]
1327     CYHAL_TRIGGER_TCPWM0_TR_OUT035_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT035, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[35]
1328     CYHAL_TRIGGER_TCPWM0_TR_OUT035_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT035, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[35]
1329     CYHAL_TRIGGER_TCPWM0_TR_OUT036_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT036, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[36]
1330     CYHAL_TRIGGER_TCPWM0_TR_OUT036_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT036, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[36]
1331     CYHAL_TRIGGER_TCPWM0_TR_OUT037_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT037, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[37]
1332     CYHAL_TRIGGER_TCPWM0_TR_OUT037_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT037, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[37]
1333     CYHAL_TRIGGER_TCPWM0_TR_OUT038_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT038, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[38]
1334     CYHAL_TRIGGER_TCPWM0_TR_OUT038_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT038, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[38]
1335     CYHAL_TRIGGER_TCPWM0_TR_OUT039_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT039, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[39]
1336     CYHAL_TRIGGER_TCPWM0_TR_OUT039_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT039, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[39]
1337     CYHAL_TRIGGER_TCPWM0_TR_OUT040_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT040, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[40]
1338     CYHAL_TRIGGER_TCPWM0_TR_OUT040_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT040, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[40]
1339     CYHAL_TRIGGER_TCPWM0_TR_OUT041_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT041, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[41]
1340     CYHAL_TRIGGER_TCPWM0_TR_OUT041_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT041, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[41]
1341     CYHAL_TRIGGER_TCPWM0_TR_OUT042_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT042, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[42]
1342     CYHAL_TRIGGER_TCPWM0_TR_OUT042_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT042, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[42]
1343     CYHAL_TRIGGER_TCPWM0_TR_OUT043_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT043, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[43]
1344     CYHAL_TRIGGER_TCPWM0_TR_OUT043_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT043, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[43]
1345     CYHAL_TRIGGER_TCPWM0_TR_OUT044_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT044, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[44]
1346     CYHAL_TRIGGER_TCPWM0_TR_OUT044_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT044, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[44]
1347     CYHAL_TRIGGER_TCPWM0_TR_OUT045_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT045, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[45]
1348     CYHAL_TRIGGER_TCPWM0_TR_OUT045_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT045, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[45]
1349     CYHAL_TRIGGER_TCPWM0_TR_OUT046_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT046, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[46]
1350     CYHAL_TRIGGER_TCPWM0_TR_OUT046_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT046, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[46]
1351     CYHAL_TRIGGER_TCPWM0_TR_OUT047_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT047, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[47]
1352     CYHAL_TRIGGER_TCPWM0_TR_OUT047_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT047, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[47]
1353     CYHAL_TRIGGER_TCPWM0_TR_OUT048_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT048, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[48]
1354     CYHAL_TRIGGER_TCPWM0_TR_OUT048_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT048, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[48]
1355     CYHAL_TRIGGER_TCPWM0_TR_OUT049_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT049, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[49]
1356     CYHAL_TRIGGER_TCPWM0_TR_OUT049_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT049, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[49]
1357     CYHAL_TRIGGER_TCPWM0_TR_OUT050_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT050, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[50]
1358     CYHAL_TRIGGER_TCPWM0_TR_OUT050_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT050, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[50]
1359     CYHAL_TRIGGER_TCPWM0_TR_OUT051_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT051, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[51]
1360     CYHAL_TRIGGER_TCPWM0_TR_OUT051_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT051, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[51]
1361     CYHAL_TRIGGER_TCPWM0_TR_OUT052_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT052, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[52]
1362     CYHAL_TRIGGER_TCPWM0_TR_OUT052_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT052, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[52]
1363     CYHAL_TRIGGER_TCPWM0_TR_OUT053_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT053, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[53]
1364     CYHAL_TRIGGER_TCPWM0_TR_OUT053_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT053, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[53]
1365     CYHAL_TRIGGER_TCPWM0_TR_OUT054_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT054, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[54]
1366     CYHAL_TRIGGER_TCPWM0_TR_OUT054_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT054, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[54]
1367     CYHAL_TRIGGER_TCPWM0_TR_OUT055_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT055, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[55]
1368     CYHAL_TRIGGER_TCPWM0_TR_OUT055_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT055, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[55]
1369     CYHAL_TRIGGER_TCPWM0_TR_OUT056_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT056, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[56]
1370     CYHAL_TRIGGER_TCPWM0_TR_OUT056_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT056, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[56]
1371     CYHAL_TRIGGER_TCPWM0_TR_OUT057_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT057, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[57]
1372     CYHAL_TRIGGER_TCPWM0_TR_OUT057_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT057, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[57]
1373     CYHAL_TRIGGER_TCPWM0_TR_OUT058_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT058, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[58]
1374     CYHAL_TRIGGER_TCPWM0_TR_OUT058_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT058, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[58]
1375     CYHAL_TRIGGER_TCPWM0_TR_OUT059_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT059, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[59]
1376     CYHAL_TRIGGER_TCPWM0_TR_OUT059_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT059, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[59]
1377     CYHAL_TRIGGER_TCPWM0_TR_OUT060_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT060, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[60]
1378     CYHAL_TRIGGER_TCPWM0_TR_OUT060_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT060, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[60]
1379     CYHAL_TRIGGER_TCPWM0_TR_OUT061_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT061, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[61]
1380     CYHAL_TRIGGER_TCPWM0_TR_OUT061_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT061, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[61]
1381     CYHAL_TRIGGER_TCPWM0_TR_OUT062_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT062, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[62]
1382     CYHAL_TRIGGER_TCPWM0_TR_OUT062_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT062, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[62]
1383     CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256]
1384     CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256]
1385     CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257]
1386     CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257]
1387     CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258]
1388     CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258]
1389     CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[259]
1390     CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[259]
1391     CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[260]
1392     CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[260]
1393     CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[261]
1394     CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[261]
1395     CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[262]
1396     CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[262]
1397     CYHAL_TRIGGER_TCPWM0_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[263]
1398     CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[263]
1399     CYHAL_TRIGGER_TCPWM0_TR_OUT0264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[264]
1400     CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[264]
1401     CYHAL_TRIGGER_TCPWM0_TR_OUT0265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[265]
1402     CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[265]
1403     CYHAL_TRIGGER_TCPWM0_TR_OUT0266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[266]
1404     CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[266]
1405     CYHAL_TRIGGER_TCPWM0_TR_OUT0267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[267]
1406     CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[267]
1407     CYHAL_TRIGGER_TCPWM0_TR_OUT0512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[512]
1408     CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[512]
1409     CYHAL_TRIGGER_TCPWM0_TR_OUT0513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[513]
1410     CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[513]
1411     CYHAL_TRIGGER_TCPWM0_TR_OUT0514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[514]
1412     CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[514]
1413     CYHAL_TRIGGER_TCPWM0_TR_OUT0515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[515]
1414     CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[515]
1415     CYHAL_TRIGGER_TCPWM0_TR_OUT0516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[516]
1416     CYHAL_TRIGGER_TCPWM0_TR_OUT0516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[516]
1417     CYHAL_TRIGGER_TCPWM0_TR_OUT0517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[517]
1418     CYHAL_TRIGGER_TCPWM0_TR_OUT0517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[517]
1419     CYHAL_TRIGGER_TCPWM0_TR_OUT0518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[518]
1420     CYHAL_TRIGGER_TCPWM0_TR_OUT0518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[518]
1421     CYHAL_TRIGGER_TCPWM0_TR_OUT0519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[519]
1422     CYHAL_TRIGGER_TCPWM0_TR_OUT0519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[519]
1423     CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0]
1424     CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0]
1425     CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1]
1426     CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1]
1427     CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2]
1428     CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2]
1429     CYHAL_TRIGGER_TCPWM0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[3]
1430     CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[3]
1431     CYHAL_TRIGGER_TCPWM0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[4]
1432     CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[4]
1433     CYHAL_TRIGGER_TCPWM0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[5]
1434     CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[5]
1435     CYHAL_TRIGGER_TCPWM0_TR_OUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[6]
1436     CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[6]
1437     CYHAL_TRIGGER_TCPWM0_TR_OUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[7]
1438     CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[7]
1439     CYHAL_TRIGGER_TCPWM0_TR_OUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[8]
1440     CYHAL_TRIGGER_TCPWM0_TR_OUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[8]
1441     CYHAL_TRIGGER_TCPWM0_TR_OUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[9]
1442     CYHAL_TRIGGER_TCPWM0_TR_OUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[9]
1443     CYHAL_TRIGGER_TCPWM0_TR_OUT110_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT110, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[10]
1444     CYHAL_TRIGGER_TCPWM0_TR_OUT110_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT110, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[10]
1445     CYHAL_TRIGGER_TCPWM0_TR_OUT111_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT111, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[11]
1446     CYHAL_TRIGGER_TCPWM0_TR_OUT111_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT111, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[11]
1447     CYHAL_TRIGGER_TCPWM0_TR_OUT112_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT112, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[12]
1448     CYHAL_TRIGGER_TCPWM0_TR_OUT112_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT112, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[12]
1449     CYHAL_TRIGGER_TCPWM0_TR_OUT113_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT113, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[13]
1450     CYHAL_TRIGGER_TCPWM0_TR_OUT113_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT113, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[13]
1451     CYHAL_TRIGGER_TCPWM0_TR_OUT114_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT114, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[14]
1452     CYHAL_TRIGGER_TCPWM0_TR_OUT114_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT114, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[14]
1453     CYHAL_TRIGGER_TCPWM0_TR_OUT115_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT115, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[15]
1454     CYHAL_TRIGGER_TCPWM0_TR_OUT115_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT115, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[15]
1455     CYHAL_TRIGGER_TCPWM0_TR_OUT116_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT116, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[16]
1456     CYHAL_TRIGGER_TCPWM0_TR_OUT116_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT116, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[16]
1457     CYHAL_TRIGGER_TCPWM0_TR_OUT117_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT117, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[17]
1458     CYHAL_TRIGGER_TCPWM0_TR_OUT117_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT117, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[17]
1459     CYHAL_TRIGGER_TCPWM0_TR_OUT118_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT118, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[18]
1460     CYHAL_TRIGGER_TCPWM0_TR_OUT118_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT118, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[18]
1461     CYHAL_TRIGGER_TCPWM0_TR_OUT119_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT119, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[19]
1462     CYHAL_TRIGGER_TCPWM0_TR_OUT119_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT119, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[19]
1463     CYHAL_TRIGGER_TCPWM0_TR_OUT120_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT120, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[20]
1464     CYHAL_TRIGGER_TCPWM0_TR_OUT120_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT120, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[20]
1465     CYHAL_TRIGGER_TCPWM0_TR_OUT121_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT121, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[21]
1466     CYHAL_TRIGGER_TCPWM0_TR_OUT121_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT121, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[21]
1467     CYHAL_TRIGGER_TCPWM0_TR_OUT122_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT122, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[22]
1468     CYHAL_TRIGGER_TCPWM0_TR_OUT122_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT122, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[22]
1469     CYHAL_TRIGGER_TCPWM0_TR_OUT123_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT123, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[23]
1470     CYHAL_TRIGGER_TCPWM0_TR_OUT123_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT123, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[23]
1471     CYHAL_TRIGGER_TCPWM0_TR_OUT124_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT124, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[24]
1472     CYHAL_TRIGGER_TCPWM0_TR_OUT124_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT124, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[24]
1473     CYHAL_TRIGGER_TCPWM0_TR_OUT125_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT125, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[25]
1474     CYHAL_TRIGGER_TCPWM0_TR_OUT125_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT125, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[25]
1475     CYHAL_TRIGGER_TCPWM0_TR_OUT126_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT126, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[26]
1476     CYHAL_TRIGGER_TCPWM0_TR_OUT126_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT126, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[26]
1477     CYHAL_TRIGGER_TCPWM0_TR_OUT127_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT127, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[27]
1478     CYHAL_TRIGGER_TCPWM0_TR_OUT127_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT127, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[27]
1479     CYHAL_TRIGGER_TCPWM0_TR_OUT128_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT128, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[28]
1480     CYHAL_TRIGGER_TCPWM0_TR_OUT128_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT128, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[28]
1481     CYHAL_TRIGGER_TCPWM0_TR_OUT129_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT129, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[29]
1482     CYHAL_TRIGGER_TCPWM0_TR_OUT129_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT129, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[29]
1483     CYHAL_TRIGGER_TCPWM0_TR_OUT130_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT130, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[30]
1484     CYHAL_TRIGGER_TCPWM0_TR_OUT130_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT130, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[30]
1485     CYHAL_TRIGGER_TCPWM0_TR_OUT131_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT131, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[31]
1486     CYHAL_TRIGGER_TCPWM0_TR_OUT131_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT131, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[31]
1487     CYHAL_TRIGGER_TCPWM0_TR_OUT132_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT132, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[32]
1488     CYHAL_TRIGGER_TCPWM0_TR_OUT132_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT132, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[32]
1489     CYHAL_TRIGGER_TCPWM0_TR_OUT133_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT133, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[33]
1490     CYHAL_TRIGGER_TCPWM0_TR_OUT133_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT133, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[33]
1491     CYHAL_TRIGGER_TCPWM0_TR_OUT134_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT134, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[34]
1492     CYHAL_TRIGGER_TCPWM0_TR_OUT134_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT134, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[34]
1493     CYHAL_TRIGGER_TCPWM0_TR_OUT135_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT135, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[35]
1494     CYHAL_TRIGGER_TCPWM0_TR_OUT135_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT135, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[35]
1495     CYHAL_TRIGGER_TCPWM0_TR_OUT136_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT136, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[36]
1496     CYHAL_TRIGGER_TCPWM0_TR_OUT136_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT136, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[36]
1497     CYHAL_TRIGGER_TCPWM0_TR_OUT137_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT137, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[37]
1498     CYHAL_TRIGGER_TCPWM0_TR_OUT137_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT137, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[37]
1499     CYHAL_TRIGGER_TCPWM0_TR_OUT138_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT138, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[38]
1500     CYHAL_TRIGGER_TCPWM0_TR_OUT138_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT138, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[38]
1501     CYHAL_TRIGGER_TCPWM0_TR_OUT139_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT139, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[39]
1502     CYHAL_TRIGGER_TCPWM0_TR_OUT139_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT139, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[39]
1503     CYHAL_TRIGGER_TCPWM0_TR_OUT140_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT140, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[40]
1504     CYHAL_TRIGGER_TCPWM0_TR_OUT140_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT140, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[40]
1505     CYHAL_TRIGGER_TCPWM0_TR_OUT141_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT141, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[41]
1506     CYHAL_TRIGGER_TCPWM0_TR_OUT141_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT141, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[41]
1507     CYHAL_TRIGGER_TCPWM0_TR_OUT142_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT142, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[42]
1508     CYHAL_TRIGGER_TCPWM0_TR_OUT142_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT142, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[42]
1509     CYHAL_TRIGGER_TCPWM0_TR_OUT143_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT143, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[43]
1510     CYHAL_TRIGGER_TCPWM0_TR_OUT143_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT143, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[43]
1511     CYHAL_TRIGGER_TCPWM0_TR_OUT144_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT144, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[44]
1512     CYHAL_TRIGGER_TCPWM0_TR_OUT144_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT144, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[44]
1513     CYHAL_TRIGGER_TCPWM0_TR_OUT145_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT145, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[45]
1514     CYHAL_TRIGGER_TCPWM0_TR_OUT145_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT145, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[45]
1515     CYHAL_TRIGGER_TCPWM0_TR_OUT146_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT146, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[46]
1516     CYHAL_TRIGGER_TCPWM0_TR_OUT146_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT146, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[46]
1517     CYHAL_TRIGGER_TCPWM0_TR_OUT147_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT147, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[47]
1518     CYHAL_TRIGGER_TCPWM0_TR_OUT147_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT147, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[47]
1519     CYHAL_TRIGGER_TCPWM0_TR_OUT148_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT148, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[48]
1520     CYHAL_TRIGGER_TCPWM0_TR_OUT148_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT148, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[48]
1521     CYHAL_TRIGGER_TCPWM0_TR_OUT149_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT149, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[49]
1522     CYHAL_TRIGGER_TCPWM0_TR_OUT149_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT149, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[49]
1523     CYHAL_TRIGGER_TCPWM0_TR_OUT150_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT150, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[50]
1524     CYHAL_TRIGGER_TCPWM0_TR_OUT150_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT150, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[50]
1525     CYHAL_TRIGGER_TCPWM0_TR_OUT151_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT151, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[51]
1526     CYHAL_TRIGGER_TCPWM0_TR_OUT151_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT151, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[51]
1527     CYHAL_TRIGGER_TCPWM0_TR_OUT152_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT152, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[52]
1528     CYHAL_TRIGGER_TCPWM0_TR_OUT152_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT152, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[52]
1529     CYHAL_TRIGGER_TCPWM0_TR_OUT153_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT153, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[53]
1530     CYHAL_TRIGGER_TCPWM0_TR_OUT153_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT153, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[53]
1531     CYHAL_TRIGGER_TCPWM0_TR_OUT154_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT154, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[54]
1532     CYHAL_TRIGGER_TCPWM0_TR_OUT154_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT154, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[54]
1533     CYHAL_TRIGGER_TCPWM0_TR_OUT155_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT155, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[55]
1534     CYHAL_TRIGGER_TCPWM0_TR_OUT155_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT155, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[55]
1535     CYHAL_TRIGGER_TCPWM0_TR_OUT156_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT156, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[56]
1536     CYHAL_TRIGGER_TCPWM0_TR_OUT156_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT156, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[56]
1537     CYHAL_TRIGGER_TCPWM0_TR_OUT157_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT157, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[57]
1538     CYHAL_TRIGGER_TCPWM0_TR_OUT157_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT157, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[57]
1539     CYHAL_TRIGGER_TCPWM0_TR_OUT158_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT158, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[58]
1540     CYHAL_TRIGGER_TCPWM0_TR_OUT158_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT158, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[58]
1541     CYHAL_TRIGGER_TCPWM0_TR_OUT159_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT159, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[59]
1542     CYHAL_TRIGGER_TCPWM0_TR_OUT159_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT159, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[59]
1543     CYHAL_TRIGGER_TCPWM0_TR_OUT160_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT160, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[60]
1544     CYHAL_TRIGGER_TCPWM0_TR_OUT160_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT160, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[60]
1545     CYHAL_TRIGGER_TCPWM0_TR_OUT161_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT161, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[61]
1546     CYHAL_TRIGGER_TCPWM0_TR_OUT161_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT161, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[61]
1547     CYHAL_TRIGGER_TCPWM0_TR_OUT162_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT162, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[62]
1548     CYHAL_TRIGGER_TCPWM0_TR_OUT162_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT162, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[62]
1549     CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256]
1550     CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256]
1551     CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257]
1552     CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257]
1553     CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258]
1554     CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258]
1555     CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[259]
1556     CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[259]
1557     CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[260]
1558     CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[260]
1559     CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[261]
1560     CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[261]
1561     CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[262]
1562     CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[262]
1563     CYHAL_TRIGGER_TCPWM0_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[263]
1564     CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[263]
1565     CYHAL_TRIGGER_TCPWM0_TR_OUT1264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[264]
1566     CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[264]
1567     CYHAL_TRIGGER_TCPWM0_TR_OUT1265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[265]
1568     CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[265]
1569     CYHAL_TRIGGER_TCPWM0_TR_OUT1266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[266]
1570     CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[266]
1571     CYHAL_TRIGGER_TCPWM0_TR_OUT1267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[267]
1572     CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[267]
1573     CYHAL_TRIGGER_TCPWM0_TR_OUT1512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[512]
1574     CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[512]
1575     CYHAL_TRIGGER_TCPWM0_TR_OUT1513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[513]
1576     CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[513]
1577     CYHAL_TRIGGER_TCPWM0_TR_OUT1514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[514]
1578     CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[514]
1579     CYHAL_TRIGGER_TCPWM0_TR_OUT1515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[515]
1580     CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[515]
1581     CYHAL_TRIGGER_TCPWM0_TR_OUT1516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[516]
1582     CYHAL_TRIGGER_TCPWM0_TR_OUT1516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[516]
1583     CYHAL_TRIGGER_TCPWM0_TR_OUT1517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[517]
1584     CYHAL_TRIGGER_TCPWM0_TR_OUT1517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[517]
1585     CYHAL_TRIGGER_TCPWM0_TR_OUT1518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[518]
1586     CYHAL_TRIGGER_TCPWM0_TR_OUT1518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[518]
1587     CYHAL_TRIGGER_TCPWM0_TR_OUT1519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[519]
1588     CYHAL_TRIGGER_TCPWM0_TR_OUT1519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[519]
1589     CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[0]
1590     CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[0]
1591     CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[1]
1592     CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[1]
1593     CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[2]
1594     CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[2]
1595     CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[3]
1596     CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[3]
1597     CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[4]
1598     CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[4]
1599     CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[0]
1600     CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[0]
1601     CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[1]
1602     CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[1]
1603     CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[2]
1604     CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[2]
1605     CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[3]
1606     CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[3]
1607     CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[4]
1608     CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[4]
1609     CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[0]
1610     CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[0]
1611     CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[1]
1612     CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[1]
1613     CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[2]
1614     CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[2]
1615     CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[3]
1616     CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[3]
1617     CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[4]
1618     CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[4]
1619 } cyhal_trigger_source_xmc7100_t;
1620 
1621 /** Typedef from device family specific trigger source to generic trigger source */
1622 typedef cyhal_trigger_source_xmc7100_t cyhal_source_t;
1623 
1624 /** Deprecated defines for signals that can be either level or edge. */
1625 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1626 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT0 (CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1627 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT1 (CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1628 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT2 (CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1629 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT3 (CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1630 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT4 (CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1631 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT5 (CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1632 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT6 (CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1633 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT7 (CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1634 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT8 (CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1635 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT9 (CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1636 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT10 (CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1637 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT11 (CYHAL_TRIGGER_EVTGEN0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1638 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT12 (CYHAL_TRIGGER_EVTGEN0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1639 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT13 (CYHAL_TRIGGER_EVTGEN0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1640 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT14 (CYHAL_TRIGGER_EVTGEN0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1641 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT15 (CYHAL_TRIGGER_EVTGEN0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1642 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1643 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1644 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1645 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1646 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1647 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1648 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1649 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1650 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1651 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1652 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1653 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1654 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1655 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1656 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1657 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1658 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1659 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1660 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1661 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1662 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1663 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1664 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1665 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1666 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1667 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1668 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1669 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1670 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1671 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1672 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1673 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1674 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1675 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1676 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1677 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1678 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1679 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1680 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1681 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1682 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1683 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1684 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1685 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1686 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1687 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1688 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1689 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1690 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1691 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1692 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1693 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1694 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1695 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1696 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1697 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1698 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1699 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1700 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1701 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1702 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1703 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1704 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1705 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1706 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1707 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1708 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1709 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1710 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1711 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1712 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1713 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1714 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1715 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1716 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1717 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1718 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1719 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1720 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT0 (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1721 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT1 (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1722 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT2 (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1723 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT3 (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1724 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT4 (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1725 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT5 (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1726 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT6 (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1727 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT7 (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1728 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT8 (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1729 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT9 (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1730 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT10 (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1731 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT11 (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1732 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT12 (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1733 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT13 (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1734 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT14 (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1735 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT15 (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1736 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT16 (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1737 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT17 (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1738 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT18 (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1739 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT19 (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1740 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT20 (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1741 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT21 (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1742 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT22 (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1743 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT23 (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1744 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT24 (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1745 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT25 (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1746 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT26 (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1747 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT27 (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1748 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT28 (CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1749 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT29 (CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1750 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT30 (CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1751 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT31 (CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1752 #define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1753 #define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1754 #define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1755 #define CYHAL_TRIGGER_TCPWM0_TR_OUT03 (CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1756 #define CYHAL_TRIGGER_TCPWM0_TR_OUT04 (CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1757 #define CYHAL_TRIGGER_TCPWM0_TR_OUT05 (CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1758 #define CYHAL_TRIGGER_TCPWM0_TR_OUT06 (CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1759 #define CYHAL_TRIGGER_TCPWM0_TR_OUT07 (CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1760 #define CYHAL_TRIGGER_TCPWM0_TR_OUT08 (CYHAL_TRIGGER_TCPWM0_TR_OUT08_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1761 #define CYHAL_TRIGGER_TCPWM0_TR_OUT09 (CYHAL_TRIGGER_TCPWM0_TR_OUT09_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1762 #define CYHAL_TRIGGER_TCPWM0_TR_OUT010 (CYHAL_TRIGGER_TCPWM0_TR_OUT010_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1763 #define CYHAL_TRIGGER_TCPWM0_TR_OUT011 (CYHAL_TRIGGER_TCPWM0_TR_OUT011_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1764 #define CYHAL_TRIGGER_TCPWM0_TR_OUT012 (CYHAL_TRIGGER_TCPWM0_TR_OUT012_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1765 #define CYHAL_TRIGGER_TCPWM0_TR_OUT013 (CYHAL_TRIGGER_TCPWM0_TR_OUT013_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1766 #define CYHAL_TRIGGER_TCPWM0_TR_OUT014 (CYHAL_TRIGGER_TCPWM0_TR_OUT014_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1767 #define CYHAL_TRIGGER_TCPWM0_TR_OUT015 (CYHAL_TRIGGER_TCPWM0_TR_OUT015_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1768 #define CYHAL_TRIGGER_TCPWM0_TR_OUT016 (CYHAL_TRIGGER_TCPWM0_TR_OUT016_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1769 #define CYHAL_TRIGGER_TCPWM0_TR_OUT017 (CYHAL_TRIGGER_TCPWM0_TR_OUT017_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1770 #define CYHAL_TRIGGER_TCPWM0_TR_OUT018 (CYHAL_TRIGGER_TCPWM0_TR_OUT018_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1771 #define CYHAL_TRIGGER_TCPWM0_TR_OUT019 (CYHAL_TRIGGER_TCPWM0_TR_OUT019_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1772 #define CYHAL_TRIGGER_TCPWM0_TR_OUT020 (CYHAL_TRIGGER_TCPWM0_TR_OUT020_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1773 #define CYHAL_TRIGGER_TCPWM0_TR_OUT021 (CYHAL_TRIGGER_TCPWM0_TR_OUT021_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1774 #define CYHAL_TRIGGER_TCPWM0_TR_OUT022 (CYHAL_TRIGGER_TCPWM0_TR_OUT022_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1775 #define CYHAL_TRIGGER_TCPWM0_TR_OUT023 (CYHAL_TRIGGER_TCPWM0_TR_OUT023_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1776 #define CYHAL_TRIGGER_TCPWM0_TR_OUT024 (CYHAL_TRIGGER_TCPWM0_TR_OUT024_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1777 #define CYHAL_TRIGGER_TCPWM0_TR_OUT025 (CYHAL_TRIGGER_TCPWM0_TR_OUT025_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1778 #define CYHAL_TRIGGER_TCPWM0_TR_OUT026 (CYHAL_TRIGGER_TCPWM0_TR_OUT026_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1779 #define CYHAL_TRIGGER_TCPWM0_TR_OUT027 (CYHAL_TRIGGER_TCPWM0_TR_OUT027_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1780 #define CYHAL_TRIGGER_TCPWM0_TR_OUT028 (CYHAL_TRIGGER_TCPWM0_TR_OUT028_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1781 #define CYHAL_TRIGGER_TCPWM0_TR_OUT029 (CYHAL_TRIGGER_TCPWM0_TR_OUT029_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1782 #define CYHAL_TRIGGER_TCPWM0_TR_OUT030 (CYHAL_TRIGGER_TCPWM0_TR_OUT030_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1783 #define CYHAL_TRIGGER_TCPWM0_TR_OUT031 (CYHAL_TRIGGER_TCPWM0_TR_OUT031_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1784 #define CYHAL_TRIGGER_TCPWM0_TR_OUT032 (CYHAL_TRIGGER_TCPWM0_TR_OUT032_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1785 #define CYHAL_TRIGGER_TCPWM0_TR_OUT033 (CYHAL_TRIGGER_TCPWM0_TR_OUT033_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1786 #define CYHAL_TRIGGER_TCPWM0_TR_OUT034 (CYHAL_TRIGGER_TCPWM0_TR_OUT034_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1787 #define CYHAL_TRIGGER_TCPWM0_TR_OUT035 (CYHAL_TRIGGER_TCPWM0_TR_OUT035_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1788 #define CYHAL_TRIGGER_TCPWM0_TR_OUT036 (CYHAL_TRIGGER_TCPWM0_TR_OUT036_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1789 #define CYHAL_TRIGGER_TCPWM0_TR_OUT037 (CYHAL_TRIGGER_TCPWM0_TR_OUT037_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1790 #define CYHAL_TRIGGER_TCPWM0_TR_OUT038 (CYHAL_TRIGGER_TCPWM0_TR_OUT038_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1791 #define CYHAL_TRIGGER_TCPWM0_TR_OUT039 (CYHAL_TRIGGER_TCPWM0_TR_OUT039_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1792 #define CYHAL_TRIGGER_TCPWM0_TR_OUT040 (CYHAL_TRIGGER_TCPWM0_TR_OUT040_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1793 #define CYHAL_TRIGGER_TCPWM0_TR_OUT041 (CYHAL_TRIGGER_TCPWM0_TR_OUT041_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1794 #define CYHAL_TRIGGER_TCPWM0_TR_OUT042 (CYHAL_TRIGGER_TCPWM0_TR_OUT042_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1795 #define CYHAL_TRIGGER_TCPWM0_TR_OUT043 (CYHAL_TRIGGER_TCPWM0_TR_OUT043_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1796 #define CYHAL_TRIGGER_TCPWM0_TR_OUT044 (CYHAL_TRIGGER_TCPWM0_TR_OUT044_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1797 #define CYHAL_TRIGGER_TCPWM0_TR_OUT045 (CYHAL_TRIGGER_TCPWM0_TR_OUT045_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1798 #define CYHAL_TRIGGER_TCPWM0_TR_OUT046 (CYHAL_TRIGGER_TCPWM0_TR_OUT046_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1799 #define CYHAL_TRIGGER_TCPWM0_TR_OUT047 (CYHAL_TRIGGER_TCPWM0_TR_OUT047_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1800 #define CYHAL_TRIGGER_TCPWM0_TR_OUT048 (CYHAL_TRIGGER_TCPWM0_TR_OUT048_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1801 #define CYHAL_TRIGGER_TCPWM0_TR_OUT049 (CYHAL_TRIGGER_TCPWM0_TR_OUT049_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1802 #define CYHAL_TRIGGER_TCPWM0_TR_OUT050 (CYHAL_TRIGGER_TCPWM0_TR_OUT050_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1803 #define CYHAL_TRIGGER_TCPWM0_TR_OUT051 (CYHAL_TRIGGER_TCPWM0_TR_OUT051_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1804 #define CYHAL_TRIGGER_TCPWM0_TR_OUT052 (CYHAL_TRIGGER_TCPWM0_TR_OUT052_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1805 #define CYHAL_TRIGGER_TCPWM0_TR_OUT053 (CYHAL_TRIGGER_TCPWM0_TR_OUT053_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1806 #define CYHAL_TRIGGER_TCPWM0_TR_OUT054 (CYHAL_TRIGGER_TCPWM0_TR_OUT054_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1807 #define CYHAL_TRIGGER_TCPWM0_TR_OUT055 (CYHAL_TRIGGER_TCPWM0_TR_OUT055_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1808 #define CYHAL_TRIGGER_TCPWM0_TR_OUT056 (CYHAL_TRIGGER_TCPWM0_TR_OUT056_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1809 #define CYHAL_TRIGGER_TCPWM0_TR_OUT057 (CYHAL_TRIGGER_TCPWM0_TR_OUT057_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1810 #define CYHAL_TRIGGER_TCPWM0_TR_OUT058 (CYHAL_TRIGGER_TCPWM0_TR_OUT058_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1811 #define CYHAL_TRIGGER_TCPWM0_TR_OUT059 (CYHAL_TRIGGER_TCPWM0_TR_OUT059_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1812 #define CYHAL_TRIGGER_TCPWM0_TR_OUT060 (CYHAL_TRIGGER_TCPWM0_TR_OUT060_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1813 #define CYHAL_TRIGGER_TCPWM0_TR_OUT061 (CYHAL_TRIGGER_TCPWM0_TR_OUT061_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1814 #define CYHAL_TRIGGER_TCPWM0_TR_OUT062 (CYHAL_TRIGGER_TCPWM0_TR_OUT062_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1815 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1816 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1817 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1818 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0259 (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1819 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0260 (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1820 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0261 (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1821 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0262 (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1822 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0263 (CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1823 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0264 (CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1824 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0265 (CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1825 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0266 (CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1826 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0267 (CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1827 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0512 (CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1828 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0513 (CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1829 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0514 (CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1830 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0515 (CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1831 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0516 (CYHAL_TRIGGER_TCPWM0_TR_OUT0516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1832 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0517 (CYHAL_TRIGGER_TCPWM0_TR_OUT0517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1833 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0518 (CYHAL_TRIGGER_TCPWM0_TR_OUT0518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1834 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0519 (CYHAL_TRIGGER_TCPWM0_TR_OUT0519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1835 #define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1836 #define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1837 #define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1838 #define CYHAL_TRIGGER_TCPWM0_TR_OUT13 (CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1839 #define CYHAL_TRIGGER_TCPWM0_TR_OUT14 (CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1840 #define CYHAL_TRIGGER_TCPWM0_TR_OUT15 (CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1841 #define CYHAL_TRIGGER_TCPWM0_TR_OUT16 (CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1842 #define CYHAL_TRIGGER_TCPWM0_TR_OUT17 (CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1843 #define CYHAL_TRIGGER_TCPWM0_TR_OUT18 (CYHAL_TRIGGER_TCPWM0_TR_OUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1844 #define CYHAL_TRIGGER_TCPWM0_TR_OUT19 (CYHAL_TRIGGER_TCPWM0_TR_OUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1845 #define CYHAL_TRIGGER_TCPWM0_TR_OUT110 (CYHAL_TRIGGER_TCPWM0_TR_OUT110_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1846 #define CYHAL_TRIGGER_TCPWM0_TR_OUT111 (CYHAL_TRIGGER_TCPWM0_TR_OUT111_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1847 #define CYHAL_TRIGGER_TCPWM0_TR_OUT112 (CYHAL_TRIGGER_TCPWM0_TR_OUT112_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1848 #define CYHAL_TRIGGER_TCPWM0_TR_OUT113 (CYHAL_TRIGGER_TCPWM0_TR_OUT113_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1849 #define CYHAL_TRIGGER_TCPWM0_TR_OUT114 (CYHAL_TRIGGER_TCPWM0_TR_OUT114_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1850 #define CYHAL_TRIGGER_TCPWM0_TR_OUT115 (CYHAL_TRIGGER_TCPWM0_TR_OUT115_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1851 #define CYHAL_TRIGGER_TCPWM0_TR_OUT116 (CYHAL_TRIGGER_TCPWM0_TR_OUT116_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1852 #define CYHAL_TRIGGER_TCPWM0_TR_OUT117 (CYHAL_TRIGGER_TCPWM0_TR_OUT117_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1853 #define CYHAL_TRIGGER_TCPWM0_TR_OUT118 (CYHAL_TRIGGER_TCPWM0_TR_OUT118_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1854 #define CYHAL_TRIGGER_TCPWM0_TR_OUT119 (CYHAL_TRIGGER_TCPWM0_TR_OUT119_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1855 #define CYHAL_TRIGGER_TCPWM0_TR_OUT120 (CYHAL_TRIGGER_TCPWM0_TR_OUT120_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1856 #define CYHAL_TRIGGER_TCPWM0_TR_OUT121 (CYHAL_TRIGGER_TCPWM0_TR_OUT121_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1857 #define CYHAL_TRIGGER_TCPWM0_TR_OUT122 (CYHAL_TRIGGER_TCPWM0_TR_OUT122_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1858 #define CYHAL_TRIGGER_TCPWM0_TR_OUT123 (CYHAL_TRIGGER_TCPWM0_TR_OUT123_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1859 #define CYHAL_TRIGGER_TCPWM0_TR_OUT124 (CYHAL_TRIGGER_TCPWM0_TR_OUT124_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1860 #define CYHAL_TRIGGER_TCPWM0_TR_OUT125 (CYHAL_TRIGGER_TCPWM0_TR_OUT125_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1861 #define CYHAL_TRIGGER_TCPWM0_TR_OUT126 (CYHAL_TRIGGER_TCPWM0_TR_OUT126_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1862 #define CYHAL_TRIGGER_TCPWM0_TR_OUT127 (CYHAL_TRIGGER_TCPWM0_TR_OUT127_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1863 #define CYHAL_TRIGGER_TCPWM0_TR_OUT128 (CYHAL_TRIGGER_TCPWM0_TR_OUT128_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1864 #define CYHAL_TRIGGER_TCPWM0_TR_OUT129 (CYHAL_TRIGGER_TCPWM0_TR_OUT129_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1865 #define CYHAL_TRIGGER_TCPWM0_TR_OUT130 (CYHAL_TRIGGER_TCPWM0_TR_OUT130_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1866 #define CYHAL_TRIGGER_TCPWM0_TR_OUT131 (CYHAL_TRIGGER_TCPWM0_TR_OUT131_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1867 #define CYHAL_TRIGGER_TCPWM0_TR_OUT132 (CYHAL_TRIGGER_TCPWM0_TR_OUT132_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1868 #define CYHAL_TRIGGER_TCPWM0_TR_OUT133 (CYHAL_TRIGGER_TCPWM0_TR_OUT133_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1869 #define CYHAL_TRIGGER_TCPWM0_TR_OUT134 (CYHAL_TRIGGER_TCPWM0_TR_OUT134_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1870 #define CYHAL_TRIGGER_TCPWM0_TR_OUT135 (CYHAL_TRIGGER_TCPWM0_TR_OUT135_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1871 #define CYHAL_TRIGGER_TCPWM0_TR_OUT136 (CYHAL_TRIGGER_TCPWM0_TR_OUT136_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1872 #define CYHAL_TRIGGER_TCPWM0_TR_OUT137 (CYHAL_TRIGGER_TCPWM0_TR_OUT137_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1873 #define CYHAL_TRIGGER_TCPWM0_TR_OUT138 (CYHAL_TRIGGER_TCPWM0_TR_OUT138_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1874 #define CYHAL_TRIGGER_TCPWM0_TR_OUT139 (CYHAL_TRIGGER_TCPWM0_TR_OUT139_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1875 #define CYHAL_TRIGGER_TCPWM0_TR_OUT140 (CYHAL_TRIGGER_TCPWM0_TR_OUT140_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1876 #define CYHAL_TRIGGER_TCPWM0_TR_OUT141 (CYHAL_TRIGGER_TCPWM0_TR_OUT141_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1877 #define CYHAL_TRIGGER_TCPWM0_TR_OUT142 (CYHAL_TRIGGER_TCPWM0_TR_OUT142_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1878 #define CYHAL_TRIGGER_TCPWM0_TR_OUT143 (CYHAL_TRIGGER_TCPWM0_TR_OUT143_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1879 #define CYHAL_TRIGGER_TCPWM0_TR_OUT144 (CYHAL_TRIGGER_TCPWM0_TR_OUT144_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1880 #define CYHAL_TRIGGER_TCPWM0_TR_OUT145 (CYHAL_TRIGGER_TCPWM0_TR_OUT145_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1881 #define CYHAL_TRIGGER_TCPWM0_TR_OUT146 (CYHAL_TRIGGER_TCPWM0_TR_OUT146_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1882 #define CYHAL_TRIGGER_TCPWM0_TR_OUT147 (CYHAL_TRIGGER_TCPWM0_TR_OUT147_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1883 #define CYHAL_TRIGGER_TCPWM0_TR_OUT148 (CYHAL_TRIGGER_TCPWM0_TR_OUT148_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1884 #define CYHAL_TRIGGER_TCPWM0_TR_OUT149 (CYHAL_TRIGGER_TCPWM0_TR_OUT149_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1885 #define CYHAL_TRIGGER_TCPWM0_TR_OUT150 (CYHAL_TRIGGER_TCPWM0_TR_OUT150_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1886 #define CYHAL_TRIGGER_TCPWM0_TR_OUT151 (CYHAL_TRIGGER_TCPWM0_TR_OUT151_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1887 #define CYHAL_TRIGGER_TCPWM0_TR_OUT152 (CYHAL_TRIGGER_TCPWM0_TR_OUT152_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1888 #define CYHAL_TRIGGER_TCPWM0_TR_OUT153 (CYHAL_TRIGGER_TCPWM0_TR_OUT153_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1889 #define CYHAL_TRIGGER_TCPWM0_TR_OUT154 (CYHAL_TRIGGER_TCPWM0_TR_OUT154_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1890 #define CYHAL_TRIGGER_TCPWM0_TR_OUT155 (CYHAL_TRIGGER_TCPWM0_TR_OUT155_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1891 #define CYHAL_TRIGGER_TCPWM0_TR_OUT156 (CYHAL_TRIGGER_TCPWM0_TR_OUT156_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1892 #define CYHAL_TRIGGER_TCPWM0_TR_OUT157 (CYHAL_TRIGGER_TCPWM0_TR_OUT157_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1893 #define CYHAL_TRIGGER_TCPWM0_TR_OUT158 (CYHAL_TRIGGER_TCPWM0_TR_OUT158_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1894 #define CYHAL_TRIGGER_TCPWM0_TR_OUT159 (CYHAL_TRIGGER_TCPWM0_TR_OUT159_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1895 #define CYHAL_TRIGGER_TCPWM0_TR_OUT160 (CYHAL_TRIGGER_TCPWM0_TR_OUT160_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1896 #define CYHAL_TRIGGER_TCPWM0_TR_OUT161 (CYHAL_TRIGGER_TCPWM0_TR_OUT161_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1897 #define CYHAL_TRIGGER_TCPWM0_TR_OUT162 (CYHAL_TRIGGER_TCPWM0_TR_OUT162_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1898 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1899 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1900 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1901 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1259 (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1902 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1260 (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1903 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1261 (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1904 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1262 (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1905 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1263 (CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1906 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1264 (CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1907 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1265 (CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1908 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1266 (CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1909 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1267 (CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1910 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1512 (CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1911 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1513 (CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1912 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1514 (CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1913 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1515 (CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1914 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1516 (CYHAL_TRIGGER_TCPWM0_TR_OUT1516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1915 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1517 (CYHAL_TRIGGER_TCPWM0_TR_OUT1517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1916 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1518 (CYHAL_TRIGGER_TCPWM0_TR_OUT1518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1917 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1519 (CYHAL_TRIGGER_TCPWM0_TR_OUT1519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1918 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1919 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1920 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1921 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1922 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1923 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1924 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1925 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1926 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1927 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1928 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1929 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1930 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1931 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1932 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
1933 
1934 /** @brief Name of each output trigger. */
1935 typedef enum
1936 {
1937     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[0]
1938     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 = 1, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[1]
1939     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK2 = 2, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[2]
1940     CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK3 = 3, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[3]
1941     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK0 = 4, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[0]
1942     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK1 = 5, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[1]
1943     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK2 = 6, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[2]
1944     CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK3 = 7, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[3]
1945     CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 8, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0]
1946     CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 = 9, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[1]
1947     CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN2 = 10, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[2]
1948     CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN3 = 11, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[3]
1949     CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN0 = 12, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[0]
1950     CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN1 = 13, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[1]
1951     CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN2 = 14, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[2]
1952     CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN3 = 15, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[3]
1953     CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 16, //!< Debug Multiplexer - cpuss.cti_tr_in[0]
1954     CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 17, //!< Debug Multiplexer - cpuss.cti_tr_in[1]
1955     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 18, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[0]
1956     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 19, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[1]
1957     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 20, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[2]
1958     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 21, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[3]
1959     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN4 = 22, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[4]
1960     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN5 = 23, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[5]
1961     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN6 = 24, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[6]
1962     CYHAL_TRIGGER_CPUSS_DMAC_TR_IN7 = 25, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[7]
1963     CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 26, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
1964     CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 27, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
1965     CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 28, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
1966     CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 29, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
1967     CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 30, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
1968     CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 31, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
1969     CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 32, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
1970     CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 33, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
1971     CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 34, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[8]
1972     CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 35, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[9]
1973     CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 36, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[10]
1974     CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 37, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[11]
1975     CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 38, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[12]
1976     CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 39, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[13]
1977     CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 40, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[14]
1978     CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 41, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[15]
1979     CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 42, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[16]
1980     CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 43, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[17]
1981     CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 44, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[18]
1982     CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 45, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[19]
1983     CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 46, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[20]
1984     CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 47, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[21]
1985     CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 48, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[22]
1986     CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 49, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[23]
1987     CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 50, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[24]
1988     CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 51, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[25]
1989     CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 52, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[26]
1990     CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 53, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[27]
1991     CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 54, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[28]
1992     CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 = 55, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[29]
1993     CYHAL_TRIGGER_CPUSS_DW0_TR_IN30 = 56, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[30]
1994     CYHAL_TRIGGER_CPUSS_DW0_TR_IN31 = 57, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[31]
1995     CYHAL_TRIGGER_CPUSS_DW0_TR_IN32 = 58, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[32]
1996     CYHAL_TRIGGER_CPUSS_DW0_TR_IN33 = 59, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[33]
1997     CYHAL_TRIGGER_CPUSS_DW0_TR_IN34 = 60, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[34]
1998     CYHAL_TRIGGER_CPUSS_DW0_TR_IN35 = 61, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[35]
1999     CYHAL_TRIGGER_CPUSS_DW0_TR_IN36 = 62, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[36]
2000     CYHAL_TRIGGER_CPUSS_DW0_TR_IN37 = 63, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[37]
2001     CYHAL_TRIGGER_CPUSS_DW0_TR_IN38 = 64, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[38]
2002     CYHAL_TRIGGER_CPUSS_DW0_TR_IN39 = 65, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[39]
2003     CYHAL_TRIGGER_CPUSS_DW0_TR_IN40 = 66, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[40]
2004     CYHAL_TRIGGER_CPUSS_DW0_TR_IN41 = 67, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[41]
2005     CYHAL_TRIGGER_CPUSS_DW0_TR_IN42 = 68, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[42]
2006     CYHAL_TRIGGER_CPUSS_DW0_TR_IN43 = 69, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[43]
2007     CYHAL_TRIGGER_CPUSS_DW0_TR_IN44 = 70, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[44]
2008     CYHAL_TRIGGER_CPUSS_DW0_TR_IN45 = 71, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[45]
2009     CYHAL_TRIGGER_CPUSS_DW0_TR_IN46 = 72, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[46]
2010     CYHAL_TRIGGER_CPUSS_DW0_TR_IN47 = 73, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[47]
2011     CYHAL_TRIGGER_CPUSS_DW0_TR_IN48 = 74, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[48]
2012     CYHAL_TRIGGER_CPUSS_DW0_TR_IN49 = 75, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[49]
2013     CYHAL_TRIGGER_CPUSS_DW0_TR_IN50 = 76, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[50]
2014     CYHAL_TRIGGER_CPUSS_DW0_TR_IN51 = 77, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[51]
2015     CYHAL_TRIGGER_CPUSS_DW0_TR_IN52 = 78, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[52]
2016     CYHAL_TRIGGER_CPUSS_DW0_TR_IN53 = 79, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[53]
2017     CYHAL_TRIGGER_CPUSS_DW0_TR_IN54 = 80, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[54]
2018     CYHAL_TRIGGER_CPUSS_DW0_TR_IN55 = 81, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[55]
2019     CYHAL_TRIGGER_CPUSS_DW0_TR_IN56 = 82, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[56]
2020     CYHAL_TRIGGER_CPUSS_DW0_TR_IN57 = 83, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[57]
2021     CYHAL_TRIGGER_CPUSS_DW0_TR_IN58 = 84, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[58]
2022     CYHAL_TRIGGER_CPUSS_DW0_TR_IN59 = 85, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[59]
2023     CYHAL_TRIGGER_CPUSS_DW0_TR_IN60 = 86, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[60]
2024     CYHAL_TRIGGER_CPUSS_DW0_TR_IN61 = 87, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[61]
2025     CYHAL_TRIGGER_CPUSS_DW0_TR_IN62 = 88, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[62]
2026     CYHAL_TRIGGER_CPUSS_DW0_TR_IN63 = 89, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[63]
2027     CYHAL_TRIGGER_CPUSS_DW0_TR_IN64 = 90, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[64]
2028     CYHAL_TRIGGER_CPUSS_DW0_TR_IN65 = 91, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[65]
2029     CYHAL_TRIGGER_CPUSS_DW0_TR_IN66 = 92, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[66]
2030     CYHAL_TRIGGER_CPUSS_DW0_TR_IN67 = 93, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[67]
2031     CYHAL_TRIGGER_CPUSS_DW0_TR_IN68 = 94, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[68]
2032     CYHAL_TRIGGER_CPUSS_DW0_TR_IN69 = 95, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[69]
2033     CYHAL_TRIGGER_CPUSS_DW0_TR_IN70 = 96, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[70]
2034     CYHAL_TRIGGER_CPUSS_DW0_TR_IN71 = 97, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[71]
2035     CYHAL_TRIGGER_CPUSS_DW0_TR_IN72 = 98, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[72]
2036     CYHAL_TRIGGER_CPUSS_DW0_TR_IN73 = 99, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[73]
2037     CYHAL_TRIGGER_CPUSS_DW0_TR_IN74 = 100, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[74]
2038     CYHAL_TRIGGER_CPUSS_DW0_TR_IN75 = 101, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[75]
2039     CYHAL_TRIGGER_CPUSS_DW0_TR_IN76 = 102, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[76]
2040     CYHAL_TRIGGER_CPUSS_DW0_TR_IN77 = 103, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[77]
2041     CYHAL_TRIGGER_CPUSS_DW0_TR_IN78 = 104, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[78]
2042     CYHAL_TRIGGER_CPUSS_DW0_TR_IN79 = 105, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[79]
2043     CYHAL_TRIGGER_CPUSS_DW0_TR_IN80 = 106, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[80]
2044     CYHAL_TRIGGER_CPUSS_DW0_TR_IN81 = 107, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[81]
2045     CYHAL_TRIGGER_CPUSS_DW0_TR_IN82 = 108, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[82]
2046     CYHAL_TRIGGER_CPUSS_DW0_TR_IN83 = 109, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[83]
2047     CYHAL_TRIGGER_CPUSS_DW0_TR_IN84 = 110, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[84]
2048     CYHAL_TRIGGER_CPUSS_DW0_TR_IN85 = 111, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[85]
2049     CYHAL_TRIGGER_CPUSS_DW0_TR_IN86 = 112, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[86]
2050     CYHAL_TRIGGER_CPUSS_DW0_TR_IN87 = 113, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[87]
2051     CYHAL_TRIGGER_CPUSS_DW0_TR_IN88 = 114, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[88]
2052     CYHAL_TRIGGER_CPUSS_DW0_TR_IN89 = 115, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[89]
2053     CYHAL_TRIGGER_CPUSS_DW0_TR_IN90 = 116, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[90]
2054     CYHAL_TRIGGER_CPUSS_DW0_TR_IN91 = 117, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[91]
2055     CYHAL_TRIGGER_CPUSS_DW0_TR_IN92 = 118, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[92]
2056     CYHAL_TRIGGER_CPUSS_DW0_TR_IN93 = 119, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[93]
2057     CYHAL_TRIGGER_CPUSS_DW0_TR_IN94 = 120, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[94]
2058     CYHAL_TRIGGER_CPUSS_DW0_TR_IN95 = 121, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[95]
2059     CYHAL_TRIGGER_CPUSS_DW0_TR_IN96 = 122, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[96]
2060     CYHAL_TRIGGER_CPUSS_DW0_TR_IN97 = 123, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[97]
2061     CYHAL_TRIGGER_CPUSS_DW0_TR_IN98 = 124, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[98]
2062     CYHAL_TRIGGER_CPUSS_DW0_TR_IN99 = 125, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[99]
2063     CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 126, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
2064     CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 127, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
2065     CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 128, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
2066     CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 129, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
2067     CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 130, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
2068     CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 131, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
2069     CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 132, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
2070     CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 133, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
2071     CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 134, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[8]
2072     CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 135, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[9]
2073     CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 136, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[10]
2074     CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 137, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[11]
2075     CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 138, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[12]
2076     CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 139, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[13]
2077     CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 140, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[14]
2078     CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 141, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[15]
2079     CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 142, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[16]
2080     CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 143, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[17]
2081     CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 144, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[18]
2082     CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 145, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[19]
2083     CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 146, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[20]
2084     CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 147, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[21]
2085     CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 148, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[22]
2086     CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 149, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[23]
2087     CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 150, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[24]
2088     CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 151, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[25]
2089     CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 152, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[26]
2090     CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 153, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[27]
2091     CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 154, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[28]
2092     CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 155, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[29]
2093     CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 156, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[30]
2094     CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 157, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[31]
2095     CYHAL_TRIGGER_CPUSS_DW1_TR_IN32 = 158, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[32]
2096     CYHAL_TRIGGER_CPUSS_DW1_TR_IN33 = 159, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[33]
2097     CYHAL_TRIGGER_CPUSS_DW1_TR_IN34 = 160, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[34]
2098     CYHAL_TRIGGER_CPUSS_DW1_TR_IN35 = 161, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[35]
2099     CYHAL_TRIGGER_CPUSS_DW1_TR_IN36 = 162, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[36]
2100     CYHAL_TRIGGER_CPUSS_DW1_TR_IN37 = 163, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[37]
2101     CYHAL_TRIGGER_CPUSS_DW1_TR_IN38 = 164, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[38]
2102     CYHAL_TRIGGER_CPUSS_DW1_TR_IN39 = 165, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[39]
2103     CYHAL_TRIGGER_CPUSS_DW1_TR_IN40 = 166, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[40]
2104     CYHAL_TRIGGER_CPUSS_DW1_TR_IN41 = 167, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[41]
2105     CYHAL_TRIGGER_CPUSS_DW1_TR_IN42 = 168, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[42]
2106     CYHAL_TRIGGER_CPUSS_DW1_TR_IN43 = 169, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[43]
2107     CYHAL_TRIGGER_CPUSS_DW1_TR_IN44 = 170, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[44]
2108     CYHAL_TRIGGER_CPUSS_DW1_TR_IN45 = 171, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[45]
2109     CYHAL_TRIGGER_CPUSS_DW1_TR_IN46 = 172, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[46]
2110     CYHAL_TRIGGER_CPUSS_DW1_TR_IN47 = 173, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[47]
2111     CYHAL_TRIGGER_CPUSS_DW1_TR_IN48 = 174, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[48]
2112     CYHAL_TRIGGER_CPUSS_DW1_TR_IN49 = 175, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[49]
2113     CYHAL_TRIGGER_CPUSS_DW1_TR_IN50 = 176, //!< SMIF DW1 Triggers - cpuss.dw1_tr_in[50]
2114     CYHAL_TRIGGER_CPUSS_DW1_TR_IN51 = 177, //!< SMIF DW1 Triggers - cpuss.dw1_tr_in[51]
2115     CYHAL_TRIGGER_CPUSS_DW1_TR_IN52 = 178, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[52]
2116     CYHAL_TRIGGER_CPUSS_DW1_TR_IN53 = 179, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[53]
2117     CYHAL_TRIGGER_CPUSS_DW1_TR_IN54 = 180, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[54]
2118     CYHAL_TRIGGER_CPUSS_DW1_TR_IN55 = 181, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[55]
2119     CYHAL_TRIGGER_CPUSS_DW1_TR_IN56 = 182, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[56]
2120     CYHAL_TRIGGER_CPUSS_DW1_TR_IN57 = 183, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[57]
2121     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 = 184, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[0]
2122     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 = 185, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[1]
2123     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER2 = 186, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[2]
2124     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER3 = 187, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[3]
2125     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER4 = 188, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[4]
2126     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER5 = 189, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[5]
2127     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER6 = 190, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[6]
2128     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER7 = 191, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[7]
2129     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER8 = 192, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[8]
2130     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER9 = 193, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[9]
2131     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER10 = 194, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[10]
2132     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER11 = 195, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[11]
2133     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER12 = 196, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[12]
2134     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER13 = 197, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[13]
2135     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER14 = 198, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[14]
2136     CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER15 = 199, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[15]
2137     CYHAL_TRIGGER_PASS0_TR_DEBUG_FREEZE = 200, //!< Debug Multiplexer - pass[0].tr_debug_freeze
2138     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN0 = 201, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[0]
2139     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN1 = 202, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[1]
2140     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN2 = 203, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[2]
2141     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN3 = 204, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[3]
2142     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN4 = 205, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[4]
2143     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN5 = 206, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[5]
2144     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN6 = 207, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[6]
2145     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN7 = 208, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[7]
2146     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN8 = 209, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[8]
2147     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN9 = 210, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[9]
2148     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN10 = 211, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[10]
2149     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN11 = 212, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[11]
2150     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN12 = 213, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[12]
2151     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN13 = 214, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[13]
2152     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN14 = 215, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[14]
2153     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN15 = 216, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[15]
2154     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN16 = 217, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[16]
2155     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN17 = 218, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[17]
2156     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN18 = 219, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[18]
2157     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN19 = 220, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[19]
2158     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN20 = 221, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[20]
2159     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN21 = 222, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[21]
2160     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN22 = 223, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[22]
2161     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN23 = 224, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[23]
2162     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN24 = 225, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[24]
2163     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN25 = 226, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[25]
2164     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN26 = 227, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[26]
2165     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN27 = 228, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[27]
2166     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN28 = 229, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[28]
2167     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN29 = 230, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[29]
2168     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN30 = 231, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[30]
2169     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN31 = 232, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[31]
2170     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN32 = 233, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[32]
2171     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN33 = 234, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[33]
2172     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN34 = 235, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[34]
2173     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN35 = 236, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[35]
2174     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN36 = 237, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[36]
2175     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN37 = 238, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[37]
2176     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN38 = 239, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[38]
2177     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN39 = 240, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[39]
2178     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN40 = 241, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[40]
2179     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN41 = 242, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[41]
2180     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN42 = 243, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[42]
2181     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN43 = 244, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[43]
2182     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN44 = 245, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[44]
2183     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN45 = 246, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[45]
2184     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN46 = 247, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[46]
2185     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN47 = 248, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[47]
2186     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN48 = 249, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[48]
2187     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN49 = 250, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[49]
2188     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN50 = 251, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[50]
2189     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN51 = 252, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[51]
2190     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN52 = 253, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[52]
2191     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN53 = 254, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[53]
2192     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN54 = 255, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[54]
2193     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN55 = 256, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[55]
2194     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN56 = 257, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[56]
2195     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN57 = 258, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[57]
2196     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN58 = 259, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[58]
2197     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN59 = 260, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[59]
2198     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN60 = 261, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[60]
2199     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN61 = 262, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[61]
2200     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN62 = 263, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[62]
2201     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN63 = 264, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[63]
2202     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN64 = 265, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[64]
2203     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN65 = 266, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[65]
2204     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN66 = 267, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[66]
2205     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN67 = 268, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[67]
2206     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN68 = 269, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[68]
2207     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN69 = 270, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[69]
2208     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN70 = 271, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[70]
2209     CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN71 = 272, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[71]
2210     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN0 = 273, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[0]
2211     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN1 = 274, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[1]
2212     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN2 = 275, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[2]
2213     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN3 = 276, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[3]
2214     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN4 = 277, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[4]
2215     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN5 = 278, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[5]
2216     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN6 = 279, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[6]
2217     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN7 = 280, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[7]
2218     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN8 = 281, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[8]
2219     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN9 = 282, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[9]
2220     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN10 = 283, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[10]
2221     CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN11 = 284, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[11]
2222     CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 285, //!< Debug Multiplexer - peri.tr_dbg_freeze
2223     CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 286, //!< Debug Multiplexer - peri.tr_io_output[0]
2224     CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 287, //!< Debug Multiplexer - peri.tr_io_output[1]
2225     CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 288, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[0]
2226     CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 = 289, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[1]
2227     CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT2 = 290, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[2]
2228     CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT = 291, //!< Debug Multiplexer - srss.tr_debug_freeze_wdt
2229     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 292, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[0]
2230     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 293, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[1]
2231     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 294, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[2]
2232     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 295, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[3]
2233     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 296, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[4]
2234     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 297, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[5]
2235     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 298, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[6]
2236     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 299, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[7]
2237     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 300, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[8]
2238     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 301, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[9]
2239     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 302, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[10]
2240     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 303, //!< TCPWM loopback mux - tcpwm[0].tr_all_cnt_in[11]
2241     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 304, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[12]
2242     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 305, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[13]
2243     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 306, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[14]
2244     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 307, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[15]
2245     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 308, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[16]
2246     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 309, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[17]
2247     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 310, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[18]
2248     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 311, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[19]
2249     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 312, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[20]
2250     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 313, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[21]
2251     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 314, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[22]
2252     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 315, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[23]
2253     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 316, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[24]
2254     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 317, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[25]
2255     CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 318, //!< TCPWM Trigger Multiplexer - tcpwm[0].tr_all_cnt_in[26]
2256     CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 319, //!< Debug Multiplexer - tcpwm[0].tr_debug_freeze
2257     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN2 = 320, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[2]
2258     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN5 = 321, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[5]
2259     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN8 = 322, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[8]
2260     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN11 = 323, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[11]
2261     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN14 = 324, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[14]
2262     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN17 = 325, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[17]
2263     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN20 = 326, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[20]
2264     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN23 = 327, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[23]
2265     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN26 = 328, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[26]
2266     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN29 = 329, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[29]
2267     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN32 = 330, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[32]
2268     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN35 = 331, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[35]
2269     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN38 = 332, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[38]
2270     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN41 = 333, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[41]
2271     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN44 = 334, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[44]
2272     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN47 = 335, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[47]
2273     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN50 = 336, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[50]
2274     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN53 = 337, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[53]
2275     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN56 = 338, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[56]
2276     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN59 = 339, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[59]
2277     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN62 = 340, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[62]
2278     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN65 = 341, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[65]
2279     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN68 = 342, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[68]
2280     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN71 = 343, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[71]
2281     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN74 = 344, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[74]
2282     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN77 = 345, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[77]
2283     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN80 = 346, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[80]
2284     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN83 = 347, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[83]
2285     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN86 = 348, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[86]
2286     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN89 = 349, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[89]
2287     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN92 = 350, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[92]
2288     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN95 = 351, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[95]
2289     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN98 = 352, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[98]
2290     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN101 = 353, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[101]
2291     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN104 = 354, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[104]
2292     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN107 = 355, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[107]
2293     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN110 = 356, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[110]
2294     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN113 = 357, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[113]
2295     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN116 = 358, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[116]
2296     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN119 = 359, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[119]
2297     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN122 = 360, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[122]
2298     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN125 = 361, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[125]
2299     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN128 = 362, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[128]
2300     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN131 = 363, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[131]
2301     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN134 = 364, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[134]
2302     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN137 = 365, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[137]
2303     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN140 = 366, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[140]
2304     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN143 = 367, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[143]
2305     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN146 = 368, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[146]
2306     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN149 = 369, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[149]
2307     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN152 = 370, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[152]
2308     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN155 = 371, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[155]
2309     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN158 = 372, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[158]
2310     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN161 = 373, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[161]
2311     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN164 = 374, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[164]
2312     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN167 = 375, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[167]
2313     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN170 = 376, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[170]
2314     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN173 = 377, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[173]
2315     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN176 = 378, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[176]
2316     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN179 = 379, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[179]
2317     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN770 = 380, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[770]
2318     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN773 = 381, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[773]
2319     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN776 = 382, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[776]
2320     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN779 = 383, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[779]
2321     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN782 = 384, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[782]
2322     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN785 = 385, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[785]
2323     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN788 = 386, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[788]
2324     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN791 = 387, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[791]
2325     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN794 = 388, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[794]
2326     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN797 = 389, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[797]
2327     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN800 = 390, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[800]
2328     CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN803 = 391, //!< PASS to PWM direct connect - tcpwm[0].tr_one_cnt_in[803]
2329     CYHAL_TRIGGER_TR_GROUP9_INPUT1 = 392, //!< Debug Reduction #1 - tr_group[9].input[1]
2330     CYHAL_TRIGGER_TR_GROUP9_INPUT2 = 393, //!< Debug Reduction #1 - tr_group[9].input[2]
2331     CYHAL_TRIGGER_TR_GROUP9_INPUT3 = 394, //!< Debug Reduction #1 - tr_group[9].input[3]
2332     CYHAL_TRIGGER_TR_GROUP9_INPUT4 = 395, //!< Debug Reduction #1 - tr_group[9].input[4]
2333     CYHAL_TRIGGER_TR_GROUP9_INPUT5 = 396, //!< Debug Reduction #1 - tr_group[9].input[5]
2334     CYHAL_TRIGGER_TR_GROUP9_INPUT6 = 397, //!< Debug Reduction #2 - tr_group[9].input[6]
2335     CYHAL_TRIGGER_TR_GROUP9_INPUT7 = 398, //!< Debug Reduction #2 - tr_group[9].input[7]
2336     CYHAL_TRIGGER_TR_GROUP9_INPUT8 = 399, //!< Debug Reduction #2 - tr_group[9].input[8]
2337     CYHAL_TRIGGER_TR_GROUP9_INPUT9 = 400, //!< Debug Reduction #2 - tr_group[9].input[9]
2338     CYHAL_TRIGGER_TR_GROUP9_INPUT10 = 401, //!< Debug Reduction #2 - tr_group[9].input[10]
2339     CYHAL_TRIGGER_TR_GROUP9_INPUT11 = 402, //!< Debug Reduction #3 - tr_group[9].input[11]
2340     CYHAL_TRIGGER_TR_GROUP9_INPUT12 = 403, //!< Debug Reduction #3 - tr_group[9].input[12]
2341     CYHAL_TRIGGER_TR_GROUP9_INPUT13 = 404, //!< Debug Reduction #3 - tr_group[9].input[13]
2342     CYHAL_TRIGGER_TR_GROUP9_INPUT14 = 405, //!< Debug Reduction #3 - tr_group[9].input[14]
2343     CYHAL_TRIGGER_TR_GROUP9_INPUT15 = 406, //!< Debug Reduction #3 - tr_group[9].input[15]
2344 } cyhal_trigger_dest_xmc7100_t;
2345 
2346 /** Typedef from device family specific trigger dest to generic trigger dest */
2347 typedef cyhal_trigger_dest_xmc7100_t cyhal_dest_t;
2348 
2349 /** \cond INTERNAL */
2350 /** Table of number of inputs to each mux. */
2351 extern const uint16_t cyhal_sources_per_mux[24];
2352 
2353 /** Table indicating whether mux is 1to1. */
2354 extern const bool cyhal_is_mux_1to1[24];
2355 
2356 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
2357 extern const _cyhal_trigger_source_xmc7100_t* cyhal_mux_to_sources [24];
2358 
2359 /** Maps each cyhal_destination_t to a mux index.
2360  * If bit 8 of the mux index is set, this denotes that the trigger is a
2361  * one to one trigger.
2362  */
2363 extern const uint8_t cyhal_dest_to_mux[407];
2364 
2365 /* Maps each cyhal_destination_t to a specific output in its mux */
2366 extern const uint8_t cyhal_mux_dest_index[407];
2367 /** \endcond */
2368 
2369 #if defined(__cplusplus)
2370 }
2371 #endif /* __cplusplus */
2372 /** \} group_hal_impl_triggers_xmc7100 */
2373 #endif /* _CYHAL_TRIGGERS_XMC7100_H_ */
2374 
2375 
2376 /* [] END OF FILE */
2377