1 /***************************************************************************//** 2 * \file cyhal_syspm_impl.h 3 * 4 * \brief 5 * Provides a PSoC™ Specific interface for interacting with the Infineon power 6 * management and system clock configuration. This interface abstracts out the 7 * chip specific details. If any chip specific functionality is necessary, or 8 * performance is critical the low level functions can be used directly. 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation 14 * 15 * SPDX-License-Identifier: Apache-2.0 16 * 17 * Licensed under the Apache License, Version 2.0 (the "License"); 18 * you may not use this file except in compliance with the License. 19 * You may obtain a copy of the License at 20 * 21 * http://www.apache.org/licenses/LICENSE-2.0 22 * 23 * Unless required by applicable law or agreed to in writing, software 24 * distributed under the License is distributed on an "AS IS" BASIS, 25 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 * See the License for the specific language governing permissions and 27 * limitations under the License. 28 *******************************************************************************/ 29 30 #pragma once 31 32 #if defined(COMPONENT_CAT1) 33 /** 34 * \addtogroup group_hal_impl_syspm System Power Management 35 * \ingroup group_hal_impl 36 * \{ 37 * On CAT1 devices, the Pin based Hibernate wakeup sources (\ref CYHAL_SYSPM_HIBERNATE_PINA_LOW, 38 * \ref CYHAL_SYSPM_HIBERNATE_PINA_HIGH, \ref CYHAL_SYSPM_HIBERNATE_PINB_LOW, and \ref 39 * CYHAL_SYSPM_HIBERNATE_PINB_HIGH) are mapped to datsheet capabilities as follows:<br> 40 * PINA = hibernate_wakeup[0]<br> 41 * PINB = hibernate_wakeup[1] 42 * 43 * The CAT1 (PSoC™ 6) Power Management has the following characteristics:<br> 44 * \ref CYHAL_SYSPM_SYSTEM_NORMAL equates to the Low Power mode<br> 45 * \ref CYHAL_SYSPM_SYSTEM_LOW equates to the Ultra Low Power mode 46 * 47 * \section group_hal_impl_syspm_ulp Switching the System into Ultra Low Power 48 * Before switching into system Ultra Low Power mode, ensure that the device meets 49 * the requirements below: 50 * 51 * * The core regulator voltage is set to <b>0.9 V (nominal)</b> and the 52 * following limitations must be meet: 53 * * The maximum operating frequency for all Clk_HF paths must not exceed 54 * <b>50* MHz</b> 55 * * The maximum operating frequency for peripheral and slow clock must not exceed 56 * <b>25* MHz</b>. 57 * * The total current consumption must be less than or equal to <b>20* mA</b> 58 * * Flash write operations are prohibited. Flash is Read-only in this mode. 59 * 60 * \note * - Numbers shown are approximate and real limit values may be 61 * different because they are device specific. You should refer to the device 62 * datasheet for exact values of maximum frequency and current in system 63 * ULP mode. 64 * \} group_hal_impl_syspm 65 */ 66 #endif 67 68 #if defined(__cplusplus) 69 extern "C" { 70 #endif 71 72 /** 73 * \cond INTERNAL 74 */ 75 76 void _cyhal_syspm_register_peripheral_callback(cyhal_syspm_callback_data_t *callback_data); 77 void _cyhal_syspm_unregister_peripheral_callback(cyhal_syspm_callback_data_t *callback_data); 78 79 cy_rslt_t cyhal_syspm_tickless_sleep_deepsleep(cyhal_lptimer_t *obj, uint32_t desired_ms, uint32_t *actual_ms, bool deep_sleep); 80 81 #define cyhal_syspm_tickless_deepsleep(obj, desired_ms, actual_ms) cyhal_syspm_tickless_sleep_deepsleep(obj, desired_ms, actual_ms, true) 82 83 #define cyhal_syspm_tickless_sleep(obj, desired_ms, actual_ms) cyhal_syspm_tickless_sleep_deepsleep(obj, desired_ms, actual_ms, false) 84 85 86 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D) 87 #define cyhal_syspm_sleep() Cy_SysPm_CpuEnterSleep(CY_SYSPM_WAIT_FOR_INTERRUPT) 88 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1D) 89 #define cyhal_syspm_get_system_state() (Cy_SysPm_IsSystemUlp() ? CYHAL_SYSPM_SYSTEM_LOW : CYHAL_SYSPM_SYSTEM_NORMAL) 90 #elif defined(COMPONENT_CAT1B) 91 #define cyhal_syspm_get_system_state() (Cy_SysPm_IsSystemLpActiveEnabled() ? CYHAL_SYSPM_SYSTEM_LOW : CYHAL_SYSPM_SYSTEM_NORMAL) 92 #elif defined(COMPONENT_CAT1C) 93 #define cyhal_syspm_get_system_state() (CYHAL_SYSPM_SYSTEM_NORMAL) 94 #endif 95 #elif defined(COMPONENT_CAT2) /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */ 96 #define cyhal_syspm_sleep() Cy_SysPm_CpuEnterSleep() 97 #define cyhal_syspm_get_system_state() (CYHAL_SYSPM_SYSTEM_NORMAL) 98 #endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */ 99 100 /** \endcond */ 101 102 #if defined(__cplusplus) 103 } 104 #endif 105
