1 /***************************************************************************//** 2 * \file cyhal_psoc6_04_80_m_csp.h 3 * 4 * \brief 5 * PSoC6_04 device GPIO HAL header for 80-M-CSP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_04_80_M_CSP_H_ 28 #define _CYHAL_PSOC6_04_80_M_CSP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_04_80_m_csp PSoC6_04 80-M-CSP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_04 80-M-CSP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 80-M-CSP package for the PSoC6_04 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 63 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 64 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 65 66 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 67 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 68 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 69 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 70 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 71 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 72 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 73 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 74 75 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 76 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 77 78 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 79 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 80 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 81 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 82 P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 83 84 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 85 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 86 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 87 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 88 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 89 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 90 91 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 92 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 93 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 94 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 95 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 96 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 97 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 98 99 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 100 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 101 102 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 103 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 104 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 105 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 106 P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 107 P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 108 109 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 110 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 111 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 112 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 113 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 114 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 115 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 116 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 117 118 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 119 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 120 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 121 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 122 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 123 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 124 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 125 126 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 127 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 128 129 USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 130 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 131 USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 132 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 133 } cyhal_gpio_psoc6_04_80_m_csp_t; 134 135 /** Create generic name for the series/package specific type. */ 136 typedef cyhal_gpio_psoc6_04_80_m_csp_t cyhal_gpio_t; 137 138 /* Connection type definition */ 139 /** Represents an association between a pin and a resource */ 140 typedef struct 141 { 142 uint8_t block_num; //!< The block number of the resource with this connection 143 uint8_t channel_num; //!< The channel number of the block with this connection 144 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 145 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 146 } cyhal_resource_pin_mapping_t; 147 148 /* Pin connections */ 149 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 150 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 151 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 152 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; 153 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 154 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 155 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 156 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; 157 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 158 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 159 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 160 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 161 /** Indicates that a pin map exists for cpuss_fault_out*/ 162 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 163 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 164 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[2]; 165 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 166 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 167 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 168 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 169 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 170 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 171 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 172 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 173 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 174 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 175 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 176 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 177 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 178 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 179 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 180 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 181 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 182 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 183 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 184 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 185 /** Indicates that a pin map exists for cpuss_trace_clock*/ 186 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 187 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 188 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 189 /** Indicates that a pin map exists for cpuss_trace_data*/ 190 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 191 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 192 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 193 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 194 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 195 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 196 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[2]; 197 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 198 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 199 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 200 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 201 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 202 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 203 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 204 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 205 /** Indicates that a pin map exists for opamp_dsi_ctb_cmp*/ 206 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP (CY_GPIO_DM_STRONG_IN_OFF) 207 /** List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. */ 208 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2]; 209 /** Indicates that a pin map exists for opamp_out_10x*/ 210 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X (CY_GPIO_DM_ANALOG) 211 /** List of valid pin to peripheral connections for the opamp_out_10x signal. */ 212 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2]; 213 /** Indicates that a pin map exists for opamp_vin_m*/ 214 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M (CY_GPIO_DM_ANALOG) 215 /** List of valid pin to peripheral connections for the opamp_vin_m signal. */ 216 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2]; 217 /** Indicates that a pin map exists for opamp_vin_p0*/ 218 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0 (CY_GPIO_DM_ANALOG) 219 /** List of valid pin to peripheral connections for the opamp_vin_p0 signal. */ 220 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2]; 221 /** Indicates that a pin map exists for pass_sarmux_pads*/ 222 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 223 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 224 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[16]; 225 /** Indicates that a pin map exists for peri_tr_io_input*/ 226 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 227 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 228 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24]; 229 /** Indicates that a pin map exists for peri_tr_io_output*/ 230 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 231 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 232 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 233 /** Indicates that a pin map exists for scb_i2c_scl*/ 234 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 235 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 236 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[9]; 237 /** Indicates that a pin map exists for scb_i2c_sda*/ 238 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 239 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 240 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[9]; 241 /** Indicates that a pin map exists for scb_spi_m_clk*/ 242 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 243 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 244 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7]; 245 /** Indicates that a pin map exists for scb_spi_m_miso*/ 246 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 247 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 248 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[8]; 249 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 250 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 251 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 252 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[8]; 253 /** Indicates that a pin map exists for scb_spi_m_select0*/ 254 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 255 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 256 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7]; 257 /** Indicates that a pin map exists for scb_spi_m_select1*/ 258 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 259 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 260 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[6]; 261 /** Indicates that a pin map exists for scb_spi_m_select2*/ 262 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 263 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 264 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6]; 265 /** Indicates that a pin map exists for scb_spi_m_select3*/ 266 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 267 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 268 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3]; 269 /** Indicates that a pin map exists for scb_spi_s_clk*/ 270 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 271 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 272 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7]; 273 /** Indicates that a pin map exists for scb_spi_s_miso*/ 274 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 275 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 276 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[8]; 277 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 278 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 279 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 280 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[8]; 281 /** Indicates that a pin map exists for scb_spi_s_select0*/ 282 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 283 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 284 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7]; 285 /** Indicates that a pin map exists for scb_spi_s_select1*/ 286 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 287 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 288 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[6]; 289 /** Indicates that a pin map exists for scb_spi_s_select2*/ 290 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 291 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 292 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6]; 293 /** Indicates that a pin map exists for scb_spi_s_select3*/ 294 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 295 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 296 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3]; 297 /** Indicates that a pin map exists for scb_uart_cts*/ 298 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 299 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 300 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; 301 /** Indicates that a pin map exists for scb_uart_rts*/ 302 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 303 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 304 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6]; 305 /** Indicates that a pin map exists for scb_uart_rx*/ 306 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 307 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 308 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8]; 309 /** Indicates that a pin map exists for scb_uart_tx*/ 310 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 311 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 312 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8]; 313 /** Indicates that a pin map exists for smif_spi_clk*/ 314 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 315 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 316 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 317 /** Indicates that a pin map exists for smif_spi_data0*/ 318 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 319 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 320 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 321 /** Indicates that a pin map exists for smif_spi_data1*/ 322 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 323 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 324 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 325 /** Indicates that a pin map exists for smif_spi_data2*/ 326 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 327 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 328 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 329 /** Indicates that a pin map exists for smif_spi_data3*/ 330 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 331 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 332 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 333 /** Indicates that a pin map exists for smif_spi_select0*/ 334 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 335 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 336 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 337 /** Indicates that a pin map exists for smif_spi_select1*/ 338 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 339 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 340 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 341 /** Indicates that a pin map exists for smif_spi_select2*/ 342 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 343 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 344 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 345 /** Indicates that a pin map exists for tcpwm_line*/ 346 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 347 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 348 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[53]; 349 /** Indicates that a pin map exists for tcpwm_line_compl*/ 350 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 351 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 352 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[53]; 353 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 354 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 355 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 356 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[62]; 357 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 358 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 359 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 360 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[2]; 361 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 362 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 363 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 364 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[2]; 365 366 #if defined(__cplusplus) 367 } 368 #endif /* __cplusplus */ 369 370 /** \} group_hal_impl_pin_package */ 371 372 #endif /* _CYHAL_PSOC6_04_80_M_CSP_H_ */ 373 374 375 /* [] END OF FILE */ 376
