1 /***************************************************************************//** 2 * \file cyhal_psoc6_01_124_bga_sip.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO HAL header for 124-BGA-SIP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_01_124_BGA_SIP_H_ 28 #define _CYHAL_PSOC6_01_124_BGA_SIP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_01_124_bga_sip PSoC6_01 124-BGA-SIP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_01 124-BGA-SIP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 124-BGA-SIP package for the PSoC6_01 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 63 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 64 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 65 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 66 P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 67 P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 68 69 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 70 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 71 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 72 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 73 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 74 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 75 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 76 P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 77 78 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 79 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 80 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 81 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 82 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 83 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 84 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 85 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 86 87 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 88 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 89 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 90 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 91 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 92 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 93 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 94 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 95 96 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 97 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 98 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 99 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 100 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 101 P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 102 P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 103 P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 104 105 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 106 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 107 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 108 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 109 P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 110 P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 111 P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 112 P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 113 114 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 115 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 116 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 117 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 118 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 119 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 120 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 121 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 122 123 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 124 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 125 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 126 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 127 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 128 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 129 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 130 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 131 132 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 133 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 134 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 135 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 136 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 137 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 138 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 139 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 140 141 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 142 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 143 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 144 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 145 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 146 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 147 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 148 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 149 150 USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 151 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 152 USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 153 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 154 } cyhal_gpio_psoc6_01_124_bga_sip_t; 155 156 /** Create generic name for the series/package specific type. */ 157 typedef cyhal_gpio_psoc6_01_124_bga_sip_t cyhal_gpio_t; 158 159 /* Connection type definition */ 160 /** Represents an association between a pin and a resource */ 161 typedef struct 162 { 163 uint8_t block_num; //!< The block number of the resource with this connection 164 uint8_t channel_num; //!< The channel number of the block with this connection 165 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 166 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 167 } cyhal_resource_pin_mapping_t; 168 169 /* Pin connections */ 170 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 171 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 172 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 173 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; 174 /** Indicates that a pin map exists for audioss_pdm_clk*/ 175 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 176 /** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ 177 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; 178 /** Indicates that a pin map exists for audioss_pdm_data*/ 179 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_DATA (CY_GPIO_DM_HIGHZ) 180 /** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ 181 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; 182 /** Indicates that a pin map exists for audioss_rx_sck*/ 183 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 184 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 185 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; 186 /** Indicates that a pin map exists for audioss_rx_sdi*/ 187 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 188 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 189 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; 190 /** Indicates that a pin map exists for audioss_rx_ws*/ 191 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 192 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 193 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; 194 /** Indicates that a pin map exists for audioss_tx_sck*/ 195 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 196 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 197 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; 198 /** Indicates that a pin map exists for audioss_tx_sdo*/ 199 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 200 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 201 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; 202 /** Indicates that a pin map exists for audioss_tx_ws*/ 203 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 204 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 205 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; 206 /** Indicates that a pin map exists for bless_ext_lna_rx_ctl_out*/ 207 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_LNA_RX_CTL_OUT (CY_GPIO_DM_STRONG_IN_OFF) 208 /** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ 209 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; 210 /** Indicates that a pin map exists for bless_ext_pa_lna_chip_en_out*/ 211 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_PA_LNA_CHIP_EN_OUT (CY_GPIO_DM_STRONG_IN_OFF) 212 /** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ 213 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; 214 /** Indicates that a pin map exists for bless_ext_pa_tx_ctl_out*/ 215 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_PA_TX_CTL_OUT (CY_GPIO_DM_STRONG_IN_OFF) 216 /** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ 217 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; 218 /** Indicates that a pin map exists for bless_mxd_act_bpktctl*/ 219 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_BPKTCTL (CY_GPIO_DM_STRONG_IN_OFF) 220 /** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ 221 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; 222 /** Indicates that a pin map exists for bless_mxd_act_dbus_rx_en*/ 223 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_DBUS_RX_EN (CY_GPIO_DM_STRONG_IN_OFF) 224 /** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ 225 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; 226 /** Indicates that a pin map exists for bless_mxd_act_dbus_tx_en*/ 227 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_DBUS_TX_EN (CY_GPIO_DM_STRONG_IN_OFF) 228 /** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ 229 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; 230 /** Indicates that a pin map exists for bless_mxd_act_txd_rxd*/ 231 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_TXD_RXD (CY_GPIO_DM_STRONG_IN_OFF) 232 /** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ 233 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; 234 /** Indicates that a pin map exists for bless_mxd_dpslp_act_ldo_en*/ 235 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_ACT_LDO_EN (CY_GPIO_DM_STRONG_IN_OFF) 236 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ 237 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; 238 /** Indicates that a pin map exists for bless_mxd_dpslp_buck_en*/ 239 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_BUCK_EN (CY_GPIO_DM_STRONG_IN_OFF) 240 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ 241 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; 242 /** Indicates that a pin map exists for bless_mxd_dpslp_clk_en*/ 243 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_CLK_EN (CY_GPIO_DM_STRONG_IN_OFF) 244 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ 245 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; 246 /** Indicates that a pin map exists for bless_mxd_dpslp_dig_ldo_en*/ 247 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_DIG_LDO_EN (CY_GPIO_DM_STRONG_IN_OFF) 248 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ 249 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; 250 /** Indicates that a pin map exists for bless_mxd_dpslp_isolate_n*/ 251 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_ISOLATE_N (CY_GPIO_DM_STRONG_IN_OFF) 252 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ 253 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; 254 /** Indicates that a pin map exists for bless_mxd_dpslp_mxd_clk_out*/ 255 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_MXD_CLK_OUT (CY_GPIO_DM_HIGHZ) 256 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ 257 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; 258 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_clk*/ 259 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_CLK (CY_GPIO_DM_STRONG_IN_OFF) 260 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ 261 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; 262 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_data*/ 263 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_DATA (CY_GPIO_DM_STRONG_IN_OFF) 264 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ 265 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; 266 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_le*/ 267 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_LE (CY_GPIO_DM_STRONG_IN_OFF) 268 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ 269 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; 270 /** Indicates that a pin map exists for bless_mxd_dpslp_reset_n*/ 271 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RESET_N (CY_GPIO_DM_STRONG_IN_OFF) 272 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ 273 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; 274 /** Indicates that a pin map exists for bless_mxd_dpslp_ret_ldo_ol_hv*/ 275 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RET_LDO_OL_HV (CY_GPIO_DM_STRONG_IN_OFF) 276 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ 277 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; 278 /** Indicates that a pin map exists for bless_mxd_dpslp_ret_switch_hv*/ 279 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RET_SWITCH_HV (CY_GPIO_DM_STRONG_IN_OFF) 280 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ 281 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; 282 /** Indicates that a pin map exists for bless_mxd_dpslp_xtal_en*/ 283 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_XTAL_EN (CY_GPIO_DM_STRONG_IN_OFF) 284 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ 285 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; 286 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 287 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 288 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 289 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 290 /** Indicates that a pin map exists for cpuss_fault_out*/ 291 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 292 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 293 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[2]; 294 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 295 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 296 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 297 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 298 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 299 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 300 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 301 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 302 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 303 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 304 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 305 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 306 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 307 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 308 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 309 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 310 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 311 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 312 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 313 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 314 /** Indicates that a pin map exists for cpuss_trace_clock*/ 315 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 316 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 317 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 318 /** Indicates that a pin map exists for cpuss_trace_data*/ 319 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 320 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 321 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[12]; 322 /** Indicates that a pin map exists for dac_ctdac_voutsw*/ 323 #define CYHAL_PIN_MAP_DRIVE_MODE_DAC_CTDAC_VOUTSW (CY_GPIO_DM_ANALOG) 324 /** List of valid pin to peripheral connections for the dac_ctdac_voutsw signal. */ 325 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_dac_ctdac_voutsw[1]; 326 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 327 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 328 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 329 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[2]; 330 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 331 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 332 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 333 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 334 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 335 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 336 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 337 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 338 /** Indicates that a pin map exists for opamp_dsi_ctb_cmp*/ 339 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP (CY_GPIO_DM_STRONG_IN_OFF) 340 /** List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. */ 341 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2]; 342 /** Indicates that a pin map exists for opamp_out_10x*/ 343 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X (CY_GPIO_DM_ANALOG) 344 /** List of valid pin to peripheral connections for the opamp_out_10x signal. */ 345 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2]; 346 /** Indicates that a pin map exists for opamp_vin_m*/ 347 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M (CY_GPIO_DM_ANALOG) 348 /** List of valid pin to peripheral connections for the opamp_vin_m signal. */ 349 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2]; 350 /** Indicates that a pin map exists for opamp_vin_p0*/ 351 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0 (CY_GPIO_DM_ANALOG) 352 /** List of valid pin to peripheral connections for the opamp_vin_p0 signal. */ 353 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2]; 354 /** Indicates that a pin map exists for opamp_vin_p1*/ 355 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P1 (CY_GPIO_DM_ANALOG) 356 /** List of valid pin to peripheral connections for the opamp_vin_p1 signal. */ 357 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2]; 358 /** Indicates that a pin map exists for pass_sarmux_pads*/ 359 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 360 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 361 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; 362 /** Indicates that a pin map exists for peri_tr_io_input*/ 363 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 364 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 365 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22]; 366 /** Indicates that a pin map exists for peri_tr_io_output*/ 367 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 368 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 369 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 370 /** Indicates that a pin map exists for scb_i2c_scl*/ 371 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 372 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 373 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; 374 /** Indicates that a pin map exists for scb_i2c_sda*/ 375 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 376 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 377 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; 378 /** Indicates that a pin map exists for scb_spi_m_clk*/ 379 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 380 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 381 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14]; 382 /** Indicates that a pin map exists for scb_spi_m_miso*/ 383 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 384 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 385 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; 386 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 387 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 388 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 389 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; 390 /** Indicates that a pin map exists for scb_spi_m_select0*/ 391 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 392 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 393 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14]; 394 /** Indicates that a pin map exists for scb_spi_m_select1*/ 395 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 396 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 397 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11]; 398 /** Indicates that a pin map exists for scb_spi_m_select2*/ 399 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 400 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 401 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11]; 402 /** Indicates that a pin map exists for scb_spi_m_select3*/ 403 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 404 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 405 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[9]; 406 /** Indicates that a pin map exists for scb_spi_s_clk*/ 407 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 408 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 409 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14]; 410 /** Indicates that a pin map exists for scb_spi_s_miso*/ 411 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 412 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 413 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; 414 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 415 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 416 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 417 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; 418 /** Indicates that a pin map exists for scb_spi_s_select0*/ 419 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 420 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 421 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14]; 422 /** Indicates that a pin map exists for scb_spi_s_select1*/ 423 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 424 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 425 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11]; 426 /** Indicates that a pin map exists for scb_spi_s_select2*/ 427 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 428 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 429 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11]; 430 /** Indicates that a pin map exists for scb_spi_s_select3*/ 431 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 432 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 433 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[9]; 434 /** Indicates that a pin map exists for scb_uart_cts*/ 435 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 436 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 437 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[12]; 438 /** Indicates that a pin map exists for scb_uart_rts*/ 439 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 440 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 441 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12]; 442 /** Indicates that a pin map exists for scb_uart_rx*/ 443 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 444 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 445 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; 446 /** Indicates that a pin map exists for scb_uart_tx*/ 447 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 448 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 449 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; 450 /** Indicates that a pin map exists for smif_spi_clk*/ 451 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 452 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 453 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 454 /** Indicates that a pin map exists for smif_spi_data0*/ 455 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 456 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 457 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 458 /** Indicates that a pin map exists for smif_spi_data1*/ 459 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 460 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 461 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 462 /** Indicates that a pin map exists for smif_spi_data2*/ 463 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 464 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 465 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 466 /** Indicates that a pin map exists for smif_spi_data3*/ 467 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 468 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 469 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 470 /** Indicates that a pin map exists for smif_spi_data4*/ 471 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 472 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 473 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 474 /** Indicates that a pin map exists for smif_spi_data5*/ 475 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 476 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 477 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 478 /** Indicates that a pin map exists for smif_spi_data6*/ 479 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 480 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 481 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 482 /** Indicates that a pin map exists for smif_spi_data7*/ 483 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 484 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 485 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 486 /** Indicates that a pin map exists for smif_spi_select0*/ 487 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 488 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 489 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 490 /** Indicates that a pin map exists for smif_spi_select1*/ 491 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 492 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 493 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 494 /** Indicates that a pin map exists for smif_spi_select2*/ 495 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 496 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 497 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 498 /** Indicates that a pin map exists for smif_spi_select3*/ 499 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 500 /** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ 501 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; 502 /** Indicates that a pin map exists for tcpwm_line*/ 503 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 504 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 505 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[82]; 506 /** Indicates that a pin map exists for tcpwm_line_compl*/ 507 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 508 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 509 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82]; 510 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 511 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 512 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 513 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[2]; 514 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 515 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 516 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 517 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[2]; 518 519 #if defined(__cplusplus) 520 } 521 #endif /* __cplusplus */ 522 523 /** \} group_hal_impl_pin_package */ 524 525 #endif /* _CYHAL_PSOC6_01_124_BGA_SIP_H_ */ 526 527 528 /* [] END OF FILE */ 529
