1 /***************************************************************************//** 2 * \file cyhal_cyw20829_77_bga.c 3 * 4 * \brief 5 * CYW20829 device GPIO HAL header for 77-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_CYW20829_77_BGA_H_) 31 #include "pin_packages/cyhal_cyw20829_77_bga.h" 32 33 /* Pin connections */ 34 /* Connections for: adcmic_clk_pdm */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_clk_pdm[2] = { 36 {0u, 0u, P3_2, P3_2_ADCMIC_CLK_PDM}, 37 {0u, 0u, P5_0, P5_0_ADCMIC_CLK_PDM}, 38 }; 39 40 /* Connections for: adcmic_gpio_adc_in */ 41 /* The actual channel_num will always be 0 for the ADCMIC. However, the ADC driver does need to 42 know the bit index on the analog_in signal. So store that in the channel_num field instead. */ 43 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_gpio_adc_in[8] = { 44 {0u, 0u, P3_0, HSIOM_SEL_GPIO}, 45 {0u, 1u, P3_1, HSIOM_SEL_GPIO}, 46 {0u, 2u, P3_2, HSIOM_SEL_GPIO}, 47 {0u, 3u, P3_3, HSIOM_SEL_GPIO}, 48 {0u, 4u, P3_4, HSIOM_SEL_GPIO}, 49 {0u, 5u, P3_5, HSIOM_SEL_GPIO}, 50 {0u, 6u, P3_6, HSIOM_SEL_GPIO}, 51 {0u, 7u, P3_7, HSIOM_SEL_GPIO}, 52 }; 53 54 /* Connections for: adcmic_pdm_data */ 55 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_pdm_data[2] = { 56 {0u, 0u, P3_3, P3_3_ADCMIC_PDM_DATA}, 57 {0u, 0u, P5_1, P5_1_ADCMIC_PDM_DATA}, 58 }; 59 60 /* Connections for: canfd_ttcan_rx */ 61 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[2] = { 62 {0u, 0u, P3_2, P3_2_CANFD0_TTCAN_RX0}, 63 {0u, 0u, P5_0, P5_0_CANFD0_TTCAN_RX0}, 64 }; 65 66 /* Connections for: canfd_ttcan_tx */ 67 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[2] = { 68 {0u, 0u, P3_3, P3_3_CANFD0_TTCAN_TX0}, 69 {0u, 0u, P5_1, P5_1_CANFD0_TTCAN_TX0}, 70 }; 71 72 /* Connections for: cpuss_clk_swj_swclk_tclk */ 73 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_swj_swclk_tclk[1] = { 74 {0u, 0u, P1_3, P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK}, 75 }; 76 77 /* Connections for: cpuss_rst_swj_trstn */ 78 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_rst_swj_trstn[1] = { 79 {0u, 0u, P3_1, P3_1_CPUSS_RST_SWJ_TRSTN}, 80 }; 81 82 /* Connections for: cpuss_swj_swdio_tms */ 83 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 84 {0u, 0u, P1_2, P1_2_CPUSS_SWJ_SWDIO_TMS}, 85 }; 86 87 /* Connections for: cpuss_swj_swdoe_tdi */ 88 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 89 {0u, 0u, P1_1, P1_1_CPUSS_SWJ_SWDOE_TDI}, 90 }; 91 92 /* Connections for: cpuss_swj_swo_tdo */ 93 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 94 {0u, 0u, P1_0, P1_0_CPUSS_SWJ_SWO_TDO}, 95 }; 96 97 /* Connections for: cpuss_trace_clock */ 98 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 99 {0u, 0u, P1_2, P1_2_CPUSS_TRACE_CLOCK}, 100 {0u, 0u, P3_4, P3_4_CPUSS_TRACE_CLOCK}, 101 }; 102 103 /* Connections for: cpuss_trace_data */ 104 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 105 {0u, 3u, P0_4, P0_4_CPUSS_TRACE_DATA3}, 106 {0u, 2u, P0_5, P0_5_CPUSS_TRACE_DATA2}, 107 {0u, 1u, P1_0, P1_0_CPUSS_TRACE_DATA1}, 108 {0u, 0u, P1_1, P1_1_CPUSS_TRACE_DATA0}, 109 {0u, 3u, P3_0, P3_0_CPUSS_TRACE_DATA3}, 110 {0u, 2u, P3_1, P3_1_CPUSS_TRACE_DATA2}, 111 {0u, 1u, P3_2, P3_2_CPUSS_TRACE_DATA1}, 112 {0u, 0u, P3_3, P3_3_CPUSS_TRACE_DATA0}, 113 }; 114 115 /* Connections for: keyscan_ks_col */ 116 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 117 the bit index on the row/column signal in order to check that the indices are contiguous and 118 start at 0. Store that in the channel_num field instead. */ 119 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_col[20] = { 120 {0u, 3u, P0_0, P0_0_KEYSCAN_KS_COL3}, 121 {0u, 4u, P0_1, P0_1_KEYSCAN_KS_COL4}, 122 {0u, 11u, P0_2, P0_2_KEYSCAN_KS_COL11}, 123 {0u, 12u, P0_3, P0_3_KEYSCAN_KS_COL12}, 124 {0u, 17u, P1_2, P1_2_KEYSCAN_KS_COL17}, 125 {0u, 16u, P1_3, P1_3_KEYSCAN_KS_COL16}, 126 {0u, 15u, P1_4, P1_4_KEYSCAN_KS_COL15}, 127 {0u, 16u, P1_4, P1_4_KEYSCAN_KS_COL16}, 128 {0u, 5u, P1_5, P1_5_KEYSCAN_KS_COL5}, 129 {0u, 6u, P1_6, P1_6_KEYSCAN_KS_COL6}, 130 {0u, 13u, P3_2, P3_2_KEYSCAN_KS_COL13}, 131 {0u, 14u, P3_3, P3_3_KEYSCAN_KS_COL14}, 132 {0u, 17u, P3_3, P3_3_KEYSCAN_KS_COL17}, 133 {0u, 7u, P3_4, P3_4_KEYSCAN_KS_COL7}, 134 {0u, 8u, P3_5, P3_5_KEYSCAN_KS_COL8}, 135 {0u, 9u, P3_6, P3_6_KEYSCAN_KS_COL9}, 136 {0u, 10u, P3_7, P3_7_KEYSCAN_KS_COL10}, 137 {0u, 0u, P5_0, P5_0_KEYSCAN_KS_COL0}, 138 {0u, 1u, P5_1, P5_1_KEYSCAN_KS_COL1}, 139 {0u, 2u, P5_2, P5_2_KEYSCAN_KS_COL2}, 140 }; 141 142 /* Connections for: keyscan_ks_row */ 143 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 144 the bit index on the row/column signal in order to check that the indices are contiguous and 145 start at 0. Store that in the channel_num field instead. */ 146 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_row[8] = { 147 {0u, 0u, P0_4, P0_4_KEYSCAN_KS_ROW0}, 148 {0u, 1u, P0_5, P0_5_KEYSCAN_KS_ROW1}, 149 {0u, 5u, P1_0, P1_0_KEYSCAN_KS_ROW5}, 150 {0u, 6u, P1_1, P1_1_KEYSCAN_KS_ROW6}, 151 {0u, 7u, P3_0, P3_0_KEYSCAN_KS_ROW7}, 152 {0u, 4u, P3_1, P3_1_KEYSCAN_KS_ROW4}, 153 {0u, 2u, P4_0, P4_0_KEYSCAN_KS_ROW2}, 154 {0u, 3u, P4_1, P4_1_KEYSCAN_KS_ROW3}, 155 }; 156 157 /* Connections for: lin_lin_en */ 158 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[2] = { 159 {0u, 1u, P1_4, P1_4_LIN0_LIN_EN1}, 160 {0u, 0u, P3_1, P3_1_LIN0_LIN_EN0}, 161 }; 162 163 /* Connections for: lin_lin_rx */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[2] = { 165 {0u, 1u, P1_5, P1_5_LIN0_LIN_RX1}, 166 {0u, 0u, P3_2, P3_2_LIN0_LIN_RX0}, 167 }; 168 169 /* Connections for: lin_lin_tx */ 170 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[2] = { 171 {0u, 1u, P1_6, P1_6_LIN0_LIN_TX1}, 172 {0u, 0u, P3_3, P3_3_LIN0_LIN_TX0}, 173 }; 174 175 /* Connections for: pdm_pdm_clk */ 176 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[4] = { 177 {0u, 1u, P0_0, P0_0_PDM_PDM_CLK1}, 178 {0u, 1u, P1_0, P1_0_PDM_PDM_CLK1}, 179 {0u, 0u, P3_2, P3_2_PDM_PDM_CLK0}, 180 {0u, 0u, P5_0, P5_0_PDM_PDM_CLK0}, 181 }; 182 183 /* Connections for: pdm_pdm_data */ 184 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[4] = { 185 {0u, 1u, P0_1, P0_1_PDM_PDM_DATA1}, 186 {0u, 1u, P1_1, P1_1_PDM_PDM_DATA1}, 187 {0u, 0u, P3_3, P3_3_PDM_PDM_DATA0}, 188 {0u, 0u, P5_1, P5_1_PDM_PDM_DATA0}, 189 }; 190 191 /* Connections for: peri_tr_io_input */ 192 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 193 to know the index of the input or output trigger line. Store that in the channel_num field 194 instead. */ 195 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8] = { 196 {0u, 4u, P0_2, P0_2_PERI_TR_IO_INPUT4}, 197 {0u, 5u, P0_3, P0_3_PERI_TR_IO_INPUT5}, 198 {0u, 0u, P0_4, P0_4_PERI_TR_IO_INPUT0}, 199 {0u, 1u, P0_5, P0_5_PERI_TR_IO_INPUT1}, 200 {0u, 2u, P1_2, P1_2_PERI_TR_IO_INPUT2}, 201 {0u, 3u, P1_3, P1_3_PERI_TR_IO_INPUT3}, 202 {0u, 6u, P3_2, P3_2_PERI_TR_IO_INPUT6}, 203 {0u, 7u, P3_3, P3_3_PERI_TR_IO_INPUT7}, 204 }; 205 206 /* Connections for: peri_tr_io_output */ 207 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 208 to know the index of the input or output trigger line. Store that in the channel_num field 209 instead. */ 210 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 211 {0u, 0u, P1_0, P1_0_PERI_TR_IO_OUTPUT0}, 212 {0u, 1u, P1_1, P1_1_PERI_TR_IO_OUTPUT1}, 213 }; 214 215 /* Connections for: scb_i2c_scl */ 216 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5] = { 217 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 218 {2u, 0u, P1_2, P1_2_SCB2_I2C_SCL}, 219 {2u, 0u, P3_2, P3_2_SCB2_I2C_SCL}, 220 {0u, 0u, P4_0, P4_0_SCB0_I2C_SCL}, 221 {2u, 0u, P5_0, P5_0_SCB2_I2C_SCL}, 222 }; 223 224 /* Connections for: scb_i2c_sda */ 225 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[5] = { 226 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 227 {2u, 0u, P1_3, P1_3_SCB2_I2C_SDA}, 228 {2u, 0u, P3_3, P3_3_SCB2_I2C_SDA}, 229 {0u, 0u, P4_1, P4_1_SCB0_I2C_SDA}, 230 {2u, 0u, P5_1, P5_1_SCB2_I2C_SDA}, 231 }; 232 233 /* Connections for: scb_spi_m_clk */ 234 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[3] = { 235 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 236 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 237 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 238 }; 239 240 /* Connections for: scb_spi_m_miso */ 241 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[4] = { 242 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO}, 243 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 244 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 245 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 246 }; 247 248 /* Connections for: scb_spi_m_mosi */ 249 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[4] = { 250 {0u, 0u, P0_2, P0_2_SCB0_SPI_MOSI}, 251 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 252 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 253 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 254 }; 255 256 /* Connections for: scb_spi_m_select0 */ 257 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[4] = { 258 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 259 {1u, 0u, P3_0, P3_0_SCB1_SPI_SELECT0}, 260 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 261 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 262 }; 263 264 /* Connections for: scb_spi_m_select1 */ 265 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[3] = { 266 {0u, 0u, P0_0, P0_0_SCB0_SPI_SELECT1}, 267 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 268 {1u, 0u, P3_6, P3_6_SCB1_SPI_SELECT1}, 269 }; 270 271 /* Connections for: scb_spi_m_select2 */ 272 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3] = { 273 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2}, 274 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 275 {1u, 0u, P3_5, P3_5_SCB1_SPI_SELECT2}, 276 }; 277 278 /* Connections for: scb_spi_m_select3 */ 279 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2] = { 280 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3}, 281 {1u, 0u, P3_4, P3_4_SCB1_SPI_SELECT3}, 282 }; 283 284 /* Connections for: scb_spi_s_clk */ 285 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[3] = { 286 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 287 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 288 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 289 }; 290 291 /* Connections for: scb_spi_s_miso */ 292 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[4] = { 293 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO}, 294 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 295 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 296 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 297 }; 298 299 /* Connections for: scb_spi_s_mosi */ 300 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[4] = { 301 {0u, 0u, P0_2, P0_2_SCB0_SPI_MOSI}, 302 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 303 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 304 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 305 }; 306 307 /* Connections for: scb_spi_s_select0 */ 308 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[4] = { 309 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 310 {1u, 0u, P3_0, P3_0_SCB1_SPI_SELECT0}, 311 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 312 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 313 }; 314 315 /* Connections for: scb_spi_s_select1 */ 316 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[3] = { 317 {0u, 0u, P0_0, P0_0_SCB0_SPI_SELECT1}, 318 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 319 {1u, 0u, P3_6, P3_6_SCB1_SPI_SELECT1}, 320 }; 321 322 /* Connections for: scb_spi_s_select2 */ 323 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3] = { 324 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2}, 325 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 326 {1u, 0u, P3_5, P3_5_SCB1_SPI_SELECT2}, 327 }; 328 329 /* Connections for: scb_spi_s_select3 */ 330 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2] = { 331 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3}, 332 {1u, 0u, P3_4, P3_4_SCB1_SPI_SELECT3}, 333 }; 334 335 /* Connections for: scb_uart_cts */ 336 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[4] = { 337 {1u, 0u, P1_0, P1_0_SCB1_UART_CTS}, 338 {2u, 0u, P3_0, P3_0_SCB2_UART_CTS}, 339 {2u, 0u, P4_0, P4_0_SCB2_UART_CTS}, 340 {2u, 0u, P5_0, P5_0_SCB2_UART_CTS}, 341 }; 342 343 /* Connections for: scb_uart_rts */ 344 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[2] = { 345 {1u, 0u, P1_1, P1_1_SCB1_UART_RTS}, 346 {2u, 0u, P3_1, P3_1_SCB2_UART_RTS}, 347 }; 348 349 /* Connections for: scb_uart_rx */ 350 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[2] = { 351 {1u, 0u, P1_2, P1_2_SCB1_UART_RX}, 352 {2u, 0u, P3_2, P3_2_SCB2_UART_RX}, 353 }; 354 355 /* Connections for: scb_uart_tx */ 356 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[2] = { 357 {1u, 0u, P1_3, P1_3_SCB1_UART_TX}, 358 {2u, 0u, P3_3, P3_3_SCB2_UART_TX}, 359 }; 360 361 /* Connections for: smif_spi_clk */ 362 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 363 {0u, 0u, P2_5, P2_5_SMIF_SPIHB_CLK}, 364 }; 365 366 /* Connections for: smif_spi_data0 */ 367 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 368 {0u, 0u, P2_4, P2_4_SMIF_SPIHB_DATA0}, 369 }; 370 371 /* Connections for: smif_spi_data1 */ 372 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 373 {0u, 0u, P2_3, P2_3_SMIF_SPIHB_DATA1}, 374 }; 375 376 /* Connections for: smif_spi_data2 */ 377 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 378 {0u, 0u, P2_2, P2_2_SMIF_SPIHB_DATA2}, 379 }; 380 381 /* Connections for: smif_spi_data3 */ 382 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 383 {0u, 0u, P2_1, P2_1_SMIF_SPIHB_DATA3}, 384 }; 385 386 /* Connections for: smif_spi_select0 */ 387 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 388 {0u, 0u, P2_0, P2_0_SMIF_SPIHB_SELECT0}, 389 }; 390 391 /* Connections for: smif_spi_select1 */ 392 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 393 {0u, 0u, P0_5, P0_5_SMIF_SPIHB_SELECT1}, 394 }; 395 396 /* Connections for: tcpwm_line */ 397 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[26] = { 398 {0u, 1u, P0_1, P0_1_TCPWM0_LINE1}, 399 {1u, 0u, P0_1, P0_1_TCPWM0_LINE256}, 400 {0u, 0u, P0_3, P0_3_TCPWM0_LINE0}, 401 {1u, 1u, P0_3, P0_3_TCPWM0_LINE257}, 402 {0u, 1u, P0_5, P0_5_TCPWM0_LINE1}, 403 {1u, 2u, P0_5, P0_5_TCPWM0_LINE258}, 404 {0u, 0u, P1_1, P1_1_TCPWM0_LINE0}, 405 {1u, 3u, P1_1, P1_1_TCPWM0_LINE259}, 406 {0u, 1u, P1_3, P1_3_TCPWM0_LINE1}, 407 {1u, 4u, P1_3, P1_3_TCPWM0_LINE260}, 408 {0u, 0u, P1_5, P1_5_TCPWM0_LINE0}, 409 {1u, 5u, P1_5, P1_5_TCPWM0_LINE261}, 410 {0u, 0u, P3_0, P3_0_TCPWM0_LINE0}, 411 {1u, 0u, P3_0, P3_0_TCPWM0_LINE256}, 412 {0u, 1u, P3_2, P3_2_TCPWM0_LINE1}, 413 {1u, 1u, P3_2, P3_2_TCPWM0_LINE257}, 414 {0u, 0u, P3_4, P3_4_TCPWM0_LINE0}, 415 {1u, 2u, P3_4, P3_4_TCPWM0_LINE258}, 416 {0u, 1u, P3_6, P3_6_TCPWM0_LINE1}, 417 {1u, 3u, P3_6, P3_6_TCPWM0_LINE259}, 418 {0u, 0u, P4_1, P4_1_TCPWM0_LINE0}, 419 {1u, 6u, P4_1, P4_1_TCPWM0_LINE262}, 420 {0u, 0u, P5_0, P5_0_TCPWM0_LINE0}, 421 {1u, 4u, P5_0, P5_0_TCPWM0_LINE260}, 422 {0u, 1u, P5_2, P5_2_TCPWM0_LINE1}, 423 {1u, 5u, P5_2, P5_2_TCPWM0_LINE261}, 424 }; 425 426 /* Connections for: tcpwm_line_compl */ 427 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[26] = { 428 {0u, 0u, P0_0, P0_0_TCPWM0_LINE_COMPL0}, 429 {1u, 6u, P0_0, P0_0_TCPWM0_LINE_COMPL262}, 430 {0u, 1u, P0_2, P0_2_TCPWM0_LINE_COMPL1}, 431 {1u, 0u, P0_2, P0_2_TCPWM0_LINE_COMPL256}, 432 {0u, 0u, P0_4, P0_4_TCPWM0_LINE_COMPL0}, 433 {1u, 1u, P0_4, P0_4_TCPWM0_LINE_COMPL257}, 434 {0u, 1u, P1_0, P1_0_TCPWM0_LINE_COMPL1}, 435 {1u, 2u, P1_0, P1_0_TCPWM0_LINE_COMPL258}, 436 {0u, 0u, P1_2, P1_2_TCPWM0_LINE_COMPL0}, 437 {1u, 3u, P1_2, P1_2_TCPWM0_LINE_COMPL259}, 438 {0u, 1u, P1_4, P1_4_TCPWM0_LINE_COMPL1}, 439 {1u, 4u, P1_4, P1_4_TCPWM0_LINE_COMPL260}, 440 {0u, 0u, P1_6, P1_6_TCPWM0_LINE_COMPL0}, 441 {1u, 5u, P1_6, P1_6_TCPWM0_LINE_COMPL261}, 442 {0u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL0}, 443 {1u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL256}, 444 {0u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL1}, 445 {1u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL257}, 446 {0u, 0u, P3_5, P3_5_TCPWM0_LINE_COMPL0}, 447 {1u, 2u, P3_5, P3_5_TCPWM0_LINE_COMPL258}, 448 {0u, 1u, P3_7, P3_7_TCPWM0_LINE_COMPL1}, 449 {1u, 3u, P3_7, P3_7_TCPWM0_LINE_COMPL259}, 450 {0u, 1u, P4_0, P4_0_TCPWM0_LINE_COMPL1}, 451 {1u, 5u, P4_0, P4_0_TCPWM0_LINE_COMPL261}, 452 {0u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL0}, 453 {1u, 4u, P5_1, P5_1_TCPWM0_LINE_COMPL260}, 454 }; 455 456 /* Connections for: tdm_tdm_rx_fsync */ 457 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[1] = { 458 {0u, 0u, P0_2, P0_2_TDM_TDM_RX_FSYNC0}, 459 }; 460 461 /* Connections for: tdm_tdm_rx_mck */ 462 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1] = { 463 {0u, 0u, P0_0, P0_0_TDM_TDM_RX_MCK0}, 464 }; 465 466 /* Connections for: tdm_tdm_rx_sck */ 467 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1] = { 468 {0u, 0u, P0_1, P0_1_TDM_TDM_RX_SCK0}, 469 }; 470 471 /* Connections for: tdm_tdm_rx_sd */ 472 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[1] = { 473 {0u, 0u, P0_3, P0_3_TDM_TDM_RX_SD0}, 474 }; 475 476 /* Connections for: tdm_tdm_tx_fsync */ 477 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[1] = { 478 {0u, 0u, P1_0, P1_0_TDM_TDM_TX_FSYNC0}, 479 }; 480 481 /* Connections for: tdm_tdm_tx_mck */ 482 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[1] = { 483 {0u, 0u, P0_4, P0_4_TDM_TDM_TX_MCK0}, 484 }; 485 486 /* Connections for: tdm_tdm_tx_sck */ 487 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[1] = { 488 {0u, 0u, P0_5, P0_5_TDM_TDM_TX_SCK0}, 489 }; 490 491 /* Connections for: tdm_tdm_tx_sd */ 492 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[1] = { 493 {0u, 0u, P1_1, P1_1_TDM_TDM_TX_SD0}, 494 }; 495 496 #endif 497
