1 /***************************************************************************//** 2 * \file cyhal_cyw20829_40_qfn.c 3 * 4 * \brief 5 * CYW20829 device GPIO HAL header for 40-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_CYW20829_40_QFN_H_) 31 #include "pin_packages/cyhal_cyw20829_40_qfn.h" 32 33 /* Pin connections */ 34 /* Connections for: adcmic_clk_pdm */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_clk_pdm[2] = { 36 {0u, 0u, P3_2, P3_2_ADCMIC_CLK_PDM}, 37 {0u, 0u, P5_0, P5_0_ADCMIC_CLK_PDM}, 38 }; 39 40 /* Connections for: adcmic_gpio_adc_in */ 41 /* The actual channel_num will always be 0 for the ADCMIC. However, the ADC driver does need to 42 know the bit index on the analog_in signal. So store that in the channel_num field instead. */ 43 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_gpio_adc_in[3] = { 44 {0u, 1u, P3_1, HSIOM_SEL_GPIO}, 45 {0u, 2u, P3_2, HSIOM_SEL_GPIO}, 46 {0u, 3u, P3_3, HSIOM_SEL_GPIO}, 47 }; 48 49 /* Connections for: adcmic_pdm_data */ 50 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_pdm_data[2] = { 51 {0u, 0u, P3_3, P3_3_ADCMIC_PDM_DATA}, 52 {0u, 0u, P5_1, P5_1_ADCMIC_PDM_DATA}, 53 }; 54 55 /* Connections for: canfd_ttcan_rx */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[2] = { 57 {0u, 0u, P3_2, P3_2_CANFD0_TTCAN_RX0}, 58 {0u, 0u, P5_0, P5_0_CANFD0_TTCAN_RX0}, 59 }; 60 61 /* Connections for: canfd_ttcan_tx */ 62 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[2] = { 63 {0u, 0u, P3_3, P3_3_CANFD0_TTCAN_TX0}, 64 {0u, 0u, P5_1, P5_1_CANFD0_TTCAN_TX0}, 65 }; 66 67 /* Connections for: cpuss_clk_swj_swclk_tclk */ 68 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_swj_swclk_tclk[1] = { 69 {0u, 0u, P1_3, P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK}, 70 }; 71 72 /* Connections for: cpuss_rst_swj_trstn */ 73 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_rst_swj_trstn[1] = { 74 {0u, 0u, P3_1, P3_1_CPUSS_RST_SWJ_TRSTN}, 75 }; 76 77 /* Connections for: cpuss_swj_swdio_tms */ 78 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 79 {0u, 0u, P1_2, P1_2_CPUSS_SWJ_SWDIO_TMS}, 80 }; 81 82 /* Connections for: cpuss_swj_swdoe_tdi */ 83 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 84 {0u, 0u, P1_1, P1_1_CPUSS_SWJ_SWDOE_TDI}, 85 }; 86 87 /* Connections for: cpuss_swj_swo_tdo */ 88 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 89 {0u, 0u, P1_0, P1_0_CPUSS_SWJ_SWO_TDO}, 90 }; 91 92 /* Connections for: cpuss_trace_clock */ 93 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 94 {0u, 0u, P1_2, P1_2_CPUSS_TRACE_CLOCK}, 95 }; 96 97 /* Connections for: cpuss_trace_data */ 98 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[7] = { 99 {0u, 3u, P0_4, P0_4_CPUSS_TRACE_DATA3}, 100 {0u, 2u, P0_5, P0_5_CPUSS_TRACE_DATA2}, 101 {0u, 1u, P1_0, P1_0_CPUSS_TRACE_DATA1}, 102 {0u, 0u, P1_1, P1_1_CPUSS_TRACE_DATA0}, 103 {0u, 2u, P3_1, P3_1_CPUSS_TRACE_DATA2}, 104 {0u, 1u, P3_2, P3_2_CPUSS_TRACE_DATA1}, 105 {0u, 0u, P3_3, P3_3_CPUSS_TRACE_DATA0}, 106 }; 107 108 /* Connections for: keyscan_ks_col */ 109 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 110 the bit index on the row/column signal in order to check that the indices are contiguous and 111 start at 0. Store that in the channel_num field instead. */ 112 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_col[2] = { 113 {0u, 0u, P5_0, P5_0_KEYSCAN_KS_COL0}, 114 {0u, 1u, P5_1, P5_1_KEYSCAN_KS_COL1}, 115 }; 116 117 /* Connections for: keyscan_ks_row */ 118 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 119 the bit index on the row/column signal in order to check that the indices are contiguous and 120 start at 0. Store that in the channel_num field instead. */ 121 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_row[7] = { 122 {0u, 0u, P0_4, P0_4_KEYSCAN_KS_ROW0}, 123 {0u, 1u, P0_5, P0_5_KEYSCAN_KS_ROW1}, 124 {0u, 5u, P1_0, P1_0_KEYSCAN_KS_ROW5}, 125 {0u, 6u, P1_1, P1_1_KEYSCAN_KS_ROW6}, 126 {0u, 4u, P3_1, P3_1_KEYSCAN_KS_ROW4}, 127 {0u, 2u, P4_0, P4_0_KEYSCAN_KS_ROW2}, 128 {0u, 3u, P4_1, P4_1_KEYSCAN_KS_ROW3}, 129 }; 130 131 /* Connections for: lin_lin_en */ 132 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[1] = { 133 {0u, 0u, P3_1, P3_1_LIN0_LIN_EN0}, 134 }; 135 136 /* Connections for: lin_lin_rx */ 137 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[1] = { 138 {0u, 0u, P3_2, P3_2_LIN0_LIN_RX0}, 139 }; 140 141 /* Connections for: lin_lin_tx */ 142 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[1] = { 143 {0u, 0u, P3_3, P3_3_LIN0_LIN_TX0}, 144 }; 145 146 /* Connections for: pdm_pdm_clk */ 147 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[3] = { 148 {0u, 1u, P1_0, P1_0_PDM_PDM_CLK1}, 149 {0u, 0u, P3_2, P3_2_PDM_PDM_CLK0}, 150 {0u, 0u, P5_0, P5_0_PDM_PDM_CLK0}, 151 }; 152 153 /* Connections for: pdm_pdm_data */ 154 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[3] = { 155 {0u, 1u, P1_1, P1_1_PDM_PDM_DATA1}, 156 {0u, 0u, P3_3, P3_3_PDM_PDM_DATA0}, 157 {0u, 0u, P5_1, P5_1_PDM_PDM_DATA0}, 158 }; 159 160 /* Connections for: peri_tr_io_input */ 161 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 162 to know the index of the input or output trigger line. Store that in the channel_num field 163 instead. */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[6] = { 165 {0u, 0u, P0_4, P0_4_PERI_TR_IO_INPUT0}, 166 {0u, 1u, P0_5, P0_5_PERI_TR_IO_INPUT1}, 167 {0u, 2u, P1_2, P1_2_PERI_TR_IO_INPUT2}, 168 {0u, 3u, P1_3, P1_3_PERI_TR_IO_INPUT3}, 169 {0u, 6u, P3_2, P3_2_PERI_TR_IO_INPUT6}, 170 {0u, 7u, P3_3, P3_3_PERI_TR_IO_INPUT7}, 171 }; 172 173 /* Connections for: peri_tr_io_output */ 174 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 175 to know the index of the input or output trigger line. Store that in the channel_num field 176 instead. */ 177 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 178 {0u, 0u, P1_0, P1_0_PERI_TR_IO_OUTPUT0}, 179 {0u, 1u, P1_1, P1_1_PERI_TR_IO_OUTPUT1}, 180 }; 181 182 /* Connections for: scb_i2c_scl */ 183 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[4] = { 184 {2u, 0u, P1_2, P1_2_SCB2_I2C_SCL}, 185 {2u, 0u, P3_2, P3_2_SCB2_I2C_SCL}, 186 {0u, 0u, P4_0, P4_0_SCB0_I2C_SCL}, 187 {2u, 0u, P5_0, P5_0_SCB2_I2C_SCL}, 188 }; 189 190 /* Connections for: scb_i2c_sda */ 191 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[4] = { 192 {2u, 0u, P1_3, P1_3_SCB2_I2C_SDA}, 193 {2u, 0u, P3_3, P3_3_SCB2_I2C_SDA}, 194 {0u, 0u, P4_1, P4_1_SCB0_I2C_SDA}, 195 {2u, 0u, P5_1, P5_1_SCB2_I2C_SDA}, 196 }; 197 198 /* Connections for: scb_spi_m_clk */ 199 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[3] = { 200 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 201 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 202 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 203 }; 204 205 /* Connections for: scb_spi_m_miso */ 206 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[3] = { 207 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 208 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 209 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 210 }; 211 212 /* Connections for: scb_spi_m_mosi */ 213 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[3] = { 214 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 215 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 216 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 217 }; 218 219 /* Connections for: scb_spi_m_select0 */ 220 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[3] = { 221 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 222 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 223 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 224 }; 225 226 /* Connections for: scb_spi_m_select1 */ 227 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1] = { 228 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 229 }; 230 231 /* Connections for: scb_spi_m_select2 */ 232 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1] = { 233 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 234 }; 235 236 /* Connections for: scb_spi_m_select3 */ 237 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1] = { 238 {0u, 0u, NC, HSIOM_SEL_GPIO}, 239 }; 240 241 /* Connections for: scb_spi_s_clk */ 242 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[3] = { 243 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 244 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 245 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 246 }; 247 248 /* Connections for: scb_spi_s_miso */ 249 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[3] = { 250 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 251 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 252 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 253 }; 254 255 /* Connections for: scb_spi_s_mosi */ 256 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[3] = { 257 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 258 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 259 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 260 }; 261 262 /* Connections for: scb_spi_s_select0 */ 263 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[3] = { 264 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 265 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 266 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 267 }; 268 269 /* Connections for: scb_spi_s_select1 */ 270 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1] = { 271 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 272 }; 273 274 /* Connections for: scb_spi_s_select2 */ 275 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1] = { 276 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 277 }; 278 279 /* Connections for: scb_spi_s_select3 */ 280 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1] = { 281 {0u, 0u, NC, HSIOM_SEL_GPIO}, 282 }; 283 284 /* Connections for: scb_uart_cts */ 285 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[3] = { 286 {1u, 0u, P1_0, P1_0_SCB1_UART_CTS}, 287 {2u, 0u, P4_0, P4_0_SCB2_UART_CTS}, 288 {2u, 0u, P5_0, P5_0_SCB2_UART_CTS}, 289 }; 290 291 /* Connections for: scb_uart_rts */ 292 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[2] = { 293 {1u, 0u, P1_1, P1_1_SCB1_UART_RTS}, 294 {2u, 0u, P3_1, P3_1_SCB2_UART_RTS}, 295 }; 296 297 /* Connections for: scb_uart_rx */ 298 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[2] = { 299 {1u, 0u, P1_2, P1_2_SCB1_UART_RX}, 300 {2u, 0u, P3_2, P3_2_SCB2_UART_RX}, 301 }; 302 303 /* Connections for: scb_uart_tx */ 304 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[2] = { 305 {1u, 0u, P1_3, P1_3_SCB1_UART_TX}, 306 {2u, 0u, P3_3, P3_3_SCB2_UART_TX}, 307 }; 308 309 /* Connections for: smif_spi_clk */ 310 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 311 {0u, 0u, P2_5, P2_5_SMIF_SPIHB_CLK}, 312 }; 313 314 /* Connections for: smif_spi_data0 */ 315 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 316 {0u, 0u, P2_4, P2_4_SMIF_SPIHB_DATA0}, 317 }; 318 319 /* Connections for: smif_spi_data1 */ 320 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 321 {0u, 0u, P2_3, P2_3_SMIF_SPIHB_DATA1}, 322 }; 323 324 /* Connections for: smif_spi_data2 */ 325 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 326 {0u, 0u, P2_2, P2_2_SMIF_SPIHB_DATA2}, 327 }; 328 329 /* Connections for: smif_spi_data3 */ 330 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 331 {0u, 0u, P2_1, P2_1_SMIF_SPIHB_DATA3}, 332 }; 333 334 /* Connections for: smif_spi_select0 */ 335 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 336 {0u, 0u, P2_0, P2_0_SMIF_SPIHB_SELECT0}, 337 }; 338 339 /* Connections for: smif_spi_select1 */ 340 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 341 {0u, 0u, P0_5, P0_5_SMIF_SPIHB_SELECT1}, 342 }; 343 344 /* Connections for: tcpwm_line */ 345 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[12] = { 346 {0u, 1u, P0_5, P0_5_TCPWM0_LINE1}, 347 {1u, 2u, P0_5, P0_5_TCPWM0_LINE258}, 348 {0u, 0u, P1_1, P1_1_TCPWM0_LINE0}, 349 {1u, 3u, P1_1, P1_1_TCPWM0_LINE259}, 350 {0u, 1u, P1_3, P1_3_TCPWM0_LINE1}, 351 {1u, 4u, P1_3, P1_3_TCPWM0_LINE260}, 352 {0u, 1u, P3_2, P3_2_TCPWM0_LINE1}, 353 {1u, 1u, P3_2, P3_2_TCPWM0_LINE257}, 354 {0u, 0u, P4_1, P4_1_TCPWM0_LINE0}, 355 {1u, 6u, P4_1, P4_1_TCPWM0_LINE262}, 356 {0u, 0u, P5_0, P5_0_TCPWM0_LINE0}, 357 {1u, 4u, P5_0, P5_0_TCPWM0_LINE260}, 358 }; 359 360 /* Connections for: tcpwm_line_compl */ 361 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[14] = { 362 {0u, 0u, P0_4, P0_4_TCPWM0_LINE_COMPL0}, 363 {1u, 1u, P0_4, P0_4_TCPWM0_LINE_COMPL257}, 364 {0u, 1u, P1_0, P1_0_TCPWM0_LINE_COMPL1}, 365 {1u, 2u, P1_0, P1_0_TCPWM0_LINE_COMPL258}, 366 {0u, 0u, P1_2, P1_2_TCPWM0_LINE_COMPL0}, 367 {1u, 3u, P1_2, P1_2_TCPWM0_LINE_COMPL259}, 368 {0u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL0}, 369 {1u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL256}, 370 {0u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL1}, 371 {1u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL257}, 372 {0u, 1u, P4_0, P4_0_TCPWM0_LINE_COMPL1}, 373 {1u, 5u, P4_0, P4_0_TCPWM0_LINE_COMPL261}, 374 {0u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL0}, 375 {1u, 4u, P5_1, P5_1_TCPWM0_LINE_COMPL260}, 376 }; 377 378 /* Connections for: tdm_tdm_rx_fsync */ 379 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[1] = { 380 {0u, 0u, NC, HSIOM_SEL_GPIO}, 381 }; 382 383 /* Connections for: tdm_tdm_rx_mck */ 384 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1] = { 385 {0u, 0u, NC, HSIOM_SEL_GPIO}, 386 }; 387 388 /* Connections for: tdm_tdm_rx_sck */ 389 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1] = { 390 {0u, 0u, NC, HSIOM_SEL_GPIO}, 391 }; 392 393 /* Connections for: tdm_tdm_rx_sd */ 394 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[1] = { 395 {0u, 0u, NC, HSIOM_SEL_GPIO}, 396 }; 397 398 /* Connections for: tdm_tdm_tx_fsync */ 399 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[1] = { 400 {0u, 0u, P1_0, P1_0_TDM_TDM_TX_FSYNC0}, 401 }; 402 403 /* Connections for: tdm_tdm_tx_mck */ 404 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[1] = { 405 {0u, 0u, P0_4, P0_4_TDM_TDM_TX_MCK0}, 406 }; 407 408 /* Connections for: tdm_tdm_tx_sck */ 409 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[1] = { 410 {0u, 0u, P0_5, P0_5_TDM_TDM_TX_SCK0}, 411 }; 412 413 /* Connections for: tdm_tdm_tx_sd */ 414 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[1] = { 415 {0u, 0u, P1_1, P1_1_TDM_TDM_TX_SD0}, 416 }; 417 418 #endif 419
