1 /******************************************************************************* 2 * File Name: cycfg_pins.h 3 * 4 * Description: 5 * Pin configuration 6 * This file was automatically generated and should not be modified. 7 * Tools Package 2.2.0.2801 8 * latest-v2.X 2.0.0.6211 9 * personalities 3.0.0.0 10 * udd 3.0.0.562 11 * 12 ******************************************************************************** 13 * Copyright 2020 Cypress Semiconductor Corporation 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the "License"); 17 * you may not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an "AS IS" BASIS, 24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 ********************************************************************************/ 28 29 #if !defined(CYCFG_PINS_H) 30 #define CYCFG_PINS_H 31 32 #include "cycfg_notices.h" 33 #include "cy_gpio.h" 34 #if defined (CY_USING_HAL) 35 #include "cyhal_hwmgr.h" 36 #endif //defined (CY_USING_HAL) 37 #include "cycfg_routing.h" 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif 42 43 #define CYBSP_WCO_IN_ENABLED 1U 44 #define CYBSP_WCO_IN_PORT GPIO_PRT0 45 #define CYBSP_WCO_IN_PORT_NUM 0U 46 #define CYBSP_WCO_IN_PIN 0U 47 #define CYBSP_WCO_IN_NUM 0U 48 #define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG 49 #define CYBSP_WCO_IN_INIT_DRIVESTATE 1 50 #ifndef ioss_0_port_0_pin_0_HSIOM 51 #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO 52 #endif 53 #define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM 54 #define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn 55 #if defined (CY_USING_HAL) 56 #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 57 #endif //defined (CY_USING_HAL) 58 #if defined (CY_USING_HAL) 59 #define CYBSP_WCO_IN P0_0 60 #endif //defined (CY_USING_HAL) 61 #if defined (CY_USING_HAL) 62 #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE 63 #endif //defined (CY_USING_HAL) 64 #if defined (CY_USING_HAL) 65 #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 66 #endif //defined (CY_USING_HAL) 67 #if defined (CY_USING_HAL) 68 #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 69 #endif //defined (CY_USING_HAL) 70 #define CYBSP_WCO_OUT_ENABLED 1U 71 #define CYBSP_WCO_OUT_PORT GPIO_PRT0 72 #define CYBSP_WCO_OUT_PORT_NUM 0U 73 #define CYBSP_WCO_OUT_PIN 1U 74 #define CYBSP_WCO_OUT_NUM 1U 75 #define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG 76 #define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 77 #ifndef ioss_0_port_0_pin_1_HSIOM 78 #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO 79 #endif 80 #define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM 81 #define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn 82 #if defined (CY_USING_HAL) 83 #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 84 #endif //defined (CY_USING_HAL) 85 #if defined (CY_USING_HAL) 86 #define CYBSP_WCO_OUT P0_1 87 #endif //defined (CY_USING_HAL) 88 #if defined (CY_USING_HAL) 89 #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE 90 #endif //defined (CY_USING_HAL) 91 #if defined (CY_USING_HAL) 92 #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 93 #endif //defined (CY_USING_HAL) 94 #if defined (CY_USING_HAL) 95 #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 96 #endif //defined (CY_USING_HAL) 97 #if defined (CY_USING_HAL) 98 #define CYBSP_SW2 (P0_4) 99 #define CYBSP_USER_BTN1 CYBSP_SW2 100 #define CYBSP_USER_BTN CYBSP_SW2 101 #endif //defined (CY_USING_HAL) 102 #if defined (CY_USING_HAL) 103 #define CYBSP_LED_RGB_GREEN (P0_5) 104 #define CYBSP_USER_LED4 CYBSP_LED_RGB_GREEN 105 #endif //defined (CY_USING_HAL) 106 #if defined (CY_USING_HAL) 107 #define CYBSP_A0 (P10_0) 108 #define CYBSP_J2_1 CYBSP_A0 109 #endif //defined (CY_USING_HAL) 110 #if defined (CY_USING_HAL) 111 #define CYBSP_A1 (P10_1) 112 #define CYBSP_J2_3 CYBSP_A1 113 #endif //defined (CY_USING_HAL) 114 #if defined (CY_USING_HAL) 115 #define CYBSP_A2 (P10_2) 116 #define CYBSP_J2_5 CYBSP_A2 117 #endif //defined (CY_USING_HAL) 118 #if defined (CY_USING_HAL) 119 #define CYBSP_A3 (P10_3) 120 #define CYBSP_J2_7 CYBSP_A3 121 #endif //defined (CY_USING_HAL) 122 #if defined (CY_USING_HAL) 123 #define CYBSP_A4 (P10_4) 124 #define CYBSP_J2_9 CYBSP_A4 125 #endif //defined (CY_USING_HAL) 126 #if defined (CY_USING_HAL) 127 #define CYBSP_A5 (P10_5) 128 #define CYBSP_J2_11 CYBSP_A5 129 #endif //defined (CY_USING_HAL) 130 #if defined (CY_USING_HAL) 131 #define CYBSP_J2_13 (P10_6) 132 #endif //defined (CY_USING_HAL) 133 #if defined (CY_USING_HAL) 134 #define CYBSP_J2_15 (P10_7) 135 #endif //defined (CY_USING_HAL) 136 #if defined (CY_USING_HAL) 137 #define CYBSP_LED9 (P11_1) 138 #define CYBSP_USER_LED2 CYBSP_LED9 139 #endif //defined (CY_USING_HAL) 140 #if defined (CY_USING_HAL) 141 #define CYBSP_QSPI_SS (P11_2) 142 #endif //defined (CY_USING_HAL) 143 #if defined (CY_USING_HAL) 144 #define CYBSP_QSPI_D3 (P11_3) 145 #endif //defined (CY_USING_HAL) 146 #if defined (CY_USING_HAL) 147 #define CYBSP_QSPI_D2 (P11_4) 148 #endif //defined (CY_USING_HAL) 149 #if defined (CY_USING_HAL) 150 #define CYBSP_QSPI_D1 (P11_5) 151 #endif //defined (CY_USING_HAL) 152 #if defined (CY_USING_HAL) 153 #define CYBSP_QSPI_D0 (P11_6) 154 #endif //defined (CY_USING_HAL) 155 #if defined (CY_USING_HAL) 156 #define CYBSP_QSPI_SCK (P11_7) 157 #endif //defined (CY_USING_HAL) 158 #if defined (CY_USING_HAL) 159 #define CYBSP_SPI_MOSI (P12_0) 160 #define CYBSP_D11 CYBSP_SPI_MOSI 161 #endif //defined (CY_USING_HAL) 162 #if defined (CY_USING_HAL) 163 #define CYBSP_SPI_MISO (P12_1) 164 #define CYBSP_D12 CYBSP_SPI_MISO 165 #endif //defined (CY_USING_HAL) 166 #if defined (CY_USING_HAL) 167 #define CYBSP_SPI_CLK (P12_2) 168 #define CYBSP_D13 CYBSP_SPI_CLK 169 #endif //defined (CY_USING_HAL) 170 #if defined (CY_USING_HAL) 171 #define CYBSP_SPI_CS (P12_3) 172 #define CYBSP_D10 CYBSP_SPI_CS 173 #endif //defined (CY_USING_HAL) 174 #if defined (CY_USING_HAL) 175 #define CYBSP_SDHC_CMD (P12_4) 176 #endif //defined (CY_USING_HAL) 177 #if defined (CY_USING_HAL) 178 #define CYBSP_SDHC_CLK (P12_5) 179 #endif //defined (CY_USING_HAL) 180 #if defined (CY_USING_HAL) 181 #define CYBSP_SDHC_IO0 (P13_0) 182 #endif //defined (CY_USING_HAL) 183 #if defined (CY_USING_HAL) 184 #define CYBSP_SDHC_IO1 (P13_1) 185 #endif //defined (CY_USING_HAL) 186 #if defined (CY_USING_HAL) 187 #define CYBSP_SDHC_IO2 (P13_2) 188 #endif //defined (CY_USING_HAL) 189 #if defined (CY_USING_HAL) 190 #define CYBSP_SDHC_IO3 (P13_3) 191 #endif //defined (CY_USING_HAL) 192 #if defined (CY_USING_HAL) 193 #define CYBSP_SDHC_DETECT (P13_7) 194 #endif //defined (CY_USING_HAL) 195 #define CYBSP_CSD_RX_ENABLED 1U 196 #define CYBSP_CSD_RX_PORT GPIO_PRT1 197 #define CYBSP_CSD_RX_PORT_NUM 1U 198 #define CYBSP_CSD_RX_PIN 0U 199 #define CYBSP_CSD_RX_NUM 0U 200 #define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG 201 #define CYBSP_CSD_RX_INIT_DRIVESTATE 1 202 #ifndef ioss_0_port_1_pin_0_HSIOM 203 #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO 204 #endif 205 #define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM 206 #define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn 207 #if defined (CY_USING_HAL) 208 #define CYBSP_CSD_RX_HAL_PORT_PIN P1_0 209 #endif //defined (CY_USING_HAL) 210 #if defined (CY_USING_HAL) 211 #define CYBSP_CSD_RX P1_0 212 #endif //defined (CY_USING_HAL) 213 #if defined (CY_USING_HAL) 214 #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE 215 #endif //defined (CY_USING_HAL) 216 #if defined (CY_USING_HAL) 217 #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 218 #endif //defined (CY_USING_HAL) 219 #if defined (CY_USING_HAL) 220 #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 221 #endif //defined (CY_USING_HAL) 222 #if defined (CY_USING_HAL) 223 #define CYBSP_LED_RGB_RED (P1_1) 224 #define CYBSP_USER_LED3 CYBSP_LED_RGB_RED 225 #endif //defined (CY_USING_HAL) 226 #if defined (CY_USING_HAL) 227 #define CYBSP_SW4 (P1_4) 228 #define CYBSP_USER_BTN2 CYBSP_SW4 229 #endif //defined (CY_USING_HAL) 230 #if defined (CY_USING_HAL) 231 #define CYBSP_LED8 (P1_5) 232 #define CYBSP_USER_LED1 CYBSP_LED8 233 #define CYBSP_USER_LED CYBSP_LED8 234 #endif //defined (CY_USING_HAL) 235 #if defined (CY_USING_HAL) 236 #define CYBSP_WIFI_SDIO_D0 (P2_0) 237 #endif //defined (CY_USING_HAL) 238 #if defined (CY_USING_HAL) 239 #define CYBSP_WIFI_SDIO_D1 (P2_1) 240 #endif //defined (CY_USING_HAL) 241 #if defined (CY_USING_HAL) 242 #define CYBSP_WIFI_SDIO_D2 (P2_2) 243 #endif //defined (CY_USING_HAL) 244 #if defined (CY_USING_HAL) 245 #define CYBSP_WIFI_SDIO_D3 (P2_3) 246 #endif //defined (CY_USING_HAL) 247 #if defined (CY_USING_HAL) 248 #define CYBSP_WIFI_SDIO_CMD (P2_4) 249 #endif //defined (CY_USING_HAL) 250 #if defined (CY_USING_HAL) 251 #define CYBSP_WIFI_SDIO_CLK (P2_5) 252 #endif //defined (CY_USING_HAL) 253 #if defined (CY_USING_HAL) 254 #define CYBSP_WIFI_WL_REG_ON (P2_6) 255 #endif //defined (CY_USING_HAL) 256 #if defined (CY_USING_HAL) 257 #define CYBSP_BT_UART_RX (P3_0) 258 #endif //defined (CY_USING_HAL) 259 #if defined (CY_USING_HAL) 260 #define CYBSP_BT_UART_TX (P3_1) 261 #endif //defined (CY_USING_HAL) 262 #if defined (CY_USING_HAL) 263 #define CYBSP_BT_UART_RTS (P3_2) 264 #endif //defined (CY_USING_HAL) 265 #if defined (CY_USING_HAL) 266 #define CYBSP_BT_UART_CTS (P3_3) 267 #endif //defined (CY_USING_HAL) 268 #if defined (CY_USING_HAL) 269 #define CYBSP_BT_POWER (P3_4) 270 #endif //defined (CY_USING_HAL) 271 #if defined (CY_USING_HAL) 272 #define CYBSP_BT_DEVICE_WAKE (P3_5) 273 #endif //defined (CY_USING_HAL) 274 #if defined (CY_USING_HAL) 275 #define CYBSP_BT_HOST_WAKE (P4_0) 276 #endif //defined (CY_USING_HAL) 277 #if defined (CY_USING_HAL) 278 #define CYBSP_WIFI_HOST_WAKE (P4_1) 279 #endif //defined (CY_USING_HAL) 280 #if defined (CY_USING_HAL) 281 #define CYBSP_DEBUG_UART_RX (P5_0) 282 #define CYBSP_D0 CYBSP_DEBUG_UART_RX 283 #endif //defined (CY_USING_HAL) 284 #if defined (CY_USING_HAL) 285 #define CYBSP_DEBUG_UART_TX (P5_1) 286 #define CYBSP_D1 CYBSP_DEBUG_UART_TX 287 #endif //defined (CY_USING_HAL) 288 #if defined (CY_USING_HAL) 289 #define CYBSP_DEBUG_UART_RTS (P5_2) 290 #define CYBSP_D2 CYBSP_DEBUG_UART_RTS 291 #endif //defined (CY_USING_HAL) 292 #if defined (CY_USING_HAL) 293 #define CYBSP_DEBUG_UART_CTS (P5_3) 294 #define CYBSP_D3 CYBSP_DEBUG_UART_CTS 295 #endif //defined (CY_USING_HAL) 296 #if defined (CY_USING_HAL) 297 #define CYBSP_D4 (P5_4) 298 #endif //defined (CY_USING_HAL) 299 #if defined (CY_USING_HAL) 300 #define CYBSP_D5 (P5_5) 301 #endif //defined (CY_USING_HAL) 302 #if defined (CY_USING_HAL) 303 #define CYBSP_D6 (P5_6) 304 #endif //defined (CY_USING_HAL) 305 #if defined (CY_USING_HAL) 306 #define CYBSP_D7 (P5_7) 307 #endif //defined (CY_USING_HAL) 308 #if defined (CY_USING_HAL) 309 #define CYBSP_I2C_SCL (P6_0) 310 #define CYBSP_D15 CYBSP_I2C_SCL 311 #endif //defined (CY_USING_HAL) 312 #if defined (CY_USING_HAL) 313 #define CYBSP_I2C_SDA (P6_1) 314 #define CYBSP_D14 CYBSP_I2C_SDA 315 #endif //defined (CY_USING_HAL) 316 #define CYBSP_SWO_ENABLED 1U 317 #define CYBSP_SWO_PORT GPIO_PRT6 318 #define CYBSP_SWO_PORT_NUM 6U 319 #define CYBSP_SWO_PIN 4U 320 #define CYBSP_SWO_NUM 4U 321 #define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF 322 #define CYBSP_SWO_INIT_DRIVESTATE 1 323 #ifndef ioss_0_port_6_pin_4_HSIOM 324 #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO 325 #endif 326 #define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM 327 #define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn 328 #if defined (CY_USING_HAL) 329 #define CYBSP_SWO_HAL_PORT_PIN P6_4 330 #endif //defined (CY_USING_HAL) 331 #if defined (CY_USING_HAL) 332 #define CYBSP_SWO P6_4 333 #endif //defined (CY_USING_HAL) 334 #if defined (CY_USING_HAL) 335 #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE 336 #endif //defined (CY_USING_HAL) 337 #if defined (CY_USING_HAL) 338 #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 339 #endif //defined (CY_USING_HAL) 340 #if defined (CY_USING_HAL) 341 #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG 342 #endif //defined (CY_USING_HAL) 343 #define CYBSP_SWDIO_ENABLED 1U 344 #define CYBSP_SWDIO_PORT GPIO_PRT6 345 #define CYBSP_SWDIO_PORT_NUM 6U 346 #define CYBSP_SWDIO_PIN 6U 347 #define CYBSP_SWDIO_NUM 6U 348 #define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP 349 #define CYBSP_SWDIO_INIT_DRIVESTATE 1 350 #ifndef ioss_0_port_6_pin_6_HSIOM 351 #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO 352 #endif 353 #define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM 354 #define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn 355 #if defined (CY_USING_HAL) 356 #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 357 #endif //defined (CY_USING_HAL) 358 #if defined (CY_USING_HAL) 359 #define CYBSP_SWDIO P6_6 360 #endif //defined (CY_USING_HAL) 361 #if defined (CY_USING_HAL) 362 #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE 363 #endif //defined (CY_USING_HAL) 364 #if defined (CY_USING_HAL) 365 #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 366 #endif //defined (CY_USING_HAL) 367 #if defined (CY_USING_HAL) 368 #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP 369 #endif //defined (CY_USING_HAL) 370 #define CYBSP_SWDCK_ENABLED 1U 371 #define CYBSP_SWDCK_PORT GPIO_PRT6 372 #define CYBSP_SWDCK_PORT_NUM 6U 373 #define CYBSP_SWDCK_PIN 7U 374 #define CYBSP_SWDCK_NUM 7U 375 #define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN 376 #define CYBSP_SWDCK_INIT_DRIVESTATE 1 377 #ifndef ioss_0_port_6_pin_7_HSIOM 378 #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO 379 #endif 380 #define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM 381 #define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn 382 #if defined (CY_USING_HAL) 383 #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 384 #endif //defined (CY_USING_HAL) 385 #if defined (CY_USING_HAL) 386 #define CYBSP_SWDCK P6_7 387 #endif //defined (CY_USING_HAL) 388 #if defined (CY_USING_HAL) 389 #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE 390 #endif //defined (CY_USING_HAL) 391 #if defined (CY_USING_HAL) 392 #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 393 #endif //defined (CY_USING_HAL) 394 #if defined (CY_USING_HAL) 395 #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN 396 #endif //defined (CY_USING_HAL) 397 #define CYBSP_CINA_ENABLED 1U 398 #define CYBSP_CINA_PORT GPIO_PRT7 399 #define CYBSP_CINA_PORT_NUM 7U 400 #define CYBSP_CINA_PIN 1U 401 #define CYBSP_CINA_NUM 1U 402 #define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG 403 #define CYBSP_CINA_INIT_DRIVESTATE 1 404 #ifndef ioss_0_port_7_pin_1_HSIOM 405 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO 406 #endif 407 #define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM 408 #define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn 409 #if defined (CY_USING_HAL) 410 #define CYBSP_CINA_HAL_PORT_PIN P7_1 411 #endif //defined (CY_USING_HAL) 412 #if defined (CY_USING_HAL) 413 #define CYBSP_CINA P7_1 414 #endif //defined (CY_USING_HAL) 415 #if defined (CY_USING_HAL) 416 #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE 417 #endif //defined (CY_USING_HAL) 418 #if defined (CY_USING_HAL) 419 #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 420 #endif //defined (CY_USING_HAL) 421 #if defined (CY_USING_HAL) 422 #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 423 #endif //defined (CY_USING_HAL) 424 #define CYBSP_CINB_ENABLED 1U 425 #define CYBSP_CINB_PORT GPIO_PRT7 426 #define CYBSP_CINB_PORT_NUM 7U 427 #define CYBSP_CINB_PIN 2U 428 #define CYBSP_CINB_NUM 2U 429 #define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG 430 #define CYBSP_CINB_INIT_DRIVESTATE 1 431 #ifndef ioss_0_port_7_pin_2_HSIOM 432 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO 433 #endif 434 #define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM 435 #define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn 436 #if defined (CY_USING_HAL) 437 #define CYBSP_CINB_HAL_PORT_PIN P7_2 438 #endif //defined (CY_USING_HAL) 439 #if defined (CY_USING_HAL) 440 #define CYBSP_CINB P7_2 441 #endif //defined (CY_USING_HAL) 442 #if defined (CY_USING_HAL) 443 #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE 444 #endif //defined (CY_USING_HAL) 445 #if defined (CY_USING_HAL) 446 #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 447 #endif //defined (CY_USING_HAL) 448 #if defined (CY_USING_HAL) 449 #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 450 #endif //defined (CY_USING_HAL) 451 #if defined (CY_USING_HAL) 452 #define CYBSP_LED_RGB_BLUE (P7_3) 453 #define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE 454 #endif //defined (CY_USING_HAL) 455 #if defined (CY_USING_HAL) 456 #define CYBSP_D8 (P7_5) 457 #endif //defined (CY_USING_HAL) 458 #if defined (CY_USING_HAL) 459 #define CYBSP_D9 (P7_6) 460 #endif //defined (CY_USING_HAL) 461 #define CYBSP_CMOD_ENABLED 1U 462 #define CYBSP_CMOD_PORT GPIO_PRT7 463 #define CYBSP_CMOD_PORT_NUM 7U 464 #define CYBSP_CMOD_PIN 7U 465 #define CYBSP_CMOD_NUM 7U 466 #define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG 467 #define CYBSP_CMOD_INIT_DRIVESTATE 1 468 #ifndef ioss_0_port_7_pin_7_HSIOM 469 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO 470 #endif 471 #define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM 472 #define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn 473 #if defined (CY_USING_HAL) 474 #define CYBSP_CMOD_HAL_PORT_PIN P7_7 475 #endif //defined (CY_USING_HAL) 476 #if defined (CY_USING_HAL) 477 #define CYBSP_CMOD P7_7 478 #endif //defined (CY_USING_HAL) 479 #if defined (CY_USING_HAL) 480 #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE 481 #endif //defined (CY_USING_HAL) 482 #if defined (CY_USING_HAL) 483 #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 484 #endif //defined (CY_USING_HAL) 485 #if defined (CY_USING_HAL) 486 #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 487 #endif //defined (CY_USING_HAL) 488 #define CYBSP_CSD_BTN0_ENABLED 1U 489 #define CYBSP_CSD_BTN0_PORT GPIO_PRT8 490 #define CYBSP_CSD_BTN0_PORT_NUM 8U 491 #define CYBSP_CSD_BTN0_PIN 1U 492 #define CYBSP_CSD_BTN0_NUM 1U 493 #define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG 494 #define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 495 #ifndef ioss_0_port_8_pin_1_HSIOM 496 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO 497 #endif 498 #define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM 499 #define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn 500 #if defined (CY_USING_HAL) 501 #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1 502 #endif //defined (CY_USING_HAL) 503 #if defined (CY_USING_HAL) 504 #define CYBSP_CSD_BTN0 P8_1 505 #endif //defined (CY_USING_HAL) 506 #if defined (CY_USING_HAL) 507 #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE 508 #endif //defined (CY_USING_HAL) 509 #if defined (CY_USING_HAL) 510 #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 511 #endif //defined (CY_USING_HAL) 512 #if defined (CY_USING_HAL) 513 #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 514 #endif //defined (CY_USING_HAL) 515 #define CYBSP_CSD_BTN1_ENABLED 1U 516 #define CYBSP_CSD_BTN1_PORT GPIO_PRT8 517 #define CYBSP_CSD_BTN1_PORT_NUM 8U 518 #define CYBSP_CSD_BTN1_PIN 2U 519 #define CYBSP_CSD_BTN1_NUM 2U 520 #define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG 521 #define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 522 #ifndef ioss_0_port_8_pin_2_HSIOM 523 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO 524 #endif 525 #define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM 526 #define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn 527 #if defined (CY_USING_HAL) 528 #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2 529 #endif //defined (CY_USING_HAL) 530 #if defined (CY_USING_HAL) 531 #define CYBSP_CSD_BTN1 P8_2 532 #endif //defined (CY_USING_HAL) 533 #if defined (CY_USING_HAL) 534 #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE 535 #endif //defined (CY_USING_HAL) 536 #if defined (CY_USING_HAL) 537 #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 538 #endif //defined (CY_USING_HAL) 539 #if defined (CY_USING_HAL) 540 #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 541 #endif //defined (CY_USING_HAL) 542 #define CYBSP_CSD_SLD0_ENABLED 1U 543 #define CYBSP_CSD_SLD0_PORT GPIO_PRT8 544 #define CYBSP_CSD_SLD0_PORT_NUM 8U 545 #define CYBSP_CSD_SLD0_PIN 3U 546 #define CYBSP_CSD_SLD0_NUM 3U 547 #define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG 548 #define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 549 #ifndef ioss_0_port_8_pin_3_HSIOM 550 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO 551 #endif 552 #define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM 553 #define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn 554 #if defined (CY_USING_HAL) 555 #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3 556 #endif //defined (CY_USING_HAL) 557 #if defined (CY_USING_HAL) 558 #define CYBSP_CSD_SLD0 P8_3 559 #endif //defined (CY_USING_HAL) 560 #if defined (CY_USING_HAL) 561 #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE 562 #endif //defined (CY_USING_HAL) 563 #if defined (CY_USING_HAL) 564 #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 565 #endif //defined (CY_USING_HAL) 566 #if defined (CY_USING_HAL) 567 #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 568 #endif //defined (CY_USING_HAL) 569 #define CYBSP_CSD_SLD1_ENABLED 1U 570 #define CYBSP_CSD_SLD1_PORT GPIO_PRT8 571 #define CYBSP_CSD_SLD1_PORT_NUM 8U 572 #define CYBSP_CSD_SLD1_PIN 4U 573 #define CYBSP_CSD_SLD1_NUM 4U 574 #define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG 575 #define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 576 #ifndef ioss_0_port_8_pin_4_HSIOM 577 #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO 578 #endif 579 #define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM 580 #define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn 581 #if defined (CY_USING_HAL) 582 #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4 583 #endif //defined (CY_USING_HAL) 584 #if defined (CY_USING_HAL) 585 #define CYBSP_CSD_SLD1 P8_4 586 #endif //defined (CY_USING_HAL) 587 #if defined (CY_USING_HAL) 588 #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE 589 #endif //defined (CY_USING_HAL) 590 #if defined (CY_USING_HAL) 591 #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 592 #endif //defined (CY_USING_HAL) 593 #if defined (CY_USING_HAL) 594 #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 595 #endif //defined (CY_USING_HAL) 596 #define CYBSP_CSD_SLD2_ENABLED 1U 597 #define CYBSP_CSD_SLD2_PORT GPIO_PRT8 598 #define CYBSP_CSD_SLD2_PORT_NUM 8U 599 #define CYBSP_CSD_SLD2_PIN 5U 600 #define CYBSP_CSD_SLD2_NUM 5U 601 #define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG 602 #define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 603 #ifndef ioss_0_port_8_pin_5_HSIOM 604 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO 605 #endif 606 #define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM 607 #define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn 608 #if defined (CY_USING_HAL) 609 #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5 610 #endif //defined (CY_USING_HAL) 611 #if defined (CY_USING_HAL) 612 #define CYBSP_CSD_SLD2 P8_5 613 #endif //defined (CY_USING_HAL) 614 #if defined (CY_USING_HAL) 615 #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE 616 #endif //defined (CY_USING_HAL) 617 #if defined (CY_USING_HAL) 618 #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 619 #endif //defined (CY_USING_HAL) 620 #if defined (CY_USING_HAL) 621 #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 622 #endif //defined (CY_USING_HAL) 623 #define CYBSP_CSD_SLD3_ENABLED 1U 624 #define CYBSP_CSD_SLD3_PORT GPIO_PRT8 625 #define CYBSP_CSD_SLD3_PORT_NUM 8U 626 #define CYBSP_CSD_SLD3_PIN 6U 627 #define CYBSP_CSD_SLD3_NUM 6U 628 #define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG 629 #define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 630 #ifndef ioss_0_port_8_pin_6_HSIOM 631 #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO 632 #endif 633 #define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM 634 #define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn 635 #if defined (CY_USING_HAL) 636 #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6 637 #endif //defined (CY_USING_HAL) 638 #if defined (CY_USING_HAL) 639 #define CYBSP_CSD_SLD3 P8_6 640 #endif //defined (CY_USING_HAL) 641 #if defined (CY_USING_HAL) 642 #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE 643 #endif //defined (CY_USING_HAL) 644 #if defined (CY_USING_HAL) 645 #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 646 #endif //defined (CY_USING_HAL) 647 #if defined (CY_USING_HAL) 648 #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 649 #endif //defined (CY_USING_HAL) 650 #define CYBSP_CSD_SLD4_ENABLED 1U 651 #define CYBSP_CSD_SLD4_PORT GPIO_PRT8 652 #define CYBSP_CSD_SLD4_PORT_NUM 8U 653 #define CYBSP_CSD_SLD4_PIN 7U 654 #define CYBSP_CSD_SLD4_NUM 7U 655 #define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG 656 #define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 657 #ifndef ioss_0_port_8_pin_7_HSIOM 658 #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO 659 #endif 660 #define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM 661 #define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn 662 #if defined (CY_USING_HAL) 663 #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7 664 #endif //defined (CY_USING_HAL) 665 #if defined (CY_USING_HAL) 666 #define CYBSP_CSD_SLD4 P8_7 667 #endif //defined (CY_USING_HAL) 668 #if defined (CY_USING_HAL) 669 #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE 670 #endif //defined (CY_USING_HAL) 671 #if defined (CY_USING_HAL) 672 #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 673 #endif //defined (CY_USING_HAL) 674 #if defined (CY_USING_HAL) 675 #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 676 #endif //defined (CY_USING_HAL) 677 #if defined (CY_USING_HAL) 678 #define CYBSP_J2_2 (P9_0) 679 #endif //defined (CY_USING_HAL) 680 #if defined (CY_USING_HAL) 681 #define CYBSP_J2_4 (P9_1) 682 #endif //defined (CY_USING_HAL) 683 #if defined (CY_USING_HAL) 684 #define CYBSP_J2_6 (P9_2) 685 #endif //defined (CY_USING_HAL) 686 #if defined (CY_USING_HAL) 687 #define CYBSP_J2_8 (P9_3) 688 #endif //defined (CY_USING_HAL) 689 #if defined (CY_USING_HAL) 690 #define CYBSP_J2_10 (P9_4) 691 #endif //defined (CY_USING_HAL) 692 #if defined (CY_USING_HAL) 693 #define CYBSP_J2_12 (P9_5) 694 #endif //defined (CY_USING_HAL) 695 #if defined (CY_USING_HAL) 696 #define CYBSP_J2_14 (P9_6) 697 #endif //defined (CY_USING_HAL) 698 #if defined (CY_USING_HAL) 699 #define CYBSP_J2_16 (P9_7) 700 #endif //defined (CY_USING_HAL) 701 702 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; 703 #if defined (CY_USING_HAL) 704 extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; 705 #endif //defined (CY_USING_HAL) 706 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; 707 #if defined (CY_USING_HAL) 708 extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; 709 #endif //defined (CY_USING_HAL) 710 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; 711 #if defined (CY_USING_HAL) 712 extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; 713 #endif //defined (CY_USING_HAL) 714 extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; 715 #if defined (CY_USING_HAL) 716 extern const cyhal_resource_inst_t CYBSP_SWO_obj; 717 #endif //defined (CY_USING_HAL) 718 extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; 719 #if defined (CY_USING_HAL) 720 extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; 721 #endif //defined (CY_USING_HAL) 722 extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; 723 #if defined (CY_USING_HAL) 724 extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; 725 #endif //defined (CY_USING_HAL) 726 extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config; 727 #if defined (CY_USING_HAL) 728 extern const cyhal_resource_inst_t CYBSP_CINA_obj; 729 #endif //defined (CY_USING_HAL) 730 extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config; 731 #if defined (CY_USING_HAL) 732 extern const cyhal_resource_inst_t CYBSP_CINB_obj; 733 #endif //defined (CY_USING_HAL) 734 extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; 735 #if defined (CY_USING_HAL) 736 extern const cyhal_resource_inst_t CYBSP_CMOD_obj; 737 #endif //defined (CY_USING_HAL) 738 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; 739 #if defined (CY_USING_HAL) 740 extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; 741 #endif //defined (CY_USING_HAL) 742 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; 743 #if defined (CY_USING_HAL) 744 extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; 745 #endif //defined (CY_USING_HAL) 746 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; 747 #if defined (CY_USING_HAL) 748 extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; 749 #endif //defined (CY_USING_HAL) 750 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; 751 #if defined (CY_USING_HAL) 752 extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; 753 #endif //defined (CY_USING_HAL) 754 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; 755 #if defined (CY_USING_HAL) 756 extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; 757 #endif //defined (CY_USING_HAL) 758 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; 759 #if defined (CY_USING_HAL) 760 extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; 761 #endif //defined (CY_USING_HAL) 762 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; 763 #if defined (CY_USING_HAL) 764 extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; 765 #endif //defined (CY_USING_HAL) 766 767 void init_cycfg_pins(void); 768 769 #if defined(__cplusplus) 770 } 771 #endif 772 773 774 #endif /* CYCFG_PINS_H */ 775
