1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cyb06xxa_cm0plus.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM0+ core.
49; You can change the memory allocation by editing the RAM and Flash defines.
50; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
51; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
52; RAM
53#define RAM_START               0x080E0000
54#define RAM_SIZE                0x0000C000
55; Flash
56#define FLASH_START             0x10000000
57#define FLASH_SIZE              0x00010000
58
59; The size of the stack section at the end of CM0+ SRAM
60#define STACK_SIZE              0x00001000
61
62; The size of the MCU boot header area at the start of FLASH
63#define BOOT_HEADER_SIZE        0x00000400
64
65; The following defines describe a 32K flash region used for EEPROM emulation.
66; This region can also be used as the general purpose flash.
67; You can assign sections to this memory region for only one of the cores.
68; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
69; Therefore, repurposing this memory region will prevent such middleware from operation.
70#define EM_EEPROM_START         0x14000000
71#define EM_EEPROM_SIZE          0x8000
72
73; The following defines describe device specific memory regions and must not be changed.
74; Supervisory flash: User data
75#define SFLASH_USER_DATA_START  0x16000800
76#define SFLASH_USER_DATA_SIZE   0x00000800
77
78; Supervisory flash: Normal Access Restrictions (NAR)
79#define SFLASH_NAR_START        0x16001A00
80#define SFLASH_NAR_SIZE         0x00000200
81
82; Supervisory flash: Public Key
83#define SFLASH_PUBLIC_KEY_START 0x16005A00
84#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
85
86; Supervisory flash: Table of Content # 2
87#define SFLASH_TOC_2_START      0x16007C00
88#define SFLASH_TOC_2_SIZE       0x00000200
89
90; Supervisory flash: Table of Content # 2 Copy
91#define SFLASH_RTOC_2_START     0x16007E00
92#define SFLASH_RTOC_2_SIZE      0x00000200
93
94; External memory
95#define XIP_START               0x18000000
96#define XIP_SIZE                0x08000000
97
98; eFuse
99#define EFUSE_START             0x90700000
100#define EFUSE_SIZE              0x100000
101
102; Public RAM
103#define PUBLIC_RAM_SIZE         0x800
104#define PUBLIC_RAM_START        0x08000000
105
106; Cortex-M0+ application flash area
107LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
108{
109    ER_FLASH_VECTORS +0
110    {
111        * (RESET, +FIRST)
112    }
113
114    ER_FLASH_CODE +0 FIXED
115    {
116        * (InRoot$$Sections)
117        * (+RO)
118    }
119
120    ER_RAM_VECTORS RAM_START UNINIT
121    {
122        * (RESET_RAM, +FIRST)
123    }
124
125    RW_RAM_DATA +0
126    {
127        * (.cy_ramfunc)
128        * (+RW, +ZI)
129    }
130
131    ; Place variables in the section that should not be initialized during the
132    ; device startup.
133    RW_IRAM1 +0 UNINIT
134    {
135        * (.noinit)
136        * (.bss.noinit)
137    }
138
139    RW_IRAM2 PUBLIC_RAM_START UNINIT
140    {
141        * (.cy_sharedmem)
142    }
143
144    ; Application heap area (HEAP)
145    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
146    {
147    }
148
149    ; Stack region growing down
150    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
151    {
152    }
153}
154
155
156; Emulated EEPROM Flash area
157LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
158{
159    .cy_em_eeprom +0
160    {
161        * (.cy_em_eeprom)
162    }
163}
164
165; Supervisory flash: User data
166LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
167{
168    .cy_sflash_user_data +0
169    {
170        * (.cy_sflash_user_data)
171    }
172}
173
174; Supervisory flash: Normal Access Restrictions (NAR)
175LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
176{
177    .cy_sflash_nar +0
178    {
179        * (.cy_sflash_nar)
180    }
181}
182
183; Supervisory flash: Public Key
184LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
185{
186    .cy_sflash_public_key +0
187    {
188        * (.cy_sflash_public_key)
189    }
190}
191
192; Supervisory flash: Table of Content # 2
193LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
194{
195    .cy_toc_part2 +0
196    {
197        * (.cy_toc_part2)
198    }
199}
200
201; Supervisory flash: Table of Content # 2 Copy
202LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
203{
204    .cy_rtoc_part2 +0
205    {
206        * (.cy_rtoc_part2)
207    }
208}
209
210
211; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
212LR_EROM XIP_START XIP_SIZE
213{
214    cy_xip +0
215    {
216        * (.cy_xip)
217    }
218}
219
220
221; eFuse
222LR_EFUSE EFUSE_START EFUSE_SIZE
223{
224    .cy_efuse +0
225    {
226        * (.cy_efuse)
227    }
228}
229
230
231; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
232CYMETA 0x90500000
233{
234    .cymeta +0 { * (.cymeta) }
235}
236
237/* The following symbols used by the cymcuelftool. */
238/* Flash */
239#define __cy_memory_0_start 0x10000000
240#define __cy_memory_0_length  0x001D0000
241#define __cy_memory_0_row_size 0x200
242
243/* Emulated EEPROM Flash area */
244#define __cy_memory_1_start    0x14000000
245#define __cy_memory_1_length   0x8000
246#define __cy_memory_1_row_size 0x200
247
248/* Supervisory Flash */
249#define __cy_memory_2_start    0x16000000
250#define __cy_memory_2_length   0x8000
251#define __cy_memory_2_row_size 0x200
252
253/* XIP */
254#define __cy_memory_3_start    0x18000000
255#define __cy_memory_3_length   0x08000000
256#define __cy_memory_3_row_size 0x200
257
258/* eFuse */
259#define __cy_memory_4_start    0x90700000
260#define __cy_memory_4_length   0x100000
261#define __cy_memory_4_row_size 1
262
263
264/* [] END OF FILE */
265