1/***************************************************************************//**
2* \file cyb06xx7_cm4_dual.ld
3* \version 2.95.1
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
39SEARCH_DIR(.)
40GROUP(-lgcc -lc -lnosys)
41ENTRY(Reset_Handler)
42
43/* The size of the stack section at the end of CM4 SRAM */
44STACK_SIZE = 0x1000;
45
46/* The size of the MCU boot header area at the start of FLASH */
47BOOT_HEADER_SIZE = 0x400;
48
49/* The size of the Cortex-M0+ application image (including MCU boot header area) */
50FLASH_CM0P_SIZE  = 0x10000;
51
52/* Force symbol to be entered in the output file as an undefined symbol. Doing
53* this may, for example, trigger linking of additional modules from standard
54* libraries. You may list several symbols for each EXTERN, and you may use
55* EXTERN multiple times. This command has the same effect as the -u command-line
56* option.
57*/
58EXTERN(Reset_Handler)
59
60/* The MEMORY section below describes the location and size of blocks of memory in the target.
61* Use this section to specify the memory regions available for allocation.
62*/
63MEMORY
64{
65    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
66     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
67     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
68     * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.ld'.
69     */
70    ram               (rwx)   : ORIGIN = 0x08000800, LENGTH = 0x1F800
71    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x68000
72
73    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
74     * You can assign sections to this memory region for only one of the cores.
75     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
76     * Therefore, repurposing this memory region will prevent such middleware from operation.
77     */
78    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
79
80    /* The following regions define device specific memory regions and must not be changed. */
81    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
82}
83
84/* Library configurations */
85GROUP(libgcc.a libc.a libm.a libnosys.a)
86
87/* Linker script to place sections and symbol values. Should be used together
88 * with other linker script that defines memory regions FLASH and RAM.
89 * It references following symbols, which must be defined in code:
90 *   Reset_Handler : Entry of reset handler
91 *
92 * It defines following symbols, which code can use without definition:
93 *   __exidx_start
94 *   __exidx_end
95 *   __copy_table_start__
96 *   __copy_table_end__
97 *   __zero_table_start__
98 *   __zero_table_end__
99 *   __etext
100 *   __data_start__
101 *   __preinit_array_start
102 *   __preinit_array_end
103 *   __init_array_start
104 *   __init_array_end
105 *   __fini_array_start
106 *   __fini_array_end
107 *   __data_end__
108 *   __bss_start__
109 *   __bss_end__
110 *   __end__
111 *   end
112 *   __HeapLimit
113 *   __StackLimit
114 *   __StackTop
115 *   __stack
116 *   __Vectors_End
117 *   __Vectors_Size
118 */
119
120
121SECTIONS
122{
123     /* Cortex-M0+ application flash image area */
124    .cy_m0p_image ORIGIN(flash) + BOOT_HEADER_SIZE :
125    {
126        . = ALIGN(4);
127        __cy_m0p_code_start = . ;
128        KEEP(*(.cy_m0p_image))
129        __cy_m0p_code_end = . ;
130    } > flash
131
132    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
133    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
134
135    /* Cortex-M4 application flash area */
136    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
137    {
138        . = ALIGN(4);
139        __Vectors = . ;
140        KEEP(*(.vectors))
141        . = ALIGN(4);
142        __Vectors_End = .;
143        __Vectors_Size = __Vectors_End - __Vectors;
144        __end__ = .;
145
146        . = ALIGN(4);
147        *(.text*)
148
149        KEEP(*(.init))
150        KEEP(*(.fini))
151
152        /* .ctors */
153        *crtbegin.o(.ctors)
154        *crtbegin?.o(.ctors)
155        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
156        *(SORT(.ctors.*))
157        *(.ctors)
158
159        /* .dtors */
160        *crtbegin.o(.dtors)
161        *crtbegin?.o(.dtors)
162        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
163        *(SORT(.dtors.*))
164        *(.dtors)
165
166        /* Read-only code (constants). */
167        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
168
169        KEEP(*(.eh_frame*))
170    } > flash
171
172
173    .ARM.extab :
174    {
175        *(.ARM.extab* .gnu.linkonce.armextab.*)
176    } > flash
177
178    __exidx_start = .;
179
180    .ARM.exidx :
181    {
182        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
183    } > flash
184    __exidx_end = .;
185
186
187    /* To copy multiple ROM to RAM sections,
188     * uncomment .copy.table section and,
189     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
190    .copy.table :
191    {
192        . = ALIGN(4);
193        __copy_table_start__ = .;
194
195        /* Copy interrupt vectors from flash to RAM */
196        LONG (__Vectors)                                    /* From */
197        LONG (__ram_vectors_start__)                        /* To   */
198        LONG (__Vectors_End - __Vectors)                    /* Size */
199
200        /* Copy data section to RAM */
201        LONG (__etext)                                      /* From */
202        LONG (__data_start__)                               /* To   */
203        LONG (__data_end__ - __data_start__)                /* Size */
204
205        __copy_table_end__ = .;
206    } > flash
207
208
209    /* To clear multiple BSS sections,
210     * uncomment .zero.table section and,
211     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
212    .zero.table :
213    {
214        . = ALIGN(4);
215        __zero_table_start__ = .;
216        LONG (__bss_start__)
217        LONG (__bss_end__ - __bss_start__)
218        __zero_table_end__ = .;
219    } > flash
220
221    __etext =  . ;
222
223
224    .ramVectors (NOLOAD) : ALIGN(8)
225    {
226        __ram_vectors_start__ = .;
227        KEEP(*(.ram_vectors))
228        __ram_vectors_end__   = .;
229    } > ram
230
231
232    .data __ram_vectors_end__ :
233    {
234        . = ALIGN(4);
235        __data_start__ = .;
236
237        *(vtable)
238        *(.data*)
239
240        . = ALIGN(4);
241        /* preinit data */
242        PROVIDE_HIDDEN (__preinit_array_start = .);
243        KEEP(*(.preinit_array))
244        PROVIDE_HIDDEN (__preinit_array_end = .);
245
246        . = ALIGN(4);
247        /* init data */
248        PROVIDE_HIDDEN (__init_array_start = .);
249        KEEP(*(SORT(.init_array.*)))
250        KEEP(*(.init_array))
251        PROVIDE_HIDDEN (__init_array_end = .);
252
253        . = ALIGN(4);
254        /* finit data */
255        PROVIDE_HIDDEN (__fini_array_start = .);
256        KEEP(*(SORT(.fini_array.*)))
257        KEEP(*(.fini_array))
258        PROVIDE_HIDDEN (__fini_array_end = .);
259
260        KEEP(*(.jcr*))
261        . = ALIGN(4);
262
263        KEEP(*(.cy_ramfunc*))
264        . = ALIGN(4);
265
266        __data_end__ = .;
267
268    } > ram AT>flash
269
270
271    /* Place variables in the section that should not be initialized during the
272    *  device startup.
273    */
274    .noinit (NOLOAD) : ALIGN(8)
275    {
276      KEEP(*(.noinit))
277    } > ram
278
279
280    /* The uninitialized global or static variables are placed in this section.
281    *
282    * The NOLOAD attribute tells linker that .bss section does not consume
283    * any space in the image. The NOLOAD attribute changes the .bss type to
284    * NOBITS, and that  makes linker to A) not allocate section in memory, and
285    * A) put information to clear the section with all zeros during application
286    * loading.
287    *
288    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
289    * This  makes linker to A) allocate zeroed section in memory, and B) copy
290    * this section to RAM during application loading.
291    */
292    .bss (NOLOAD):
293    {
294        . = ALIGN(4);
295        __bss_start__ = .;
296        *(.bss*)
297        *(COMMON)
298        . = ALIGN(4);
299        __bss_end__ = .;
300    } > ram
301
302
303    .heap (NOLOAD):
304    {
305        __HeapBase = .;
306        __end__ = .;
307        end = __end__;
308        KEEP(*(.heap*))
309        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
310        __HeapLimit = .;
311    } > ram
312
313
314    /* .stack_dummy section doesn't contains any symbols. It is only
315     * used for linker to calculate size of stack sections, and assign
316     * values to stack symbols later */
317    .stack_dummy (NOLOAD):
318    {
319        KEEP(*(.stack*))
320    } > ram
321
322
323    /* Set stack top to end of RAM, and stack limit move down by
324     * size of stack_dummy section */
325    __StackTop = ORIGIN(ram) + LENGTH(ram);
326    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
327    PROVIDE(__stack = __StackTop);
328
329    /* Check if data + heap + stack exceeds RAM limit */
330    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
331
332
333    /* Used for the digital signature of the secure application and the Bootloader SDK application.
334    * The size of the section depends on the required data size. */
335    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
336    {
337        KEEP(*(.cy_app_signature))
338    } > flash
339
340
341    /* Emulated EEPROM Flash area */
342    .cy_em_eeprom :
343    {
344        KEEP(*(.cy_em_eeprom))
345    } > em_eeprom
346
347
348
349    /* Places the code in the Execute in Place (XIP) section. See the smif driver
350    *  documentation for details.
351    */
352    cy_xip :
353    {
354        __cy_xip_start = .;
355        KEEP(*(.cy_xip))
356        __cy_xip_end = .;
357    } > xip
358
359}
360
361/* EOF */
362