1/***************************************************************************//**
2* \file cyb06xx7_cm0plus.ld
3* \version 2.95.1
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
39SEARCH_DIR(.)
40GROUP(-lgcc -lc -lnosys)
41ENTRY(Reset_Handler)
42
43/* The size of the stack section at the end of CM0+ SRAM */
44STACK_SIZE = 0x1000;
45
46/* The size of the MCU boot header area at the start of FLASH */
47BOOT_HEADER_SIZE = 0x400;
48
49/* The size of the unprotected public RAM to place an objects that require a full access from both cores */
50PUBLIC_RAM_SIZE = 0x800;
51
52/* Force symbol to be entered in the output file as an undefined symbol. Doing
53* this may, for example, trigger linking of additional modules from standard
54* libraries. You may list several symbols for each EXTERN, and you may use
55* EXTERN multiple times. This command has the same effect as the -u command-line
56* option.
57*/
58EXTERN(Reset_Handler)
59
60/* The MEMORY section below describes the location and size of blocks of memory in the target.
61* Use this section to specify the memory regions available for allocation.
62*/
63MEMORY
64{
65    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
66     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
67     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
68     * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'.
69     */
70    public_ram        (rw)    : ORIGIN = 0x08000000, LENGTH = PUBLIC_RAM_SIZE
71    ram               (rwx)   : ORIGIN = 0x08020000, LENGTH = 0xC000
72    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x10000
73
74    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
75     * You can assign sections to this memory region for only one of the cores.
76     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
77     * Therefore, repurposing this memory region will prevent such middleware from operation.
78     */
79    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
80
81    /* The following regions define device specific memory regions and must not be changed. */
82    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
83    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
84    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
85    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
86    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
87    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
88    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
89}
90
91/* Library configurations */
92GROUP(libgcc.a libc.a libm.a libnosys.a)
93
94/* Linker script to place sections and symbol values. Should be used together
95 * with other linker script that defines memory regions FLASH and RAM.
96 * It references following symbols, which must be defined in code:
97 *   Reset_Handler : Entry of reset handler
98 *
99 * It defines following symbols, which code can use without definition:
100 *   __exidx_start
101 *   __exidx_end
102 *   __copy_table_start__
103 *   __copy_table_end__
104 *   __zero_table_start__
105 *   __zero_table_end__
106 *   __etext
107 *   __data_start__
108 *   __preinit_array_start
109 *   __preinit_array_end
110 *   __init_array_start
111 *   __init_array_end
112 *   __fini_array_start
113 *   __fini_array_end
114 *   __data_end__
115 *   __bss_start__
116 *   __bss_end__
117 *   __end__
118 *   end
119 *   __HeapLimit
120 *   __StackLimit
121 *   __StackTop
122 *   __stack
123 *   __Vectors_End
124 *   __Vectors_Size
125 */
126
127
128SECTIONS
129{
130    .cy_app_header :
131    {
132        KEEP(*(.cy_app_header))
133    } > flash
134
135    /* Cortex-M0+ application flash area */
136    .text ORIGIN(flash) + BOOT_HEADER_SIZE :
137    {
138        . = ALIGN(4);
139        __Vectors = . ;
140        KEEP(*(.vectors))
141        . = ALIGN(4);
142        __Vectors_End = .;
143        __Vectors_Size = __Vectors_End - __Vectors;
144        __end__ = .;
145
146        . = ALIGN(4);
147        *(.text*)
148
149        KEEP(*(.init))
150        KEEP(*(.fini))
151
152        /* .ctors */
153        *crtbegin.o(.ctors)
154        *crtbegin?.o(.ctors)
155        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
156        *(SORT(.ctors.*))
157        *(.ctors)
158
159        /* .dtors */
160        *crtbegin.o(.dtors)
161        *crtbegin?.o(.dtors)
162        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
163        *(SORT(.dtors.*))
164        *(.dtors)
165
166        /* Read-only code (constants). */
167        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
168
169        KEEP(*(.eh_frame*))
170    } > flash
171
172
173    .ARM.extab :
174    {
175        *(.ARM.extab* .gnu.linkonce.armextab.*)
176    } > flash
177
178    __exidx_start = .;
179
180    .ARM.exidx :
181    {
182        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
183    } > flash
184    __exidx_end = .;
185
186
187    /* To copy multiple ROM to RAM sections,
188     * uncomment .copy.table section and,
189     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
190    .copy.table :
191    {
192        . = ALIGN(4);
193        __copy_table_start__ = .;
194
195        /* Copy interrupt vectors from flash to RAM */
196        LONG (__Vectors)                                    /* From */
197        LONG (__ram_vectors_start__)                        /* To   */
198        LONG (__Vectors_End - __Vectors)                    /* Size */
199
200        /* Copy data section to RAM */
201        LONG (__etext)                                      /* From */
202        LONG (__data_start__)                               /* To   */
203        LONG (__data_end__ - __data_start__)                /* Size */
204
205        __copy_table_end__ = .;
206    } > flash
207
208
209    /* To clear multiple BSS sections,
210     * uncomment .zero.table section and,
211     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
212    .zero.table :
213    {
214        . = ALIGN(4);
215        __zero_table_start__ = .;
216        LONG (__bss_start__)
217        LONG (__bss_end__ - __bss_start__)
218        __zero_table_end__ = .;
219    } > flash
220
221    __etext =  . ;
222
223
224    .ramVectors (NOLOAD) : ALIGN(8)
225    {
226        __ram_vectors_start__ = .;
227        KEEP(*(.ram_vectors))
228        __ram_vectors_end__   = .;
229    } > ram
230
231
232    .data __ram_vectors_end__ :
233    {
234        . = ALIGN(4);
235        __data_start__ = .;
236
237        *(vtable)
238        __sdata_start__ = .;
239        *(.data*)
240        __sdata_end__ = .;
241
242        . = ALIGN(4);
243        /* preinit data */
244        PROVIDE_HIDDEN (__preinit_array_start = .);
245        KEEP(*(.preinit_array))
246        PROVIDE_HIDDEN (__preinit_array_end = .);
247
248        . = ALIGN(4);
249        /* init data */
250        PROVIDE_HIDDEN (__init_array_start = .);
251        KEEP(*(SORT(.init_array.*)))
252        KEEP(*(.init_array))
253        PROVIDE_HIDDEN (__init_array_end = .);
254
255        . = ALIGN(4);
256        /* finit data */
257        PROVIDE_HIDDEN (__fini_array_start = .);
258        KEEP(*(SORT(.fini_array.*)))
259        KEEP(*(.fini_array))
260        PROVIDE_HIDDEN (__fini_array_end = .);
261
262        KEEP(*(.jcr*))
263        . = ALIGN(4);
264
265        KEEP(*(.cy_ramfunc*))
266        . = ALIGN(4);
267
268        __data_end__ = .;
269
270    } > ram AT>flash
271
272
273    /* Place variables in the section that should not be initialized during the
274    *  device startup.
275    */
276    .noinit (NOLOAD) : ALIGN(8)
277    {
278      KEEP(*(.noinit))
279    } > ram
280
281
282    /* The uninitialized global or static variables are placed in this section.
283    *
284    * The NOLOAD attribute tells linker that .bss section does not consume
285    * any space in the image. The NOLOAD attribute changes the .bss type to
286    * NOBITS, and that  makes linker to A) not allocate section in memory, and
287    * A) put information to clear the section with all zeros during application
288    * loading.
289    *
290    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
291    * This  makes linker to A) allocate zeroed section in memory, and B) copy
292    * this section to RAM during application loading.
293    */
294    .bss (NOLOAD):
295    {
296        . = ALIGN(4);
297        __bss_start__ = .;
298        *(.bss*)
299        *(COMMON)
300        . = ALIGN(4);
301        __bss_end__ = .;
302    } > ram
303
304
305    .heap (NOLOAD):
306    {
307        __HeapBase = .;
308        __end__ = .;
309        end = __end__;
310        KEEP(*(.heap*))
311        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
312        __HeapLimit = .;
313    } > ram
314
315
316    /* Unprotected public RAM */
317    .cy_sharedmem (NOLOAD):
318    {
319        . = ALIGN(4);
320        __public_ram_start__ = .;
321        KEEP(*(.cy_sharedmem))
322        . = ALIGN(4);
323        __public_ram_end__ = .;
324    } > public_ram
325
326
327    /* .stack_dummy section doesn't contains any symbols. It is only
328     * used for linker to calculate size of stack sections, and assign
329     * values to stack symbols later */
330    .stack_dummy (NOLOAD):
331    {
332        KEEP(*(.stack*))
333    } > ram
334
335
336    /* Set stack top to end of RAM, and stack limit move down by
337     * size of stack_dummy section */
338    __StackTop = ORIGIN(ram) + LENGTH(ram);
339    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
340    PROVIDE(__stack = __StackTop);
341
342    /* Check if data + heap + stack exceeds RAM limit */
343    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
344
345
346    /* Emulated EEPROM Flash area */
347    .cy_em_eeprom :
348    {
349        KEEP(*(.cy_em_eeprom))
350    } > em_eeprom
351
352
353    /* Supervisory Flash: User data */
354    .cy_sflash_user_data :
355    {
356        KEEP(*(.cy_sflash_user_data))
357    } > sflash_user_data
358
359
360    /* Supervisory Flash: Normal Access Restrictions (NAR) */
361    .cy_sflash_nar :
362    {
363        KEEP(*(.cy_sflash_nar))
364    } > sflash_nar
365
366
367    /* Supervisory Flash: Public Key */
368    .cy_sflash_public_key :
369    {
370        KEEP(*(.cy_sflash_public_key))
371    } > sflash_public_key
372
373
374    /* Supervisory Flash: Table of Content # 2 */
375    .cy_toc_part2 :
376    {
377        KEEP(*(.cy_toc_part2))
378    } > sflash_toc_2
379
380
381    /* Supervisory Flash: Table of Content # 2 Copy */
382    .cy_rtoc_part2 :
383    {
384        KEEP(*(.cy_rtoc_part2))
385    } > sflash_rtoc_2
386
387
388    /* Places the code in the Execute in Place (XIP) section. See the smif driver
389    *  documentation for details.
390    */
391    cy_xip :
392    {
393        __cy_xip_start = .;
394        KEEP(*(.cy_xip))
395        __cy_xip_end = .;
396    } > xip
397
398
399    /* eFuse */
400    .cy_efuse :
401    {
402        KEEP(*(.cy_efuse))
403    } > efuse
404
405
406    /* These sections are used for additional metadata (silicon revision,
407    *  Silicon/JTAG ID, etc.) storage.
408    */
409    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
410}
411
412
413/* The following symbols used by the cymcuelftool. */
414/* Flash */
415__cy_memory_0_start    = 0x10000000;
416__cy_memory_0_length   = 0x000D0000;
417__cy_memory_0_row_size = 0x200;
418
419/* Emulated EEPROM Flash area */
420__cy_memory_1_start    = 0x14000000;
421__cy_memory_1_length   = 0x8000;
422__cy_memory_1_row_size = 0x200;
423
424/* Supervisory Flash */
425__cy_memory_2_start    = 0x16000000;
426__cy_memory_2_length   = 0x8000;
427__cy_memory_2_row_size = 0x200;
428
429/* XIP */
430__cy_memory_3_start    = 0x18000000;
431__cy_memory_3_length   = 0x08000000;
432__cy_memory_3_row_size = 0x200;
433
434/* eFuse */
435__cy_memory_4_start    = 0x90700000;
436__cy_memory_4_length   = 0x100000;
437__cy_memory_4_row_size = 1;
438
439/* EOF */
440