1 /***************************************************************************//**
2 * \file cy_wdt.h
3 * \version 1.60
4 *
5 * This file provides constants and parameter values for the WDT driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *
25 *******************************************************************************/
26
27 /**
28 * \addtogroup group_wdt
29 * \{
30 *
31 * The Watchdog timer (WDT) has a 16-bit free-running up-counter.
32 *
33 * The functions and other declarations used in this driver are in cy_wdt.h.
34 * You can include cy_pdl.h to get access to all functions
35 * and declarations in the PDL.
36 *
37 * The WDT can issue counter match interrupts, and a device reset if its interrupts are not
38 * handled. Use the Watchdog timer for two main purposes:
39 *
40 * The <b> First use case </b> is recovering from a CPU or firmware failure.
41 * A timeout period is set up in the Watchdog timer, and if a timeout occurs, the
42 * device is reset (WRES). <br>
43 * The <b>Second use case</b> is to generate periodic interrupts.
44 * It is strongly recommended not to use the WDT for periodic interrupt
45 * generation. However, if absolutely required, see information below.
46 *
47 * A "reset cause" register(RES_CAUSE, Part of SRSS IP) exists, and the firmware should
48 * check this register at a start-up. An appropriate action can be taken if a WRES
49 * reset is detected.
50 *
51 * The user's firmware periodically resets the timeout period (clears or "feeds"
52 * the watchdog) before a timeout occurs. If the firmware fails to do so, that is
53 * considered to be a CPU crash or a firmware failure, and the reason for a
54 * device reset.
55 * The WDT can generate an interrupt instead of a device reset. The Interrupt
56 * Service Routine (ISR) can handle the interrupt either as a periodic interrupt,
57 * or as an early indication of a firmware failure and respond accordingly.
58 * However, it is not recommended to use the WDT for periodic interrupt
59 * generation. The Multi-counter Watchdog Timers (MCWDT) can be used to generate
60 * periodic interrupts if such are presented in the device.
61 *
62 * <b> Functional Description </b>
63 *
64 * The WDT generates an interrupt when the count value in the counter equals the
65 * configured match value.
66 *
67 * Note that the counter is not reset on a match. In such case the WDT
68 * reset period is:
69 * WDT_Reset_Period = ILO_Period * (2*2^(16-IgnoreBits) + MatchValue);
70 * When the counter reaches a match value, it generates an interrupt and then
71 * keeps counting up until it overflows and rolls back to zero and reaches the
72 * match value again, at which point another interrupt is generated.
73 *
74 * To use a WDT to generate a periodic interrupt, the match value should be
75 * incremented in the ISR. As a result, the next WDT interrupt is generated when
76 * the counter reaches a new match value.
77 *
78 * You can also reduce the entire WDT counter period by
79 * specifying the number of most significant bits that are ignored in the WDT
80 * counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with
81 * parameter 3, the WDT counter becomes a 13-bit free-running up-counter.
82 *
83 * <b> Power Modes </b>
84 *
85 * WDT can operate in all possible low power modes.
86 * Operation during Hibernate mode is possible because the logic and
87 * high-voltage internal low oscillator (ILO) are supplied by the external
88 * high-voltage supply (Vddd). The WDT can be configured to wake the device from
89 * Hibernate mode.
90 *
91 * In CPU Active mode, an interrupt request from the WDT is sent to the
92 * CPU. In CPU Sleep, CPU Deep Sleep mode, the CPU subsystem
93 * is powered down, so the interrupt request from the WDT is sent directly to the
94 * WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The
95 * CPU then acknowledges the interrupt request and executes the ISR.
96 *
97 * <b> Clock Source </b>
98 *
99 * The WDT is clocked by the ILO. The WDT must be disabled before disabling
100 * the ILO. According to the device datasheet, the ILO accuracy is +/-30% over
101 * voltage and temperature. This means that the timeout period may vary by 30%
102 * from the configured value. Appropriate margins should be added while
103 * configuring WDT intervals to make sure that unwanted device resets do not
104 * occur on some devices.
105 *
106 * Refer to the device datasheet for more information on the oscillator accuracy.
107 *
108 * <b> Register Locking </b>
109 *
110 * You can prevent accidental corruption of the WDT configuration by calling
111 * the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*,
112 * CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is
113 * ignored.
114 * Call the Cy_WDT_Unlock() function to allow registers modification, mentioned
115 * above.
116 *
117 * Note that the WDT lock state is not retained during system Deep Sleep. After
118 * the wakeup from system Deep Sleep the WDT is locked.
119 *
120 * <b> Clearing WDT </b>
121 *
122 * The ILO clock is asynchronous to the SysClk. Therefore it generally
123 * takes three ILO cycles for WDT register changes to come into effect. It is
124 * important to remember that a WDT should be cleared at least four cycles
125 * (3 + 1 for sure) before a timeout occurs, especially when small
126 * match values / low-toggle bit numbers are used.
127 *
128 * \warning It may happen that a WDT reset can be generated
129 * faster than a device start-up. To prevent this, calculate the
130 * start-up time and WDT reset time. The WDT reset time should be always greater
131 * than device start-up time.
132 *
133 * <b> Reset Detection </b>
134 *
135 * Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has
136 * triggered a device reset.
137 *
138 * <b> Interrupt Configuration </b>
139 *
140 * If the WDT is configured to generate an interrupt, pending
141 * interrupts must be cleared within the ISR (otherwise, the interrupt will be
142 * generated continuously).
143 * A pending interrupt to the WDT block must be cleared by calling the
144 * Cy_WDT_ClearInterrupt() function. The call to the function will clear the
145 * unhandled WDT interrupt counter.
146 *
147 * Use the WDT ISR as a timer to trigger certain actions
148 * and to change a next WDT match value.
149 *
150 * Ensure that the interrupts from the WDT are passed to the CPU to avoid
151 * unregistered interrupts. Unregistered WDT interrupts result in a continuous
152 * device reset. To avoid this, call Cy_WDT_UnmaskInterrupt().
153 * After that, call the WDT API functions for interrupt
154 * handling/clearing.
155 *
156 * \section group_wdt_configuration Configuration Considerations
157 *
158 * To start the WDT, make sure that ILO is enabled.
159 * After the ILO is enabled, ensure that the WDT is unlocked and disabled by
160 * calling the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match
161 * value by calling Cy_WDT_SetMatch() with the required match value. If needed,
162 * set the ignore bits for reducing the WDT counter period by calling
163 * Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set,
164 * call Cy_WDT_Enable().
165 *
166 * \note Enable a WDT if the power supply can produce
167 * sudden brownout events that may compromise the CPU functionality. This
168 * ensures that the system can recover after a brownout.
169 *
170 * When the WDT is used to protect against system crashes, the
171 * WDT interrupt should be cleared by a portion of the code that is not directly
172 * associated with the WDT interrupt.
173 * Otherwise, it is possible that the main firmware loop has crashed or is in an
174 * endless loop, but the WDT interrupt vector continues to operate and service
175 * the WDT. The user should:
176 * * Feed the watchdog by clearing the interrupt bit regularly in the main body
177 * of the firmware code.
178 *
179 * * Guarantee that the interrupt is cleared at least once every WDT period.
180 *
181 * * Use the WDT ISR only as a timer to trigger certain actions and to change the
182 * next match value.
183 *
184 * \section group_wdt_section_more_information More Information
185 *
186 * For more information on the WDT peripheral, refer to the technical reference
187 * manual (TRM).
188 *
189 * \section group_wdt_changelog Changelog
190 * <table class="doxtable">
191 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
192 * <tr>
193 * <td>1.60</td>
194 * <td>Updated \ref cy_en_wdt_clk_sources_t enum and added support for CAT1D.</td>
195 * <td>Code Enhancement and new device support added.</td>
196 * </tr>
197 * <tr>
198 * <td>1.50</td>
199 * <td>Added WDT_B type support required for CAT1C devices.<br>Newly added APIs:
200 * \n Cy_WDT_SetLowerLimit(),
201 * \n Cy_WDT_SetUpperLimit(),
202 * \n Cy_WDT_SetWarnLimit(),
203 * \n Cy_WDT_SetLowerAction(),
204 * \n Cy_WDT_SetUpperAction(),
205 * \n Cy_WDT_SetWarnAction(),
206 * \n Cy_WDT_SetAutoService(),
207 * \n Cy_WDT_SetDeepSleepPause(),
208 * \n Cy_WDT_SetHibernatePause(),
209 * \n Cy_WDT_SetDebugRun(),
210 * \n Cy_WDT_SetService(),
211 * <td>Support for new devices.</td>
212 * </tr>
213 * <tr>
214 * <td>1.40</td>
215 * <td>CAT1B, CAT1C devices support.<br>
216 * Newly added API's Cy_WDT_SetClkSource() to configure the WDT clock source, Cy_WDT_GetClkSource() to get the WDT clock source configured,
217 * Cy_WDT_SetMatchBits() to configure the bit position above which the bits will be ignored for match, Cy_WDT_GetMatchBits() to get the bit position above which the bits will be ignored for match.</td>
218 * <td>Support for new devices.</td>
219 * </tr>
220 * <tr>
221 * <td>1.30.1</td>
222 * <td>Minor documentation updates.</td>
223 * <td>Removed MISRA 2004 compliance details and verified MISRA 2012 compliance.</td>
224 * </tr>
225 * <tr>
226 * <td rowspan="2">1.30</td>
227 * <td>Updated the following functions for the PSoC 64 devices: \ref Cy_WDT_ClearInterrupt(),
228 * \ref Cy_WDT_MaskInterrupt(), and \ref Cy_WDT_UnmaskInterrupt().</td>
229 * <td>Added PSoC 64 device support.</td>
230 * </tr>
231 * <tr>
232 * <td>Minor documentation updates.</td>
233 * <td>Documentation enhancement.</td>
234 * </tr>
235 * <tr>
236 * <td>1.20</td>
237 * <td>Added a new API function \ref Cy_WDT_IsEnabled() </td>
238 * <td>Enhancement based on usability feedback.</td>
239 * </tr>
240 * <tr>
241 * <td>1.10.1</td>
242 * <td>Added info that the WDT lock state is not retained during
243 * system Deep Sleep power mode.
244 * </td>
245 * <td>Documentation updates.</td>
246 * </tr>
247 * <tr>
248 * <td rowspan="4">1.10</td>
249 * <td>Flattened the organization of the driver source code into the single
250 * source directory and the single include directory.
251 * </td>
252 * <td>Driver library directory-structure simplification.</td>
253 * </tr>
254 * <tr>
255 * <td> Removed critical section usage in the following functions:
256 * - \ref Cy_WDT_Init()
257 * - \ref Cy_WDT_Lock()
258 * - \ref Cy_WDT_Unlock()
259 * </td>
260 * <td>Driver functions simplification</td>
261 * </tr>
262 * <tr>
263 * <td>Updated the \ref Cy_WDT_Init(), \ref Cy_WDT_Enable() to clear WDT interrupt.</td>
264 * <td>Corner case reliability improvements</td>
265 * </tr>
266 * <tr>
267 * <td>Added register access layer. Use register access macros instead
268 * of direct register access using dereferenced pointers.</td>
269 * <td>Makes register access device-independent, so that the PDL does
270 * not need to be recompiled for each supported part number.</td>
271 * </tr>
272 * <tr>
273 * <td>1.0.2</td>
274 * <td>Minor documentation updates</td>
275 * <td>Corrected info about a reset generation</td>
276 * </tr>
277 * <tr>
278 * <td>1.0.1</td>
279 * <td>General documentation updates</td>
280 * <td>Added info about periodic interrupt generation use case</td>
281 * </tr>
282 * <tr>
283 * <td>1.0</td>
284 * <td>Initial version</td>
285 * <td></td>
286 * </tr>
287 * </table>
288 *
289 * \defgroup group_wdt_macros Macros
290 * \defgroup group_wdt_clk_src_enums Enums
291 * \defgroup group_wdt_functions Functions
292 *
293 */
294
295 #if !defined(CY_WDT_H)
296 #define CY_WDT_H
297
298 #include "cy_device.h"
299
300 #if defined (CY_IP_MXS28SRSS)|| defined (CY_IP_MXS40SSRSS ) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS)
301
302 #include <stdint.h>
303 #include <stdbool.h>
304 #include "cy_syslib.h"
305 #if defined(CY_DEVICE_SECURE)
306 #include "cy_pra.h"
307 #endif /* defined(CY_DEVICE_SECURE) */
308
309
310 #if defined(__cplusplus)
311 extern "C" {
312 #endif
313
314
315 /*******************************************************************************
316 * Function Constants
317 *******************************************************************************/
318
319 /**
320 * \addtogroup group_wdt_macros
321 * \{
322 */
323
324 /** The driver major version */
325 #define CY_WDT_DRV_VERSION_MAJOR 1
326
327 /** The driver minor version */
328 #define CY_WDT_DRV_VERSION_MINOR 60
329
330 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
331 /** The internal define for the first iteration of WDT unlocking */
332 #define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01U)
333
334 /** The internal define for the second iteration of WDT unlocking */
335 #define CY_SRSS_WDT_LOCK_BIT1 ((uint32_t)0x02U)
336 #else
337 /** The internal define for the first iteration of WDT unlocking */
338 #define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01U << 30U)
339
340 /** The internal define for the second iteration of WDT unlocking */
341 #define CY_SRSS_WDT_LOCK_BIT1 ((uint32_t)0x01U << 31U)
342 #endif
343
344 /** The WDT default match value */
345 #define CY_SRSS_WDT_DEFAULT_MATCH_VALUE ((uint32_t) 4096U)
346
347 /** The default match value of the WDT ignore bits */
348 #define CY_SRSS_WDT_DEFAULT_IGNORE_BITS (0U)
349
350 /** The default match value of the WDT ignore bits */
351 #define CY_SRSS_WDT_LOCK_BITS (3U)
352
353 /** The WDT driver identifier */
354 #define CY_WDT_ID CY_PDL_DRV_ID(0x34U)
355
356 /** \cond Internal */
357
358 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
359 /** The WDT maximum match value */
360 #define WDT_MAX_MATCH_VALUE ((0xFFFFFFFFuL) >> (32 - SRSS_NUM_WDT_A_BITS))
361 /* Internal macro to validate match value */
362 #define CY_WDT_IS_IGNORE_BITS_ABOVE_VALID(bitPos) ((bitPos) < SRSS_NUM_WDT_A_BITS)
363
364 #else
365 /** The WDT maximum match value */
366 #define WDT_MAX_MATCH_VALUE (0xFFFFuL)
367 #endif
368
369 /** The WDT maximum Ignore Bits */
370 #define WDT_MAX_IGNORE_BITS (0xFuL)
371
372 /* Internal macro to validate match value */
373 #define CY_WDT_IS_MATCH_VAL_VALID(match) ((match) <= WDT_MAX_MATCH_VALUE)
374
375 /* Internal macro to validate match value */
376 #define CY_WDT_IS_IGNORE_BITS_VALID(bitsNum) ((bitsNum) <= WDT_MAX_IGNORE_BITS)
377
378 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
379 /** The WDT default match value */
380 /**
381 * \note
382 * This Macro is available for CAT1C devices.
383 **/
384 #define CY_WDT_DEFAULT_MATCH_VALUE (32000UL) // 1 sec when clk_lf = 32KHz
385
386 /** The WDT default LOWER_LIMIT value */
387 /**
388 * \note
389 * This Macro is available for CAT1C devices.
390 **/
391 #define CY_WDT_DEFAULT_LOWER_LIMIT (0U)
392
393 /** The WDT default UPPER_LIMIT value */
394 /**
395 * \note
396 * This Macro is available for CAT1C devices.
397 **/
398 #define CY_WDT_DEFAULT_UPPER_LIMIT CY_WDT_DEFAULT_MATCH_VALUE
399
400 /** The WDT default WARN_LIMIT value */
401 /**
402 * \note
403 * This Macro is available for CAT1C devices.
404 **/
405 #define CY_WDT_DEFAULT_WARN_LIMIT (0U)
406 #endif
407
408 /**
409 * \note
410 * This Macro is available for CAT1B and CAT1D devices.
411 **/
412 #if defined (CY_IP_MXS22SRSS)
413 /* Internal macro to validate match value */
414 #define CY_WDT_IS_CLK_SRC_VALID(src) (((src) == CY_WDT_CLK_SOURCE_PILO) || \
415 ((src) == CY_WDT_CLK_SOURCE_BAK))
416 #elif defined (CY_IP_MXS40SSRSS)
417 /* Internal macro to validate match value */
418 #define CY_WDT_IS_CLK_SRC_VALID(src) (((src) == CY_WDT_CLK_SOURCE_ILO) || \
419 ((src) == CY_WDT_CLK_SOURCE_PILO) || \
420 ((src) == CY_WDT_CLK_SOURCE_BAK))
421 #endif
422
423 /** \endcond */
424 /** \} group_wdt_macros */
425 /**
426 * \addtogroup group_wdt_clk_src_enums
427 * \{
428 */
429
430 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) ||defined (CY_DOXYGEN)
431 /**
432 * \note
433 * This enum is available for CAT1B and CAT1D devices.
434 **/
435
436 typedef enum
437 {
438 #if defined (CY_IP_MXS40SSRSS)
439 CY_WDT_CLK_SOURCE_ILO = 0U, /**< Select the ILO as clock source to WDT */
440 #endif
441 CY_WDT_CLK_SOURCE_PILO = 1U, /**< Select the PILO as clock source to WDT */
442 CY_WDT_CLK_SOURCE_BAK = 2U, /**< Select the clk_bak as clock source to WDT */
443 } cy_en_wdt_clk_sources_t;
444 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) ||defined (CY_DOXYGEN) */
445
446 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
447 /** The wdt lower/upper limit actions. */
448 /**
449 * \note
450 * This Enum is available for CAT1C devices.
451 **/
452 typedef enum
453 {
454 CY_WDT_LOW_UPPER_LIMIT_ACTION_NONE,
455 CY_WDT_LOW_UPPER_LIMIT_ACTION_RESET
456 } cy_en_wdt_lower_upper_action_t;
457
458 /** The wdt lower/upper limit actions. */
459 /**
460 * \note
461 * This Enum is available for CAT1C devices.
462 **/
463 typedef enum
464 {
465 CY_WDT_WARN_ACTION_NONE,
466 CY_WDT_WARN_ACTION_INT
467 } cy_en_wdt_warn_action_t;
468
469 /** The wdt Disable/Enable Macros. */
470 /**
471 * \note
472 * This Enum is available for CAT1C devices.
473 **/
474 typedef enum
475 {
476 CY_WDT_DISABLE,
477 CY_WDT_ENABLE
478 } cy_en_wdt_enable_t;
479 #endif
480
481 /** \} group_wdt_clk_src_enums */
482
483
484 /*******************************************************************************
485 * Function Prototypes
486 *******************************************************************************/
487 /**
488 * \addtogroup group_wdt_functions
489 * @{
490 */
491 /* WDT API */
492 void Cy_WDT_Init(void);
493 void Cy_WDT_Lock(void);
494 void Cy_WDT_Unlock(void);
495 bool Cy_WDT_Locked(void);
496 void Cy_WDT_ClearInterrupt(void);
497 void Cy_WDT_ClearWatchdog(void);
498
499 __STATIC_INLINE void Cy_WDT_Enable(void);
500 __STATIC_INLINE void Cy_WDT_Disable(void);
501 __STATIC_INLINE bool Cy_WDT_IsEnabled(void);
502 __STATIC_INLINE uint32_t Cy_WDT_GetCount(void);
503 __STATIC_INLINE void Cy_WDT_MaskInterrupt(void);
504 __STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void);
505
506 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) || defined (CY_IP_MXS22SRSS)
507 void Cy_WDT_SetMatch(uint32_t match);
508 void Cy_WDT_SetIgnoreBits(uint32_t bitsNum);
509 __STATIC_INLINE uint32_t Cy_WDT_GetMatch(void);
510 __STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void);
511
512 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) ||defined (CY_DOXYGEN)
513 void Cy_WDT_SetMatchBits(uint32_t bitPos);
514 __STATIC_INLINE void Cy_WDT_SetClkSource(cy_en_wdt_clk_sources_t src);
515 __STATIC_INLINE cy_en_wdt_clk_sources_t Cy_WDT_GetClkSource(void);
516 __STATIC_INLINE uint32_t Cy_WDT_GetMatchBits(void);
517 #endif
518
519 #endif
520
521 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
522 void Cy_WDT_SetLowerLimit(uint32_t match);
523 void Cy_WDT_SetUpperLimit(uint32_t match);
524 void Cy_WDT_SetWarnLimit(uint32_t match);
525 void Cy_WDT_SetLowerAction(cy_en_wdt_lower_upper_action_t action);
526 void Cy_WDT_SetUpperAction(cy_en_wdt_lower_upper_action_t action);
527 void Cy_WDT_SetWarnAction(cy_en_wdt_warn_action_t action);
528 void Cy_WDT_SetAutoService(cy_en_wdt_enable_t enable);
529 void Cy_WDT_SetDeepSleepPause(cy_en_wdt_enable_t enable);
530 void Cy_WDT_SetHibernatePause(cy_en_wdt_enable_t enable);
531 void Cy_WDT_SetDebugRun(cy_en_wdt_enable_t enable);
532 void Cy_WDT_SetService(void);
533 #endif
534
535
536 /*******************************************************************************
537 * Function Name: Cy_WDT_Enable
538 ****************************************************************************//**
539 *
540 * Enables the Watchdog timer.
541 *
542 * \sideeffect
543 * This function clears the WDT interrupt.
544 *
545 *******************************************************************************/
Cy_WDT_Enable(void)546 __STATIC_INLINE void Cy_WDT_Enable(void)
547 {
548 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
549 SRSS_WDT_CTL |= WDT_CTL_ENABLE_Msk;
550 #else
551 SRSS_WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U);
552 #endif
553
554 Cy_WDT_ClearInterrupt();
555 }
556
557
558 /*******************************************************************************
559 * Function Name: Cy_WDT_Disable
560 ****************************************************************************//**
561 *
562 * Disables the Watchdog timer. The Watchdog timer should be unlocked before being
563 * disabled. Call the Cy_WDT_Unlock() API to unlock the WDT.
564 *
565 *******************************************************************************/
Cy_WDT_Disable(void)566 __STATIC_INLINE void Cy_WDT_Disable(void)
567 {
568 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
569 SRSS_WDT_CTL &= ((uint32_t) ~(_VAL2FLD(WDT_CTL_ENABLE, 1U)));
570 #else
571 SRSS_WDT_CTL &= ((uint32_t) ~(_VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1U)));
572 #endif
573 }
574
575
576 /*******************************************************************************
577 * Function Name: Cy_WDT_IsEnabled
578 ****************************************************************************//**
579 *
580 * Reports an enable/disable state of the Watchdog timer.
581 *
582 * \return
583 * - true - if the timer is enabled
584 * - false - if the timer is disabled
585 *
586 *******************************************************************************/
Cy_WDT_IsEnabled(void)587 __STATIC_INLINE bool Cy_WDT_IsEnabled(void)
588 {
589 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
590 return _FLD2BOOL(WDT_CTL_ENABLE, SRSS_WDT_CTL);
591 #else
592 return _FLD2BOOL(SRSS_WDT_CTL_WDT_EN, SRSS_WDT_CTL);
593 #endif
594 }
595
596 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) || defined (CY_IP_MXS22SRSS)
597
598 /*******************************************************************************
599 * Function Name: Cy_WDT_GetMatch
600 ****************************************************************************//**
601 *
602 * Reads the WDT counter match comparison value.
603 *
604 * \return The counter match value.
605 *
606 * \note
607 * This API is available for CAT1A, CAT1B and CAT1D devices.
608 *
609 *******************************************************************************/
Cy_WDT_GetMatch(void)610 __STATIC_INLINE uint32_t Cy_WDT_GetMatch(void)
611 {
612 return ((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_MATCH, SRSS_WDT_MATCH));
613 }
614
615 /*******************************************************************************
616 * Function Name: Cy_WDT_GetIgnoreBits
617 ****************************************************************************//**
618 *
619 * Reads the number of the most significant bits of the Watchdog timer that are
620 * not checked against the match.
621 *
622 * \return The number of the most significant bits.
623 *
624 * \note
625 * This API is available for CAT1A, CAT1B and CAT1D devices.
626 *
627 *******************************************************************************/
Cy_WDT_GetIgnoreBits(void)628 __STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void)
629 {
630 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
631 return((uint32_t) (WDT_MAX_IGNORE_BITS - _FLD2VAL(SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, SRSS_WDT_MATCH2)));
632 #else
633 return((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_IGNORE_BITS, SRSS_WDT_MATCH));
634 #endif
635 }
636
637 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
638 /*******************************************************************************
639 * Function Name: Cy_WDT_SetClkSource
640 ****************************************************************************//**
641 *
642 * Configures the WDT clock source
643 *
644 * \param src
645 * \ref cy_en_wdt_clk_sources_t
646 *
647 * \note
648 * This API is available for CAT1B and CAT1D devices.
649 *
650 * \note It takes four cycles of the originally selected clock to switch away
651 * from it. Do not disable the original clock during this time.
652 *
653 *******************************************************************************/
Cy_WDT_SetClkSource(cy_en_wdt_clk_sources_t src)654 __STATIC_INLINE void Cy_WDT_SetClkSource(cy_en_wdt_clk_sources_t src)
655 {
656 CY_ASSERT_L2(CY_WDT_IS_CLK_SRC_VALID(src));
657
658 if (false == Cy_WDT_Locked())
659 {
660 SRSS_WDT_CTL = _CLR_SET_FLD32U((SRSS_WDT_CTL), SRSS_WDT_CTL_WDT_CLK_SEL, src);
661 }
662 }
663
664 /*******************************************************************************
665 * Function Name: Cy_WDT_GetClkSource
666 ****************************************************************************//**
667 *
668 * Gets the WDT clock source configured.
669 *
670 * \return The Clock source enum \ref cy_en_wdt_clk_sources_t
671 *
672 * \note
673 * This API is available for CAT1B and CAT1D devices.
674 *
675 *******************************************************************************/
Cy_WDT_GetClkSource(void)676 __STATIC_INLINE cy_en_wdt_clk_sources_t Cy_WDT_GetClkSource(void)
677 {
678 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_wdt_clk_sources_t enum.');
679 return ((cy_en_wdt_clk_sources_t) _FLD2VAL(SRSS_WDT_CTL_WDT_CLK_SEL, SRSS_WDT_CTL));
680 }
681
682 /*******************************************************************************
683 * Function Name: Cy_WDT_GetMatchBits
684 ****************************************************************************//**
685 *
686 * Gets the bit position above which the bits will be ignored for match.
687 *
688 * \return The bit position above which the bits will be ignored for match.
689 *
690 * \note
691 * This API is available for CAT1B and CAT1D devices.
692 *
693 *******************************************************************************/
Cy_WDT_GetMatchBits(void)694 __STATIC_INLINE uint32_t Cy_WDT_GetMatchBits(void)
695 {
696 return((uint32_t) (_FLD2VAL(SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, SRSS_WDT_MATCH2)));
697 }
698 #endif
699
700 #endif /*defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) */
701
702
703 /*******************************************************************************
704 * Function Name: Cy_WDT_GetCount
705 ****************************************************************************//**
706 *
707 * Reads the current WDT counter value.
708 *
709 * \return A live counter value.
710 *
711 *******************************************************************************/
Cy_WDT_GetCount(void)712 __STATIC_INLINE uint32_t Cy_WDT_GetCount(void)
713 {
714 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
715 return ((uint32_t) _FLD2VAL(WDT_CNT_CNT, SRSS_WDT_CNT));
716 #else
717 return ((uint32_t) _FLD2VAL(SRSS_WDT_CNT_COUNTER, SRSS_WDT_CNT));
718 #endif
719 }
720
721
722 /*******************************************************************************
723 * Function Name: Cy_WDT_MaskInterrupt
724 ****************************************************************************//**
725 *
726 * After masking interrupts from the WDT, they are not passed to the CPU.
727 * This function does not disable the WDT-reset generation.
728 *
729 *******************************************************************************/
Cy_WDT_MaskInterrupt(void)730 __STATIC_INLINE void Cy_WDT_MaskInterrupt(void)
731 {
732 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
733 SRSS_WDT_INTR_MASK &= ~WDT_INTR_MASK_WDT_Msk;
734 #else
735 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE)
736 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 0U);
737 #else
738 SRSS_SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U));
739 #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */
740 #endif
741 }
742
743
744 /*******************************************************************************
745 * Function Name: Cy_WDT_UnmaskInterrupt
746 ****************************************************************************//**
747 *
748 * After unmasking interrupts from the WDT, they are passed to CPU.
749 * This function does not impact the reset generation.
750 *
751 *******************************************************************************/
Cy_WDT_UnmaskInterrupt(void)752 __STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void)
753 {
754 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
755 SRSS_WDT_INTR_MASK |= WDT_INTR_MASK_WDT_Msk;
756 #else
757 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE)
758 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U);
759 #else
760 SRSS_SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U);
761 #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */
762 #endif
763 }
764 /** \} group_wdt_functions */
765
766 #if defined(__cplusplus)
767 }
768 #endif
769
770 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SRSS */
771
772 #endif /* CY_WDT_H */
773
774 /** \} group_wdt */
775
776
777 /* [] END OF FILE */
778
