1 /***************************************************************************//**
2 * \file cy_syslib.h
3 * \version 3.60
4 *
5 * Provides an API declaration of the SysLib driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_syslib
28 * \{
29 * The system libraries provide APIs that can be called in the user application
30 * to handle the timing, logical checking or register.
31 *
32 * The functions and other declarations used in this driver are in cy_syslib.h.
33 * You can include cy_pdl.h to get access to all functions
34 * and declarations in the PDL.
35 *
36 * The SysLib driver contains a set of different system functions. These functions
37 * can be called in the application routine. Major features of the system library:
38 * * Delay functions
39 * * The register Read/Write macro
40 * * Assert and Halt
41 * * Assert Classes and Levels
42 * * A software reset
43 * * Reading the reset cause
44 * * An API to invalidate the flash cache and buffer
45 * * Data manipulation macro
46 * * A variable type definition from MISRA-C which specifies signedness
47 * * Cross compiler compatible attributes
48 * * Getting a silicon-unique ID API
49 * * Setting wait states API
50 * * Resetting the backup domain API
51 * * APIs to serve Fault handler
52 *
53 * \section group_syslib_configuration Configuration Considerations
54 * <b> Assertion Usage </b> <br />
55 * Use the CY_ASSERT() macro to check expressions that must be true if the
56 * program is running correctly. It is a convenient way to insert sanity checks.
57 * The CY_ASSERT() macro is defined in the cy_utils.h file, which is part of the
58 * <a href="https://github.com/Infineon/core-lib">Cypress Core Library (core-lib)</a>.
59 * The macro behavior is as follows: if the expression passed
60 * to the macro is false, the CPU is halted. \n
61 *
62 * Starting from the driver version 2.50, the CY_ASSERT macro was moved
63 * to the Cypress Core Library (core-lib). Also, the CY_ASSERT implementation
64 * was changed not to call Cy_SysLib_AssertFailed() function, so user application
65 * that relied on that should take this change into account. \n
66 *
67 *
68 * The PDL source code uses this assert mechanism extensively. It is recommended
69 * that you enable asserts when debugging firmware. \n
70 * <b> Assertion Classes and Levels </b> <br />
71 * The <a href="https://github.com/Infineon/core-lib">Cypress Core Library</a>
72 * defines three assert classes, which correspond to different
73 * kinds of parameters. There is a corresponding assert "level" for each class.
74 * <table class="doxtable">
75 * <tr><th>Class Macro</th><th>Level Macro</th><th>Type of check</th></tr>
76 * <tr>
77 * <td>CY_ASSERT_CLASS_1</td>
78 * <td>CY_ASSERT_L1</td>
79 * <td>A parameter that could change between different PSoC devices
80 * (e.g. the number of clock paths)</td>
81 * </tr>
82 * <tr>
83 * <td>CY_ASSERT_CLASS_2</td>
84 * <td>CY_ASSERT_L2</td>
85 * <td>A parameter that has fixed limits such as a counter period</td>
86 * </tr>
87 * <tr>
88 * <td>CY_ASSERT_CLASS_3</td>
89 * <td>CY_ASSERT_L3</td>
90 * <td>A parameter that is an enum constant</td>
91 * </tr>
92 * </table>
93 * Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL.
94 * This is a compiler command line argument, similar to how the DEBUG / NDEBUG
95 * macro is passed. \n
96 * Enabling any class also enables any lower-numbered class.
97 * CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three
98 * classes. The following example shows the command-line option to enable all
99 * the assert levels:
100 * \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode
101 * \note The use of special characters, such as spaces, parenthesis, etc. must
102 * be protected with quotes.
103 *
104 * After CY_ASSERT_LEVEL is defined, firmware can use
105 * one of the three level macros to make an assertion. For example, if the
106 * parameter can vary between devices, firmware uses the L1 macro.
107 * \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode
108 * If the parameter has bounds, firmware uses L2.
109 * \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode
110 * If the parameter is an enum, firmware uses L3.
111 * \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode
112 * Each check uses the appropriate level macro for the kind of parameter being checked.
113 * If a particular assert class/level is not enabled, then the assert does nothing.
114 *
115 * <b> Delay Functions </b> <br />
116 * Delay functions are supported with different flavors of delays and are implemented
117 * by executing known instructions in a loop considering the CPU cycles consumed by these
118 * instructions to execute. The loop count is calculated based on the amount of delay required.
119 * Cycles taken for the execution of instructions has a direct impact on the
120 * accuracy of the delay. For the best accuracy of delay, these functions need to be executed
121 * from the single cycle memory. CAT1B, CAT1C and CAT1D devices have I-Cache which
122 * ensures the accuracy of the delay as the loop executes from the I-Cache. However,
123 * for the devices without I-Cache, user needs to move these functions to faster memory,
124 * such as SRAM using appropriate memory section directive listed in the cy_syslib.h file.
125 * On devices with CM33 Core, user must ensure that the code is executed using C-BUS. This
126 * ensures the execution of the code happens through I-Cache.
127 * \n
128 *
129 * \section group_syslib_more_information More Information
130 * Refer to the technical reference manual (TRM).
131 *
132 * \section group_syslib_changelog Changelog
133 * <table class="doxtable">
134 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
135 * <tr>
136 * <td>3.60</td>
137 * <td>Updated API \ref Cy_SysLib_GetUniqueId, added section for unified linker script updation</td>
138 * <td>Code enhancement and bug fixes to enable API compilation for PSoC C3 (CAT1B).</td>
139 * </tr>
140 * <tr>
141 * <td>3.50</td>
142 * <td>Added support for TRAVEO™ II Body Entry devices.<br>
143 * Pre-processor check for MXS40SRSS version now groups ver. 2 with ver. 3. Previously ver. 2 was grouped with ver. 1.</td>
144 * Some pre-processor checks for if the device has a CM4 now also require device to not be HT_Variant to exclude TVIIBE and CAT1C devices.</td>
145 * <td>Code enhancement and support for new devices.</td>
146 * </tr>
147 * <tr>
148 * <td rowspan="2">3.40</td>
149 * <td>
150 * Newly added API \ref Cy_SysLib_GetDeviceLCS and enum \ref cy_en_syslib_lcs_mode_t
151 * </td>
152 * <td>Support of LCS added for CAT1D devices .</td>
153 * </tr>
154 * <tr>
155 * <td>Updated API \ref Cy_SysLib_SetWaitStates and added new macros.</td>
156 * <td>Enabled wait-states API for CAT1C devices.</td>
157 * </tr>
158 * <tr>
159 * <td>3.30</td>
160 * <td>Added \ref Cy_SysLib_IsDSRAMWarmBootEntry and \ref Cy_SysLib_ClearDSRAMWarmBootEntryStatus APIs.</td>
161 * <td>DEEPSLEEP-RAM support added for CAT1B Devices.</td>
162 * </tr>
163 * <tr>
164 * <td>3.20</td>
165 * <td>Updated Cy_SysLib_Delay() to perform correctly, enable Cy_SysLib_GetUniqueId() API for CAT1B,
166 * coverity fixes and documentation enhancements. \n
167 * Added CY_SECTION_INIT_CODECOPY_START and CY_SECTION_INIT_CODECOPY_END macro
168 * to move block of code from flash to sram during startup init. Currently
169 * it only supports in IAR build.</td>
170 * <td>Bug Fixes and Enhancements.</td>
171 * </tr>
172 * <tr>
173 * <td>3.10</td>
174 * <td>CAT1B, CAT1C, CAT1D devices support.<br>Added new API Cy_Syslib_SetWarmBootEntryPoint()
175 * to set the warm boot entry point address to a location read by BootROM.<br>
176 * To get the accurate delay, updated Cy_SysLib_Delay(), Cy_SysLib_DelayUs() with a calibration factor.</td>
177 * <td>Support for new devices.</td>
178 * </tr>
179 * <tr>
180 * <td>3.0</td>
181 * <td>Updated \ref Cy_SysLib_SoftResetCM4 to perform correctly when function is called multiple times.</td>
182 * <td>Fixed issue which caused IPC Message to Fail if API is called more than once.</td>
183 * </tr>
184 * <tr>
185 * <td rowspan="2">2.90</td>
186 * <td>Added new functions \ref Cy_SysLib_Rtos_Delay, \ref Cy_SysLib_Rtos_DelayUs.</td>
187 * <td>Provide user an option to overwrite delay function implementation based on target RTOS environment.</td>
188 * </tr>
189 * <tr>
190 * <td>Added new functions \ref Cy_SysLib_GetResetStatus, \ref Cy_SysLib_GetWcoTrim and \ref Cy_SysLib_SetWcoTrim.</td>
191 * <td>Add a possibility to manage the backup domain reset better and to store/restore the WCO trimming value.</td>
192 * </tr>
193 * <tr>
194 * <td rowspan="2">2.80</td>
195 * <td>Support for CM33.</td>
196 * <td>New devices support.</td>
197 * </tr>
198 * <tr>
199 * <td>Update \ref Cy_SysLib_GetResetReason API to read RES_CAUSE2 register as well.</td>
200 * <td>Code Enhancement/Bug Fix.</td>
201 * </tr>
202 * <tr>
203 * <td rowspan="4">2.70</td>
204 * <td>Added new macros CY_SECTION_RAMFUNC_BEGIN, CY_SECTION_RAMFUNC_END,
205 * CY_SECTION_SHAREDMEM to enable overriding of the linker section placement.</td>
206 * <td>Enhancement based on usability feedback.</td>
207 * </tr>
208 * <tr>
209 * <td>Noted that implementation of CY_ASSERT() was changed back in version 2.50,
210 * so that Cy_SysLib_AssertFailed() function is not called and user application
211 * may need to be updated.</td>
212 * <td>Documentation update.</td>
213 * </tr>
214 * <tr>
215 * <td>Removed the issue related to the malloc() failure to report error for the case when
216 * requested allocation size is bigger than the heap size.
217 * Refer to the \ref group_system_config_heap_stack_config_gcc section for the more details.
218 * Removed empty Known Issues section.
219 * <td>Documentation update and clarification.</td>
220 * </tr>
221 * <tr>
222 * <td>Fixed/Documented MISRA 2012 violations.</td>
223 * <td>MISRA 2012 compliance.</td>
224 * </tr>
225 * <tr>
226 * <td>2.60.1</td>
227 * <td>Updated the Configuration Considerations section with the information that
228 * CY_ASSERT() macro is defined in the cy_utils.h file, which is part of the
229 * <a href="https://github.com/Infineon/core-lib">Cypress Core Library (core-lib)</a>
230 * <td>Documentation update and clarification.</td>
231 * </tr>
232 * <tr>
233 * <td rowspan="2">2.60</td>
234 * <td>Updated the following functions for the PSoC 64 devices:
235 * \ref Cy_SysLib_ClearFlashCacheAndBuffer, \ref Cy_SysLib_ClearResetReason,
236 * \ref Cy_SysLib_SetWaitStates.
237 * <td>Added PSoC 64 device support.</td>
238 * </tr>
239 * <tr>
240 * <td>Minor documentation updates.</td>
241 * <td>Documentation enhancement.</td>
242 * </tr>
243 * <tr>
244 * <td>2.50.3</td>
245 * <td>Add section Known Issues
246 * <td>Documentation update and clarification.</td>
247 * </tr>
248 * <tr>
249 * <td>2.50.1</td>
250 * <td>Used the core library defines for the message codes forming.
251 * <td>Improve PDL code base.</td>
252 * </tr>
253 * <tr>
254 * <td>2.50</td>
255 * <td>Moved following macros to the core library:
256 * CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32,
257 * CY_SWAP_ENDIAN64,CY_GET_REG8,CY_SET_REG8,CY_GET_REG16,CY_SET_REG16,
258 * CY_GET_REG24,CY_SET_REG24,CY_GET_REG32,CY_SET_REG32,_CLR_SET_FLD32U,
259 * CY_REG32_CLR_SET,_CLR_SET_FLD16U,CY_REG16_CLR_SET,_CLR_SET_FLD8U,
260 * CY_REG8_CLR_SET,_BOOL2FLD,_FLD2BOOL,CY_SYSLIB_DIV_ROUND,
261 * CY_SYSLIB_DIV_ROUNDUP,CY_NOINIT,CY_SECTION,CY_UNUSED,CY_NOINLINE,
262 * CY_ALIGN,CY_RAMFUNC_BEGIN,CY_RAMFUNC_END.
263 * Use at least version 1.1 of the core library: https://github.com/Infineon/core-lib.
264 * <td>Improve PDL code base.</td>
265 * </tr>
266 * <tr>
267 * <td>2.40.1</td>
268 * <td>Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.</td>
269 * <td>Removed the IAR compiler warning.</td>
270 * </tr>
271 * <tr>
272 * <td>2.40</td>
273 * <td>Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.</td>
274 * <td>Improve PDL code base.</td>
275 * </tr>
276 * <tr>
277 * <td rowspan="3">2.30</td>
278 * <td>Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.</td>
279 * <td>Provided support for the ARM Compiler 6.</td>
280 * </tr>
281 * <tr>
282 * <td>Minor documentation edits.</td>
283 * <td>Documentation update and clarification.</td>
284 * </tr>
285 * <tr>
286 * <td>Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.</td>
287 * <td>Improve user experience.</td>
288 * </tr>
289 * <tr>
290 * <td rowspan="2">2.20</td>
291 * <td>Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.</td>
292 * <td>Provided support for the PDL static library in Release mode.</td>
293 * </tr>
294 * <tr>
295 * <td>Minor documentation edits.</td>
296 * <td>Documentation update and clarification.</td>
297 * </tr>
298 * <tr>
299 * <td rowspan="4">2.10</td>
300 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
301 * <td>Driver library directory-structure simplification.</td>
302 * </tr>
303 * <tr>
304 * <td>Added the following macros: CY_REG32_CLR_SET, _CLR_SET_FLD16U, CY_REG16_CLR_SET, _CLR_SET_FLD8U, CY_REG8_CLR_SET</td>
305 * <td>Register access simplification.</td>
306 * </tr>
307 * <tr>
308 * <td>Removed the Cy_SysLib_GetNumHfclkResetCause API function.</td>
309 * <td>This feature is not supported by SRSS_ver1.</td>
310 * </tr>
311 * <tr>
312 * <td>Added register access layer. Use register access macros instead
313 * of direct register access using dereferenced pointers.</td>
314 * <td>Makes register access device-independent, so that the PDL does
315 * not need to be recompiled for each supported part number.</td>
316 * </tr>
317 * <tr>
318 * <td>2.0.1</td>
319 * <td>Minor documentation edits</td>
320 * <td>Documentation update and clarification</td>
321 * </tr>
322 * <tr>
323 * <td rowspan="4"> 2.0</td>
324 * <td>
325 * Added Cy_SysLib_ResetBackupDomain() API implementation. \n
326 * Added CY_NOINLINE attribute implementation. \n
327 * Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n
328 * Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n
329 * Optimized Cy_SysLib_SetWaitStates() API implementation.
330 * </td>
331 * <td>Improvements made based on usability feedback.</td>
332 * </tr>
333 * <tr>
334 * <td>Added Assertion Classes and Levels.</td>
335 * <td>For error checking, parameter validation and status returns in the PDL API.</td>
336 * </tr>
337 * <tr>
338 * <td>Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.</td>
339 * <td>To store debug information into a non-zero init area for future analysis.</td>
340 * </tr>
341 * <tr>
342 * <td>Removed CY_WEAK attribute implementation.</td>
343 * <td>CMSIS __WEAK attribute should be used instead.</td>
344 * </tr>
345 * <tr>
346 * <td>1.0</td>
347 * <td>Initial version</td>
348 * <td></td>
349 * </tr>
350 * </table>
351 *
352 * \defgroup group_syslib_macros Macros
353 * \defgroup group_syslib_functions Functions
354 * \defgroup group_syslib_data_structures Data Structures
355 * \defgroup group_syslib_enumerated_types Enumerated Types
356 *
357 */
358
359 #if !defined (CY_SYSLIB_H)
360 #define CY_SYSLIB_H
361
362 #include "cy_device.h"
363
364 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS)
365
366 #include <stdint.h>
367 #include <stdbool.h>
368 #include "cy_utils.h"
369 #include "cy_result.h"
370
371 #if defined(__cplusplus)
372 extern "C" {
373 #endif /* defined(__cplusplus) */
374
375 #if defined( __ICCARM__ )
376 /* Suppress the warning for multiple volatile variables in an expression. */
377 /* This is common for driver's code and the usage is not order-dependent. */
378 #pragma diag_suppress=Pa082
379 #endif /* defined( __ICCARM__ ) */
380
381 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 3, \
382 'Coverity does not check the .S assembly files, the definition is a part of syslib assembly source file.')
383
384 /**
385 * \addtogroup group_syslib_macros
386 * \{
387 */
388
389 /******************************************************************************
390 * Macros
391 *****************************************************************************/
392
393 /** The macro for ARM CORTEX CM0P */
394 #define CY_CPU_CORTEX_M0P (__CORTEX_M == 0U) /**< CM0+ core CPU Code */
395 /** The macro for ARM CORTEX CM4 */
396 #define CY_CPU_CORTEX_M4 (__CORTEX_M == 4U) /**< CM4 core CPU Code */
397 /** The macro for ARM CORTEX CM7 */
398 #define CY_CPU_CORTEX_M7 (__CORTEX_M == 7U) /**< CM7 core CPU Code */
399 /** The macro for ARM CORTEX CM55 */
400 #define CY_CPU_CORTEX_M55 (__CORTEX_M == 55U) /**< CM55 core CPU Code */
401 /** The macro for ARM CORTEX CM33 */
402 #define CY_CPU_CORTEX_M33 (__CORTEX_M == 33U) /**< CM33 core CPU Code */
403
404 /** The macro to enable the Fault Handler */
405 #define CY_ARM_FAULT_DEBUG_ENABLED (1U)
406
407 #if !defined (CY_ARM_FAULT_DEBUG)
408 /** The macro defines if the Fault Handler is enabled. Enabled by default. */
409 #define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)
410 #endif /* CY_ARM_FAULT_DEBUG */
411
412 /** This macro is to be enabled and set appropriately for the CPU's which has
413 * branch prediction enabled, so the delay can work accurately.
414 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 1 for CM0P, CM33 and CM4.
415 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 2 for CM7_0 and CM7_1.
416 */
417 #ifndef CY_SYSLIB_DELAY_CALIBRATION_FACTOR
418 #define CY_SYSLIB_DELAY_CALIBRATION_FACTOR 1U
419 #endif
420
421 /**
422 * \defgroup group_syslib_macros_status_codes Status codes
423 * \{
424 * Function status type codes
425 */
426 /** \cond INTERNAL */
427
428 #define CY_PDL_STATUS_CODE_Pos (CY_RSLT_CODE_POSITION) /**< The module status code position in the status code */
429 #define CY_PDL_STATUS_TYPE_Pos (CY_RSLT_TYPE_POSITION) /**< The status type position in the status code */
430 #define CY_PDL_MODULE_ID_Pos (CY_RSLT_MODULE_POSITION) /**< The software module ID position in the status code */
431 #define CY_PDL_STATUS_INFO ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */
432 #define CY_PDL_STATUS_WARNING ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */
433 #define CY_PDL_STATUS_ERROR ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */
434 #define CY_PDL_MODULE_ID_Msk (CY_RSLT_MODULE_MASK) /**< The software module ID mask */
435
436 /** \endcond */
437
438 /** Get the software PDL module ID */
439 #define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos))
440 #define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */
441 /** \} group_syslib_macros_status_codes */
442
443 /** \} group_syslib_macros */
444
445 /**
446 * \addtogroup group_syslib_enumerated_types
447 * \{
448 */
449
450 /** The SysLib status code structure. */
451 typedef enum
452 {
453 CY_SYSLIB_SUCCESS = 0x00UL, /**< The success status code */
454 CY_SYSLIB_BAD_PARAM = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< The bad parameter status code */
455 CY_SYSLIB_TIMEOUT = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< The time out status code */
456 CY_SYSLIB_INVALID_STATE = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< The invalid state status code */
457 CY_SYSLIB_UNKNOWN = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown status code */
458 } cy_en_syslib_status_t;
459
460 /** The Life Cycle Stage(LCS) enum. */
461 typedef enum
462 {
463 CY_SYSLIB_LCS_VIRGIN = 0x000UL, /**< LCS Mode: VIRGIN */
464 CY_SYSLIB_LCS_SORT = 0x003UL, /**< LCS Mode: SORT */
465 CY_SYSLIB_LCS_PROVISIONED = 0x00FUL, /**< LCS Mode: PROVISIONED */
466 CY_SYSLIB_LCS_NORMAL_PROVISIONED = 0xC0FUL, /**< LCS Mode: NORMAL-PROVISIONED*/
467 CY_SYSLIB_LCS_NORMAL = 0xC03UL, /**< LCS Mode: NORMAL */
468 CY_SYSLIB_LCS_SECURE = 0xC3FUL, /**< LCS Mode: SECURE */
469 CY_SYSLIB_LCS_NORMAL_NO_SECURE = 0xCC3UL, /**< LCS Mode: NORMAL_NO_SECURE */
470 CY_SYSLIB_LCS_RMA = 0xF3FUL, /**< LCS Mode: RMA */
471 CY_SYSLIB_LCS_CORRUPTED = 0xFFFFUL, /**< LCS Mode: CORRUPTED */
472 } cy_en_syslib_lcs_mode_t;
473
474 /** \} group_syslib_enumerated_types */
475 /**
476 * \addtogroup group_syslib_data_structures
477 * \{
478 */
479
480 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
481 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
482 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55))
483 /** Configurable Fault Status Register - CFSR */
484 typedef struct
485 {
486 /** MemManage Fault Status Sub-register - MMFSR */
487 uint32_t iaccViol : 1; /**< MemManage Fault - The instruction access violation flag */
488 uint32_t daccViol : 1; /**< MemManage Fault - The data access violation flag */
489 uint32_t reserved1 : 1; /**< Reserved */
490 uint32_t mUnstkErr : 1; /**< MemManage Fault - Unstacking for a return from exception */
491 uint32_t mStkErr : 1; /**< MemManage Fault - MemManage fault on stacking for exception entry */
492 uint32_t mlspErr : 1; /**< MemManage Fault - MemManage fault occurred during floating-point lazy state preservation */
493 uint32_t reserved2 : 1; /**< Reserved */
494 uint32_t mmarValid : 1; /**< MemManage Fault - The MemManage Address register valid flag */
495 /** Bus Fault Status Sub-register - UFSR */
496 uint32_t iBusErr : 1; /**< Bus Fault - The instruction bus error */
497 uint32_t precisErr : 1; /**< Bus Fault - The precise Data bus error */
498 uint32_t imprecisErr : 1; /**< Bus Fault - The imprecise data bus error */
499 uint32_t unstkErr : 1; /**< Bus Fault - Unstacking for an exception return has caused one or more bus faults */
500 uint32_t stkErr : 1; /**< Bus Fault - Stacking for an exception entry has caused one or more bus faults */
501 uint32_t lspErr : 1; /**< Bus Fault - A bus fault occurred during the floating-point lazy state */
502 uint32_t reserved3 : 1; /**< Reserved */
503 uint32_t bfarValid : 1; /**< Bus Fault - The bus fault address register valid flag */
504 /** Usage Fault Status Sub-register - UFSR */
505 uint32_t undefInstr : 1; /**< Usage Fault - An undefined instruction */
506 uint32_t invState : 1; /**< Usage Fault - The invalid state */
507 uint32_t invPC : 1; /**< Usage Fault - An invalid PC */
508 uint32_t noCP : 1; /**< Usage Fault - No coprocessor */
509 uint32_t reserved4 : 4; /**< Reserved */
510 uint32_t unaligned : 1; /**< Usage Fault - Unaligned access */
511 uint32_t divByZero : 1; /**< Usage Fault - Divide by zero */
512 uint32_t reserved5 : 6; /**< Reserved */
513 } cy_stc_fault_cfsr_t;
514
515 /** Hard Fault Status Register - HFSR */
516 typedef struct
517 {
518 uint32_t reserved1 : 1; /**< Reserved. */
519 uint32_t vectTbl : 1; /**< HFSR - Indicates a bus fault on a vector table read during exception processing */
520 uint32_t reserved2 : 28; /**< Reserved. */
521 uint32_t forced : 1; /**< HFSR - Indicates a forced hard fault */
522 uint32_t debugEvt : 1; /**< HFSR - Reserved for the debug use. */
523 } cy_stc_fault_hfsr_t;
524
525 /** System Handler Control and State Register - SHCSR */
526 typedef struct
527 {
528 uint32_t memFaultAct : 1; /**< SHCSR - The MemManage exception active bit, reads as 1 if the exception is active */
529 uint32_t busFaultAct : 1; /**< SHCSR - The BusFault exception active bit, reads as 1 if the exception is active */
530 uint32_t reserved1 : 1; /**< Reserved. */
531 uint32_t usgFaultAct : 1; /**< SHCSR - The UsageFault exception active bit, reads as 1 if the exception is active */
532 uint32_t reserved2 : 3; /**< Reserved. */
533 uint32_t svCallAct : 1; /**< SHCSR - The SVCall active bit, reads as 1 if the SVC call is active */
534 uint32_t monitorAct : 1; /**< SHCSR - The debug monitor active bit, reads as 1 if the debug monitor is active */
535 uint32_t reserved3 : 1; /**< Reserved. */
536 uint32_t pendSVAct : 1; /**< SHCSR - The PendSV exception active bit, reads as 1 if the exception is active */
537 uint32_t sysTickAct : 1; /**< SHCSR - The SysTick exception active bit, reads as 1 if the exception is active */
538 uint32_t usgFaultPended : 1; /**< SHCSR - The UsageFault exception pending bit, reads as 1 if the exception is pending */
539 uint32_t memFaultPended : 1; /**< SHCSR - The MemManage exception pending bit, reads as 1 if the exception is pending */
540 uint32_t busFaultPended : 1; /**< SHCSR - The BusFault exception pending bit, reads as 1 if the exception is pending */
541 uint32_t svCallPended : 1; /**< SHCSR - The SVCall pending bit, reads as 1 if the exception is pending */
542 uint32_t memFaultEna : 1; /**< SHCSR - The MemManage enable bit, set to 1 to enable */
543 uint32_t busFaultEna : 1; /**< SHCSR - The BusFault enable bit, set to 1 to enable */
544 uint32_t usgFaultEna : 1; /**< SHCSR - The UsageFault enable bit, set to 1 to enable */
545 uint32_t reserved4 : 13; /**< Reserved */
546 } cy_stc_fault_shcsr_t;
547 #endif /* CY_CPU_CORTEX_M4, CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M33, CY_CPU_CORTEX_M55*/
548
549 /** The fault configuration structure. */
550 typedef struct
551 {
552 uint32_t r0; /**< R0 register content */
553 uint32_t r1; /**< R1 register content */
554 uint32_t r2; /**< R2 register content */
555 uint32_t r3; /**< R3 register content */
556 uint32_t r12; /**< R12 register content */
557 uint32_t lr; /**< LR register content */
558 uint32_t pc; /**< PC register content */
559 uint32_t psr; /**< PSR register content */
560 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
561 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55))
562 union
563 {
564 uint32_t cfsrReg; /**< CFSR register content as a word */
565 cy_stc_fault_cfsr_t cfsrBits; /**< CFSR register content as a structure */
566 } cfsr;
567 union
568 {
569 uint32_t hfsrReg; /**< HFSR register content as a word */
570 cy_stc_fault_hfsr_t hfsrBits; /**< HFSR register content as a structure */
571 } hfsr;
572 union
573 {
574 uint32_t shcsrReg; /**< SHCSR register content as a word */
575 cy_stc_fault_shcsr_t shcsrBits; /**< SHCSR register content as a structure */
576 } shcsr;
577 uint32_t mmfar; /**< MMFAR register content */
578 uint32_t bfar; /**< BFAR register content */
579 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
580 (defined (__FPU_USED ) && (__FPU_USED == 1U)))
581 uint32_t s0; /**< FPU S0 register content */
582 uint32_t s1; /**< FPU S1 register content */
583 uint32_t s2; /**< FPU S2 register content */
584 uint32_t s3; /**< FPU S3 register content */
585 uint32_t s4; /**< FPU S4 register content */
586 uint32_t s5; /**< FPU S5 register content */
587 uint32_t s6; /**< FPU S6 register content */
588 uint32_t s7; /**< FPU S7 register content */
589 uint32_t s8; /**< FPU S8 register content */
590 uint32_t s9; /**< FPU S9 register content */
591 uint32_t s10; /**< FPU S10 register content */
592 uint32_t s11; /**< FPU S11 register content */
593 uint32_t s12; /**< FPU S12 register content */
594 uint32_t s13; /**< FPU S13 register content */
595 uint32_t s14; /**< FPU S14 register content */
596 uint32_t s15; /**< FPU S15 register content */
597 uint32_t fpscr; /**< FPU FPSCR register content */
598 #endif /* __FPU_PRESENT */
599 #endif /* CY_CPU_CORTEX_M4, CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M33, CY_CPU_CORTEX_M55*/
600 } cy_stc_fault_frame_t;
601 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
602
603 /** \} group_syslib_data_structures */
604
605 /**
606 * \addtogroup group_syslib_macros
607 * \{
608 */
609
610 /** The driver major version */
611 #define CY_SYSLIB_DRV_VERSION_MAJOR 3
612
613 /** The driver minor version */
614 #define CY_SYSLIB_DRV_VERSION_MINOR 60
615
616 /** Define start of the function placed to the SRAM area by the linker */
617 #ifndef CY_SECTION_RAMFUNC_BEGIN
618 #if defined (__ICCARM__)
619 #define CY_SECTION_RAMFUNC_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
620 #else
621 #define CY_SECTION_RAMFUNC_BEGIN CY_SECTION(".cy_ramfunc")
622 #endif
623 #endif
624
625 /** Define end of the function placed to the SRAM area by the linker */
626 #ifndef CY_SECTION_RAMFUNC_END
627 #if defined (__ICCARM__)
628 #define CY_SECTION_RAMFUNC_END CY_PRAGMA(diag_default = Ta023)
629 #else
630 #define CY_SECTION_RAMFUNC_END
631 #endif
632 #endif
633
634 /** Define start of the function placed to the SRAM1 area by the linker */
635 #ifndef CY_SECTION_SRAM1_CODE_BEGIN
636 #if defined (__ICCARM__)
637 #define CY_SECTION_SRAM1_CODE_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
638 #else
639 #define CY_SECTION_SRAM1_CODE_BEGIN CY_SECTION(".cy_sram1_code")
640 #endif
641 #endif
642
643 /** Define end of the function placed to the SRAM1 area by the linker */
644 #ifndef CY_SECTION_SRAM1_CODE_END
645 #if defined (__ICCARM__)
646 #define CY_SECTION_SRAM1_CODE_END CY_PRAGMA(diag_default = Ta023)
647 #else
648 #define CY_SECTION_SRAM1_CODE_END
649 #endif
650 #endif
651
652 /** Define start of the function placed to the SRAM1 area by the linker */
653 #ifndef CY_SECTION_SRAM1_DATANS_BEGIN
654 #if defined (__ICCARM__)
655 #define CY_SECTION_SRAM1_DATANS_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
656 #else
657 #define CY_SECTION_SRAM1_DATANS_BEGIN CY_SECTION(".cy_sram1_data_ns")
658 #endif
659 #endif
660
661 /** Define end of the function placed to the SRAM1 area by the linker */
662 #ifndef CY_SECTION_SRAM1_DATANS_END
663 #if defined (__ICCARM__)
664 #define CY_SECTION_SRAM1_DATANS_END CY_PRAGMA(diag_default = Ta023)
665 #else
666 #define CY_SECTION_SRAM1_DATANS_END
667 #endif
668 #endif
669
670 /** Define start of the function placed to the SRAM1 area by the linker */
671 #ifndef CY_SECTION_SRAM0_DATANS_BEGIN
672 #if defined (__ICCARM__)
673 #define CY_SECTION_SRAM0_DATANS_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
674 #else
675 #define CY_SECTION_SRAM0_DATANS_BEGIN CY_SECTION(".cy_sram0_data_ns")
676 #endif
677 #endif
678
679 /** Define end of the function placed to the SRAM1 area by the linker */
680 #ifndef CY_SECTION_SRAM0_DATANS_END
681 #if defined (__ICCARM__)
682 #define CY_SECTION_SRAM0_DATANS_END CY_PRAGMA(diag_default = Ta023)
683 #else
684 #define CY_SECTION_SRAM0_DATANS_END
685 #endif
686 #endif
687
688
689 #if (CY_CPU_CORTEX_M7 || CY_CPU_CORTEX_M55)
690 /** Define start of the function placed to the ITCM area by the linker */
691 #ifndef CY_SECTION_ITCM_BEGIN
692 #define CY_SECTION_ITCM_BEGIN CY_SECTION(".cy_itcm")
693 #endif
694
695 /** Define end of the function placed to the ITCM area by the linker */
696 #ifndef CY_SECTION_ITCM_END
697 #define CY_SECTION_ITCM_END
698 #endif
699
700 /** Define start of the function placed to the DTCM area by the linker */
701 #ifndef CY_SECTION_DTCM_BEGIN
702 #define CY_SECTION_DTCM_BEGIN CY_SECTION(".cy_dtcm")
703 #endif
704
705 /** Define end of the function placed to the DTCM area by the linker */
706 #ifndef CY_SECTION_DTCM_END
707 #define CY_SECTION_DTCM_END
708 #endif
709 #endif /* CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M55 */
710
711 /** Define start of the code block to be copied to SRAM by the linker during init */
712 #ifndef CY_SECTION_INIT_CODECOPY_BEGIN
713 #if defined (__ICCARM__)
714 #define CY_SECTION_INIT_CODECOPY_BEGIN CY_PRAGMA(default_function_attributes = @ "code_in_RAM")
715 #else
716 #define CY_SECTION_INIT_CODECOPY_BEGIN
717 #endif
718 #endif
719
720 /** Define end of the code block to be copied to SRAM by the linker during init */
721 #ifndef CY_SECTION_INIT_CODECOPY_END
722 #if defined (__ICCARM__)
723 #define CY_SECTION_INIT_CODECOPY_END CY_PRAGMA(default_function_attributes =)
724 #else
725 #define CY_SECTION_INIT_CODECOPY_END
726 #endif
727 #endif
728
729 /** Define variable to be placed to the shared SRAM area by the linker. This memory region is un-cached for CM55 core */
730 #ifndef CY_SECTION_SHAREDMEM
731 #define CY_SECTION_SHAREDMEM CY_SECTION(".cy_sharedmem")
732 #endif
733
734 /** Define variable to be placed to the secured shared SRAM area by the linker */
735 #ifndef CY_SECTION_SHAREDMEM_SEC
736 #define CY_SECTION_SHAREDMEM_SEC CY_SECTION(".cy_sharedmem_sec")
737 #endif
738
739 /** Define start of code to be placed to the SOCMEMSRAM area by the linker */
740 #ifndef CY_SECTION_SOCMEMSRAMCODE_BEGIN
741 #define CY_SECTION_SOCMEMSRAMCODE_BEGIN CY_SECTION(".cy_socmem_code")
742 #endif
743
744 /** Define end of code placed to the SOCMEMSRAM area by the linker */
745 #ifndef CY_SECTION_SOCMEMSRAMCODE_END
746 #if defined (__GNUC__)
747 #define CY_SECTION_SOCMEMSRAMCODE_END
748 #endif
749 #endif
750
751 /** Define start of data to be placed to the SOCMEMSRAM area by the linker */
752 #ifndef CY_SECTION_SOCMEMSRAMDATA_BEGIN
753 #define CY_SECTION_SOCMEMSRAMDATA_BEGIN CY_SECTION(".cy_socmem_data")
754 #endif
755
756 /** Define end of code placed to the SOCMEMSRAM area by the linker */
757 #ifndef CY_SECTION_SOCMEMSRAMDATA_END
758 #if defined (__GNUC__)
759 #define CY_SECTION_SOCMEMSRAMDATA_END
760 #endif
761 #endif
762
763 /** Define start of shared data to be placed to the SOCMEMSRAM area by the linker. This memory region is un-cached for CM55 core */
764 #ifndef CY_SECTION_SOCMEMSRAMSHARED_BEGIN
765 #define CY_SECTION_SOCMEMSRAMSHARED_BEGIN CY_SECTION(".cy_shared_socmem")
766 #endif
767
768 /** Define end of shared data to be placed to the SOCMEMSRAM area by the linker */
769 #ifndef CY_SECTION_SOCMEMSRAMSHARED_END
770 #if defined (__GNUC__)
771 #define CY_SECTION_SOCMEMSRAMSHARED_END
772 #endif
773 #endif
774
775 /** Define start of function placed to the bootstrap area by the linker */
776 #ifndef CY_SECTION_BOOTSTRAP_FUNC_BEGIN
777 #if defined (__GNUC__)
778 #define CY_SECTION_BOOTSTRAP_FUNC_BEGIN CY_SECTION(".cy_l1func")
779 #endif
780 #endif
781
782 /** Define end of function placed to the bootstrap area by the linker */
783 #ifndef CY_SECTION_BOOTSTRAP_FUNC_END
784 #if defined (__GNUC__)
785 #define CY_SECTION_BOOTSTRAP_FUNC_END
786 #endif
787 #endif
788
789 /** Placed initialized global variable to the bootstrap data area by the linker */
790 #ifndef CY_SECTION_BOOTSTRAP_DATA
791 #if defined (__GNUC__)
792 #define CY_SECTION_BOOTSTRAP_DATA CY_SECTION(".cy_l1data")
793 #endif
794 #endif
795
796 /** Placed un-init global variable to the bootstrap bss area by the linker */
797 #ifndef CY_SECTION_BOOTSTRAP_BSS
798 #if defined (__GNUC__)
799 #define CY_SECTION_BOOTSTRAP_BSS CY_SECTION(".cy_l1bss")
800 #endif
801 #endif
802
803 /** Define start of the data placed in the SRAM0 area by the linker */
804 #ifndef CY_SECTION_SRAM0DATA_BEGIN
805 #define CY_SECTION_SRAM0DATA_BEGIN CY_SECTION(".cy_sram0_data")
806 #endif
807
808 /** Define end of the function placed to the ITCM area by the linker */
809 #ifndef CY_SECTION_SRAM0DATA_END
810 #define CY_SECTION_SRAM0DATA_END
811 #endif
812
813 typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */
814 #if defined (__ICCARM__)
815 typedef union { cy_israddress __fun; void * __ptr; } cy_intvec_elem;
816 #endif /* defined (__ICCARM__) */
817
818 /* MISRA rule 6.3 recommends using specific-length typedef for the basic
819 * numerical types of signed and unsigned variants of char, float, and double.
820 */
821 typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */
822 typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */
823 typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */
824
825 #if !defined(NDEBUG)
826 /** The max size of the file name which stores the ASSERT location */
827 #define CY_MAX_FILE_NAME_SIZE (24U)
828 extern CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE + 1]; /**< The assert buffer */
829 extern CY_NOINIT uint32_t cy_assertLine; /**< The assert line value */
830 #endif /* NDEBUG */
831
832 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
833 #define CY_R0_Pos (0U) /**< The position of the R0 content in a fault structure */
834 #define CY_R1_Pos (1U) /**< The position of the R1 content in a fault structure */
835 #define CY_R2_Pos (2U) /**< The position of the R2 content in a fault structure */
836 #define CY_R3_Pos (3U) /**< The position of the R3 content in a fault structure */
837 #define CY_R12_Pos (4U) /**< The position of the R12 content in a fault structure */
838 #define CY_LR_Pos (5U) /**< The position of the LR content in a fault structure */
839 #define CY_PC_Pos (6U) /**< The position of the PC content in a fault structure */
840 #define CY_PSR_Pos (7U) /**< The position of the PSR content in a fault structure */
841 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
842 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)) && \
843 ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined (__FPU_USED ) && (__FPU_USED == 1U)))
844 #define CY_FPSCR_IXC_Msk (0x00000010U) /**< The cumulative exception bit for floating-point exceptions */
845 #define CY_FPSCR_IDC_Msk (0x00000080U) /**< The cumulative exception bit for floating-point exceptions */
846 #define CY_S0_Pos (8U) /**< The position of the FPU S0 content in a fault structure */
847 #define CY_S1_Pos (9U) /**< The position of the FPU S1 content in a fault structure */
848 #define CY_S2_Pos (10U) /**< The position of the FPU S2 content in a fault structure */
849 #define CY_S3_Pos (11U) /**< The position of the FPU S3 content in a fault structure */
850 #define CY_S4_Pos (12U) /**< The position of the FPU S4 content in a fault structure */
851 #define CY_S5_Pos (13U) /**< The position of the FPU S5 content in a fault structure */
852 #define CY_S6_Pos (14U) /**< The position of the FPU S6 content in a fault structure */
853 #define CY_S7_Pos (15U) /**< The position of the FPU S7 content in a fault structure */
854 #define CY_S8_Pos (16U) /**< The position of the FPU S8 content in a fault structure */
855 #define CY_S9_Pos (17U) /**< The position of the FPU S9 content in a fault structure */
856 #define CY_S10_Pos (18U) /**< The position of the FPU S10 content in a fault structure */
857 #define CY_S11_Pos (19U) /**< The position of the FPU S11 content in a fault structure */
858 #define CY_S12_Pos (20U) /**< The position of the FPU S12 content in a fault structure */
859 #define CY_S13_Pos (21U) /**< The position of the FPU S13 content in a fault structure */
860 #define CY_S14_Pos (22U) /**< The position of the FPU S14 content in a fault structure */
861 #define CY_S15_Pos (23U) /**< The position of the FPU S15 content in a fault structure */
862 #define CY_FPSCR_Pos (24U) /**< The position of the FPU FPSCR content in a fault structure */
863 #endif /* (CY_CPU_CORTEX_M4 || CY_CPU_CORTEX_M7 || CY_CPU_CORTEX_M33 || CY_CPU_CORTEX_M55) && __FPU_PRESENT */
864
865 extern CY_NOINIT cy_stc_fault_frame_t cy_faultFrame; /**< Fault frame structure */
866 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
867
868 /**
869 * \defgroup group_syslib_macros_assert Assert Classes and Levels
870 * \{
871 * Defines for the Assert Classes and Levels
872 */
873
874 /**
875 * Class 1 - The highest class, safety-critical functions which rely on parameters that could be
876 * changed between different PSoC devices
877 */
878 #define CY_ASSERT_CLASS_1 (1U)
879
880 /** Class 2 - Functions that have fixed limits such as counter periods (16-bits/32-bits etc.) */
881 #define CY_ASSERT_CLASS_2 (2U)
882
883 /** Class 3 - Functions that accept enums as constant parameters */
884 #define CY_ASSERT_CLASS_3 (3U)
885
886 #ifndef CY_ASSERT_LEVEL
887 /** The user-definable assert level from compiler command-line argument (similarly to DEBUG / NDEBUG) */
888 #define CY_ASSERT_LEVEL CY_ASSERT_CLASS_3
889 #endif /* CY_ASSERT_LEVEL */
890
891 #if (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1)
892 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
893 #define CY_ASSERT_L2(x) do{}while(false) /**< Assert Level 2 */
894 #define CY_ASSERT_L3(x) do{}while(false) /**< Assert Level 3 */
895 #elif (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_2)
896 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
897 #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
898 #define CY_ASSERT_L3(x) do{}while(false) /**< Assert Level 3 */
899 #else /* Default is Level 3 */
900 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
901 #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
902 #define CY_ASSERT_L3(x) CY_ASSERT(x) /**< Assert Level 3 */
903 #endif /* CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1 */
904
905 /** \} group_syslib_macros_assert */
906
907 #ifdef CY_IP_M33SYSCPUSS
908 /*******************************************************************************
909 * Macro Name: CY_UNUSED_PARAM
910 ****************************************************************************//**
911 *
912 * Suppresses the unused parameter warning
913 *
914 * \note
915 * This macro is available for devices having M33SYSCPUSS IP.
916 *
917 *******************************************************************************/
918 #define CY_UNUSED_PARAM(a) (void)(a)
919
920 /*******************************************************************************
921 * Macro Name: CY_ARRAY_SIZE(x)
922 ****************************************************************************//**
923 *
924 * Returns the size of Array
925 *
926 * \param x Array Name
927 *
928 * \note
929 * This macro is available for devices having M33SYSCPUSS IP.
930 *
931 *******************************************************************************/
932 #define CY_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
933 #endif /* CY_IP_M33SYSCPUSS */
934
935
936 /******************************************************************************
937 * Constants
938 *****************************************************************************/
939
940 /**
941 * \defgroup group_syslib_macros_reset_cause Reset cause
942 * \{
943 * Define RESET_CAUSE mask values
944 */
945 /** A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. */
946 #define CY_SYSLIB_RESET_HWWDT (0x0001U)
947 /** The fault logging system requested a reset from its Active logic. */
948 #define CY_SYSLIB_RESET_ACT_FAULT (0x0002U)
949 /** The fault logging system requested a reset from its Deep-Sleep logic. */
950 #define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U)
951
952 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M7CPUSS)
953 /** The fault logging system requested a reset from its Test Controller or debugger asserted test. */
954 /**
955 * \note
956 * This macro is available for devices having M33SYSCPUSS IP.
957 **/
958 #define CY_SYSLIB_RESET_TC_DBGRESET (0x0008U)
959 #endif
960
961 /** The CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. */
962 #define CY_SYSLIB_RESET_SOFT (0x0010U)
963 /** The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. */
964 #define CY_SYSLIB_RESET_SWWDT0 (0x0020U)
965 /** The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. */
966 #define CY_SYSLIB_RESET_SWWDT1 (0x0040U)
967 /** The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. */
968 #define CY_SYSLIB_RESET_SWWDT2 (0x0080U)
969 /** The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. */
970 #define CY_SYSLIB_RESET_SWWDT3 (0x0100U)
971 /** The reset has occurred on a loss of high-frequency clock. */
972 #define CY_SYSLIB_RESET_CSV_LOSS_WAKEUP (0x10000U)
973 /** The reset has occurred due to frequency error of high-frequency clock. */
974 #define CY_SYSLIB_RESET_CSV_ERROR_WAKEUP (0x20000U)
975 /** The reset has occurred on a wakeup from Hibernate power mode. */
976 #define CY_SYSLIB_RESET_HIB_WAKEUP (0x80000000U)
977
978
979 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
980 /**
981 * \note
982 * Below macros are available for devices having CY_IP_MXS40SRSS_VERSION greater than or equal to 2.
983 **/
984 /** External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
985 #define CY_SYSLIB_RESET_XRES (0x10000U)
986 /** External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. */
987 #define CY_SYSLIB_RESET_BODVDDD (0x20000U)
988 /** External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
989 #define CY_SYSLIB_RESET_BODVDDA (0x40000U)
990 /** Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions. */
991 #define CY_SYSLIB_RESET_BODVCCD (0x80000U)
992 /** Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
993 #define CY_SYSLIB_RESET_OVDVDDD (0x100000U)
994 /** Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
995 #define CY_SYSLIB_RESET_OVDVDDA (0x200000U)
996 /** Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
997 #define CY_SYSLIB_RESET_OVDVCCD (0x400000U)
998 /** Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
999 #define CY_SYSLIB_RESET_OCD_ACT_LINREG (0x800000U)
1000 /** Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
1001 #define CY_SYSLIB_RESET_OCD_DPSLP_LINREG (0x1000000U)
1002 /** Overcurrent detection from REGHC (if present). If REGHC is not present, hardware will never set this bit.This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
1003 #define CY_SYSLIB_RESET_OCD_REGHC (0x2000000U)
1004 /** PMIC status triggered a reset. If PMIC control is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
1005 #define CY_SYSLIB_RESET_PMIC (0x4000000U)
1006 /** PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. */
1007 #define CY_SYSLIB_RESET_PXRES (0x10000000U)
1008 /** Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. */
1009 #define CY_SYSLIB_RESET_STRUCT_XRES (0x20000000U)
1010 /** Indicator that a POR occurred. This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. */
1011 #define CY_SYSLIB_RESET_PORVDDD (0x40000000U)
1012
1013 #endif
1014
1015
1016 /** \} group_syslib_macros_reset_cause */
1017
1018 #ifdef CY_IP_M4CPUSS
1019 /** Bit[31:24] Opcode = 0x1B (SoftReset)
1020 * Bit[7:1] Type = 1 (Only CM4 reset)
1021 */
1022 /**
1023 * \note
1024 * This macro is available for devices having M4CPUSS IP.
1025 **/
1026 #define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)
1027 #endif
1028
1029 #if defined(CY_IP_M4CPUSS) || defined (CY_IP_M33SYSCPUSS)
1030
1031 /**
1032 * \defgroup group_syslib_macros_unique_id Unique ID
1033 * \{
1034 * Unique ID fields positions
1035 */
1036 /**
1037 * \note
1038 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1039 **/
1040 #define CY_UNIQUE_ID_DIE_YEAR_Pos (57U) /**< The position of the DIE_YEAR field in the silicon Unique ID */
1041 /**
1042 * \note
1043 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1044 **/
1045 #define CY_UNIQUE_ID_DIE_MINOR_Pos (56U) /**< The position of the DIE_MINOR field in the silicon Unique ID */
1046 /**
1047 * \note
1048 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1049 **/
1050 #define CY_UNIQUE_ID_DIE_SORT_Pos (48U) /**< The position of the DIE_SORT field in the silicon Unique ID */
1051 /**
1052 * \note
1053 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1054 **/
1055 #define CY_UNIQUE_ID_DIE_Y_Pos (40U) /**< The position of the DIE_Y field in the silicon Unique ID */
1056 /**
1057 * \note
1058 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1059 **/
1060 #define CY_UNIQUE_ID_DIE_X_Pos (32U) /**< The position of the DIE_X field in the silicon Unique ID */
1061 /**
1062 * \note
1063 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1064 **/
1065 #define CY_UNIQUE_ID_DIE_WAFER_Pos (24U) /**< The position of the DIE_WAFER field in the silicon Unique ID */
1066 /**
1067 * \note
1068 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1069 **/
1070 #define CY_UNIQUE_ID_DIE_LOT_2_Pos (16U) /**< The position of the DIE_LOT_2 field in the silicon Unique ID */
1071 /**
1072 * \note
1073 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1074 **/
1075 #define CY_UNIQUE_ID_DIE_LOT_1_Pos (8U) /**< The position of the DIE_LOT_1 field in the silicon Unique ID */
1076 /**
1077 * \note
1078 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1079 **/
1080 #define CY_UNIQUE_ID_DIE_LOT_0_Pos (0U) /**< The position of the DIE_LOT_0 field in the silicon Unique ID */
1081
1082 /** \} group_syslib_macros_unique_id */
1083 #endif
1084
1085 /** \} group_syslib_macros */
1086
1087 /******************************************************************************
1088 * Function prototypes
1089 ******************************************************************************/
1090
1091 /**
1092 * \addtogroup group_syslib_functions
1093 * \{
1094 */
1095
1096 /*******************************************************************************
1097 * Function Name: Cy_SysLib_Delay
1098 ****************************************************************************//**
1099 *
1100 * The function delays by the specified number of milliseconds.
1101 * By default, the number of cycles to delay is calculated based on the
1102 * \ref SystemCoreClock.
1103 *
1104 * \param milliseconds The number of milliseconds to delay.
1105 *
1106 * \note The function calls \ref Cy_SysLib_DelayCycles() API to generate a delay.
1107 * If the function parameter (milliseconds) is bigger than
1108 * CY_DELAY_MS_OVERFLOW constant, then an additional loop runs to prevent
1109 * an overflow in parameter passed to \ref Cy_SysLib_DelayCycles() API.
1110 *
1111 * \note The Calibration factor is to correct the delay in cases where
1112 * CPU's use branch prediction, currently applicable for only CAT1C
1113 * devices.
1114 *
1115 *******************************************************************************/
1116 void Cy_SysLib_Delay(uint32_t milliseconds);
1117
1118
1119 /*******************************************************************************
1120 * Function Name: Cy_SysLib_DelayUs
1121 ****************************************************************************//**
1122 *
1123 * The function delays by the specified number of microseconds.
1124 * By default, the number of cycles to delay is calculated based on the
1125 * \ref SystemCoreClock.
1126 *
1127 * \param microseconds The number of microseconds to delay.
1128 *
1129 * \note If the CPU frequency is a small non-integer number, the actual delay
1130 * can be up to twice as long as the nominal value. The actual delay
1131 * cannot be shorter than the nominal one.
1132 *
1133 * \note The Calibration factor is to correct the delay in cases where
1134 * CPU's use branch prediction, currently applicable for only CAT1C
1135 * devices.
1136 *
1137 *******************************************************************************/
1138 void Cy_SysLib_DelayUs(uint16_t microseconds);
1139
1140 /*******************************************************************************
1141 * Function Name: Cy_SysLib_Rtos_Delay
1142 ****************************************************************************//**
1143 *
1144 * The function is same as \ref Cy_SysLib_Delay. However, this API is declared WEAK
1145 * providing option for user to overwrite the implementation based on target RTOS.
1146 *
1147 * \param milliseconds The number of milliseconds to delay.
1148 *
1149 *******************************************************************************/
1150 void Cy_SysLib_Rtos_Delay(uint32_t milliseconds);
1151
1152
1153 /*******************************************************************************
1154 * Function Name: Cy_SysLib_Rtos_DelayUs
1155 ****************************************************************************//**
1156 *
1157 * The function is same as \ref Cy_SysLib_DelayUs. However, this API is declared WEAK
1158 * providing option for user to overwrite the implementation based on target RTOS.
1159 *
1160 * \param microseconds The number of microseconds to delay.
1161 *
1162 *******************************************************************************/
1163 void Cy_SysLib_Rtos_DelayUs(uint16_t microseconds);
1164
1165
1166 /*******************************************************************************
1167 * Function Name: Cy_SysLib_DelayCycles
1168 ****************************************************************************//**
1169 * Delays for the specified number of cycles.
1170 * The function is implemented in the assembler for each supported compiler.
1171 *
1172 * \param cycles The number of cycles to delay.
1173 *
1174 * \note While using for CAT1C devices, where the CPU supports branch prediction,
1175 * this API needs to be called as below
1176 * Cy_SysLib_DelayCycles(cycles * CY_SYSLIB_DELAY_CALIBRATION_FACTOR);
1177 * For Example:-
1178 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 1 for CM0P, CM33 and CM4.
1179 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 2 for CM7_0 and CM7_1.
1180 *
1181 *******************************************************************************/
1182 void Cy_SysLib_DelayCycles(uint32_t cycles);
1183
1184
1185 /*******************************************************************************
1186 * Function Name: Cy_SysLib_Halt
1187 ****************************************************************************//**
1188 *
1189 * This function halts the CPU but only the CPU which calls the function.
1190 * It doesn't affect other CPUs.
1191 *
1192 * \param reason The value to be used during debugging.
1193 *
1194 * \note The function executes the BKPT instruction for halting CPU and is
1195 * intended to be used for the debug purpose. A regular use case requires
1196 * Debugger attachment before the function call.
1197 * The BKPT instruction causes the CPU to enter the Debug state. Debug
1198 * tools can use this to investigate the system state, when the
1199 * instruction at a particular address is reached.
1200 *
1201 * \note Execution of a BKPT instruction without a debugger attached produces
1202 * a fault. The fault results in the HardFault exception being taken
1203 * or causes a Lockup state if it occurs in the NMI or HardFault handler.
1204 * The default HardFault handler make a software reset if the build option
1205 * is the release mode (NDEBUG). If the build option is the debug mode,
1206 * the system will stay in the infinite loop of the
1207 * \ref Cy_SysLib_ProcessingFault() function.
1208 *
1209 *******************************************************************************/
1210 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M55APPCPUSS) || defined (CY_DOXYGEN)
1211 void Cy_SysLib_Halt(uint32_t reason);
1212 #else
1213 /** \cond INTERNAL */
1214 __NO_RETURN void Cy_SysLib_Halt(uint32_t reason);
1215 /** \endcond */
1216 #endif
1217
1218
1219 /*******************************************************************************
1220 * Macro Name: Cy_SysLib_AssertFailed
1221 ****************************************************************************//**
1222 *
1223 * This function stores the ASSERT location of the file name (including path
1224 * to file) and line number in a non-zero init area for debugging. Also it calls
1225 * the \ref Cy_SysLib_Halt() function to halt the processor.
1226 *
1227 * \param file The file name of the ASSERT location.
1228 * \param line The line number of the ASSERT location.
1229 *
1230 * \note A stored file name and line number could be accessed by
1231 * cy_assertFileName and cy_assertLine global variables.
1232 * \note This function has the WEAK option, so the user can redefine
1233 * the function for a custom processing.
1234 *
1235 *******************************************************************************/
1236 void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line);
1237
1238 #ifdef CY_IP_M4CPUSS
1239
1240
1241 /*******************************************************************************
1242 * Function Name: Cy_SysLib_ClearFlashCacheAndBuffer
1243 ****************************************************************************//**
1244 *
1245 * This function invalidates the flash cache and buffer. It ensures the valid
1246 * data is read from flash instead of using outdated data from the cache.
1247 * The caches' LRU structure is also reset to their default state.
1248 *
1249 * \note The operation takes a maximum of three clock cycles on the slowest of
1250 * the clk_slow and clk_fast clocks.
1251 *
1252 * \note
1253 * This API is available for devices having M4CPUSS IP.
1254 *
1255 *******************************************************************************/
1256 void Cy_SysLib_ClearFlashCacheAndBuffer(void);
1257
1258 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
1259 /*******************************************************************************
1260 * Function Name: Cy_SysLib_SoftResetCM4
1261 ****************************************************************************//**
1262 *
1263 * This function performs a CM4 Core software reset using the CM4_PWR_CTL
1264 * register. The register is accessed by CM0 Core by using a command transferred
1265 * to SROM API through the IPC channel. When the command is sent, the API waits
1266 * for the IPC channel release.
1267 *
1268 * \note This function should be called only when the CM4 core is in Deep
1269 * Sleep mode.
1270 * \note This function will not reset CM0+ Core.
1271 * \note This function waits for an IPC channel release state.
1272 *
1273 * \note
1274 * This API is available for devices having M4CPUSS IP.
1275 *
1276 *******************************************************************************/
1277 void Cy_SysLib_SoftResetCM4(void);
1278 #endif /* CY_CPU_CORTEX_M0P */
1279 #endif
1280
1281 #if (defined(CY_IP_M4CPUSS) && !(defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u))) || \
1282 (defined (CY_IP_M33SYSCPUSS) && defined(CY_IP_MXEFUSE)) || defined (CY_DOXYGEN)
1283
1284 /*******************************************************************************
1285 * Function Name: Cy_SysLib_GetUniqueId
1286 ****************************************************************************//**
1287 *
1288 * This function returns the silicon unique ID.
1289 * The ID includes Die lot[3]#, Die Wafer#, Die X, Die Y, Die Sort#, Die Minor
1290 * and Die Year.
1291 *
1292 * \return A combined 64-bit unique ID.
1293 * [63:57] - DIE_YEAR
1294 * [56:56] - DIE_MINOR
1295 * [55:48] - DIE_SORT
1296 * [47:40] - DIE_Y
1297 * [39:32] - DIE_X
1298 * [31:24] - DIE_WAFER
1299 * [23:16] - DIE_LOT[2]
1300 * [15: 8] - DIE_LOT[1]
1301 * [ 7: 0] - DIE_LOT[0]
1302 *
1303 * \note
1304 * This API is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1305 *
1306 * \note
1307 * For CY_IP_M33SYSCPUSS IP, EFUSE must be in enabled state before
1308 * calling this API.
1309 *
1310 *******************************************************************************/
1311 uint64_t Cy_SysLib_GetUniqueId(void);
1312 #endif
1313
1314 /*******************************************************************************
1315 * Function Name: Cy_SysLib_ResetBackupDomain
1316 ****************************************************************************//**
1317 *
1318 * This function resets the backup domain power to avoid the ILO glitch. The
1319 * glitch can occur when the device is reset due to POR/BOD/XRES while
1320 * the backup voltage is supplied into the system.
1321 *
1322 * \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
1323 * when the reset is complete. After setting the register, this function
1324 * reads the register immediately for returning the result of the backup
1325 * domain reset state. The reading register is important because the Read
1326 * itself takes multiple AHB clock cycles, and the reset is actually
1327 * finishing during that time. Use \ref Cy_SysLib_GetResetStatus to check
1328 * the BACKUP->RESET before any other BACKUP register write.
1329 *
1330 * \note This function also resets the WCO trimming value - use the
1331 * \ref Cy_SysLib_GetWcoTrim and \ref Cy_SysLib_SetWcoTrim to store/restore
1332 * the WCO trimming value.
1333 *
1334 * \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
1335 * Otherwise returns CY_SYSLIB_INVALID_STATE.
1336 *
1337 * \funcusage
1338 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1339 *
1340 *******************************************************************************/
1341 cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void);
1342
1343
1344 /*******************************************************************************
1345 * Function Name: Cy_SysLib_GetResetReason
1346 ****************************************************************************//**
1347 *
1348 * The function returns the cause for the latest reset(s) that occurred in
1349 * the system. The reset causes include system faults and
1350 * device reset on a wakeup from Hibernate mode. For M33SYSCPUSS IP,
1351 * the reset causes also include an HFCLK error.
1352 * The return results are consolidated reset causes from reading RES_CAUSE,
1353 * RES_CAUSE2 and PWR_HIBERNATE token registers.
1354 *
1355 * \return The cause of a system reset.
1356 * Return values to be checked as per the CPUSS IP of the device.
1357 *
1358 * | Name in M4CPUSS IP | Name in M33SYSCPUSS IP | Name in M7CPUSS IP | Value
1359 * |-------------------------------|------------------------------|----------------------------------|-------------------
1360 * | CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_HWWDT | 0x00001 (bit0)
1361 * | CY_SYSLIB_RESET_ACT_FAULT | CY_SYSLIB_RESET_ACT_FAULT | CY_SYSLIB_RESET_ACT_FAULT | 0x00002 (bit1)
1362 * | CY_SYSLIB_RESET_DPSLP_FAULT | CY_SYSLIB_RESET_DPSLP_FAULT | CY_SYSLIB_RESET_DPSLP_FAULT | 0x00004 (bit2)
1363 * | CY_SYSLIB_RESET_TC_DBGRESET | CY_SYSLIB_RESET_CSV_WCO_LOSS | CY_SYSLIB_RESET_TC_DBGRESET | 0x00008 (bit3)
1364 * | CY_SYSLIB_RESET_SOFT | CY_SYSLIB_RESET_SOFT | CY_SYSLIB_RESET_SOFT | 0x00010 (bit4)
1365 * | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT0 | 0x00020 (bit5)
1366 * | CY_SYSLIB_RESET_SWWDT1 | CY_SYSLIB_RESET_SWWDT1 | CY_SYSLIB_RESET_SWWDT1 | 0x00040 (bit6)
1367 * | CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT2 | 0x00080 (bit7)
1368 * | CY_SYSLIB_RESET_SWWDT3 | CY_SYSLIB_RESET_SWWDT3 | CY_SYSLIB_RESET_SWWDT3 | 0x00100 (bit8)
1369 * | | | | 0x00200 (bit9)
1370 * | | | | 0x00400 (bit10)
1371 * | | | | 0x00800 (bit11)
1372 * | | | | 0x01000 (bit12)
1373 * | | | | 0x02000 (bit13)
1374 * | | | | 0x04000 (bit14)
1375 * | | | | 0x08000 (bit15)
1376 * | | CY_SYSLIB_RESET_HFCLK_LOSS | CY_SYSLIB_RESET_XRES | 0x10000 (bit16)
1377 * | | CY_SYSLIB_RESET_HFCLK_ERR | CY_SYSLIB_RESET_BODVDDD | 0x20000 (bit17)
1378 * | | | CY_SYSLIB_RESET_BODVDDA | 0x40000 (bit18)
1379 * | | | CY_SYSLIB_RESET_BODVCCD | 0x80000 (bit19)
1380 * | | | CY_SYSLIB_RESET_OVDVDDD | 0x100000 (bit20)
1381 * | | | CY_SYSLIB_RESET_OVDVDDA | 0x200000 (bit21)
1382 * | | | CY_SYSLIB_RESET_OVDVCCD | 0x400000 (bit22)
1383 * | | | CY_SYSLIB_RESET_OCD_ACT_LINREG | 0x800000 (bit23)
1384 * | | | CY_SYSLIB_RESET_OCD_DPSLP_LINREG | 0x1000000 (bit24)
1385 * | | | CY_SYSLIB_RESET_OCD_REGHC | 0x2000000 (bit25)
1386 * | | | CY_SYSLIB_RESET_PMIC | 0x4000000 (bit26)
1387 * | | | | 0x8000000 (bit27)
1388 * | | | CY_SYSLIB_RESET_PXRES | 0x10000000 (bit28)
1389 * | | | CY_SYSLIB_RESET_STRUCT_XRES | 0x20000000 (bit29)
1390 * | | | CY_SYSLIB_RESET_PORVDDD | 0x40000000 (bit30)
1391 * | CY_SYSLIB_RESET_HIB_WAKEUP | CY_SYSLIB_RESET_HIB_WAKEUP | CY_SYSLIB_RESET_HIB_WAKEUP | 0x80000000 (bit31)
1392 * \note This not is available for devices having M33SYSCPUSS IP
1393 * CY_SYSLIB_RESET_CSV_WCO_LOSS, CY_SYSLIB_RESET_HFCLK_LOSS and
1394 * CY_SYSLIB_RESET_HFCLK_ERR causes of a system reset available only if
1395 * WCO CSV present in the device.
1396 *
1397 *******************************************************************************/
1398 uint32_t Cy_SysLib_GetResetReason(void);
1399
1400
1401 /*******************************************************************************
1402 * Function Name: Cy_SysLib_ClearResetReason
1403 ****************************************************************************//**
1404 *
1405 * This function clears the values of RES_CAUSE and RES_CAUSE2. Also it clears
1406 * PWR_HIBERNATE token, which indicates reset event on waking up from HIBERNATE.
1407 *
1408 *******************************************************************************/
1409 void Cy_SysLib_ClearResetReason(void);
1410
1411
1412 #if defined(CY_INIT_CODECOPY_ENABLE)
1413 CY_SECTION_INIT_CODECOPY_BEGIN
1414 #endif
1415
1416 /*******************************************************************************
1417 * Function Name: Cy_SysLib_GetResetStatus
1418 ****************************************************************************//**
1419 *
1420 * This function returns the BACKUP->RESET bit value.
1421 * It is reused by the \ref Cy_SysLib_ResetBackupDomain itself and also intended to
1422 * check for CY_SYSLIB_SUCCESS in loop after the \ref Cy_SysLib_ResetBackupDomain call.
1423 *
1424 * \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
1425 * when the reset is complete. After setting the register, this function
1426 * reads the register immediately for returning the result of the backup
1427 * domain reset state. The reading register is important because the Read
1428 * itself takes multiple AHB clock cycles, and the reset is actually
1429 * finishing during that time.
1430 *
1431 * \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
1432 * Otherwise returns CY_SYSLIB_INVALID_STATE.
1433 *
1434 * \funcusage
1435 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_ResetBackup
1436 *
1437 *******************************************************************************/
Cy_SysLib_GetResetStatus(void)1438 __STATIC_INLINE cy_en_syslib_status_t Cy_SysLib_GetResetStatus (void)
1439 {
1440 return ((0UL == (BACKUP_RESET & BACKUP_RESET_RESET_Msk)) ? CY_SYSLIB_SUCCESS : CY_SYSLIB_INVALID_STATE);
1441 }
1442
1443 #if defined (CY_IP_MXS40SRSS)
1444 /*******************************************************************************
1445 * Function Name: Cy_SysLib_GetWcoTrim
1446 ****************************************************************************//**
1447 *
1448 * This function returns the BACKUP->TRIM bitfield value.
1449 * It is intended to store the WCO trimming value before
1450 * the \ref Cy_SysLib_ResetBackupDomain usage.
1451 *
1452 * \return The WCO trimming value.
1453 *
1454 * \funcusage
1455 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1456 *
1457 *******************************************************************************/
Cy_SysLib_GetWcoTrim(void)1458 __STATIC_INLINE uint32_t Cy_SysLib_GetWcoTrim (void)
1459 {
1460 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)
1461 return 0;
1462 #else
1463 return (BACKUP_TRIM & BACKUP_TRIM_TRIM_Msk);
1464 #endif
1465 }
1466
1467
1468 /*******************************************************************************
1469 * Function Name: Cy_SysLib_SetWcoTrim
1470 ****************************************************************************//**
1471 *
1472 * This function writes the value into the BACKUP->TRIM bitfield.
1473 * It is intended to restore the WCO trimming value after
1474 * the \ref Cy_SysLib_ResetBackupDomain usage.
1475 *
1476 * \param wcoTrim The WCO trimming value.
1477 *
1478 * \funcusage
1479 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1480 *
1481 *******************************************************************************/
Cy_SysLib_SetWcoTrim(uint32_t wcoTrim)1482 __STATIC_INLINE void Cy_SysLib_SetWcoTrim (uint32_t wcoTrim)
1483 {
1484 CY_UNUSED_PARAMETER(wcoTrim);
1485 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2))
1486 BACKUP_TRIM = wcoTrim & BACKUP_TRIM_TRIM_Msk;
1487 #endif
1488 }
1489 #endif /* CY_IP_MXS40SRSS */
1490
1491 #if defined(CY_INIT_CODECOPY_ENABLE)
1492 CY_SECTION_INIT_CODECOPY_END
1493 #endif
1494
1495 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
1496
1497
1498 /*******************************************************************************
1499 * Function Name: Cy_SysLib_FaultHandler
1500 ****************************************************************************//**
1501 *
1502 * This function stores the ARM Cortex registers into a non-zero init area for
1503 * debugging. This function calls Cy_SysLib_ProcessingFault() after storing all
1504 * information.
1505 *
1506 * \param faultStackAddr The address of the stack pointer, indicates the lowest
1507 * address in the fault stack frame to be stored.
1508 * \note This function stores the fault stack frame only for the first occurred
1509 * fault.
1510 * \note The PDL doesn't provide an API to analyze the stored register
1511 * values. The user has to add additional functions for the analysis,
1512 * if necessary.
1513 * \note The CY_ARM_FAULT_DEBUG macro defines if the Fault Handler is enabled.
1514 * By default it is set to CY_ARM_FAULT_DEBUG_ENABLED and enables the
1515 * Fault Handler.
1516 * If there is a necessity to save memory or have some specific custom
1517 * handler, etc. then CY_ARM_FAULT_DEBUG should be redefined as
1518 * CY_ARM_FAULT_DEBUG_DISABLED. To do this, the following definition should
1519 * be added to the compiler Command Line (through the project Build
1520 * Settings): "-D CY_ARM_FAULT_DEBUG=0".
1521 *
1522 *******************************************************************************/
1523 void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr);
1524
1525
1526 /*******************************************************************************
1527 * Function Name: Cy_SysLib_ProcessingFault
1528 ****************************************************************************//**
1529 *
1530 * This function determines how to process the current fault state. By default
1531 * in case of exception the system will stay in the infinite loop of this
1532 * function.
1533 *
1534 * \note This function has the WEAK option, so the user can redefine the function
1535 * behavior for a custom processing.
1536 * For example, the function redefinition could be constructed from fault
1537 * stack processing and NVIC_SystemReset() function call.
1538 *
1539 *******************************************************************************/
1540 void Cy_SysLib_ProcessingFault(void);
1541 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
1542
1543 /*******************************************************************************
1544 * Function Name: Cy_SysLib_SetWaitStates
1545 ****************************************************************************//**
1546 *
1547 * Sets the number of clock cycles the cache will wait for, before it samples
1548 * data coming back from ROM, SRAM, and Flash.
1549 *
1550 * Call this function before increasing the HFClk0 High Frequency clock.
1551 * Call this function optionally after lowering the HFClk0 High Frequency clock
1552 * in order to improve the CPU performance.
1553 *
1554 * Also, call this function before switching the core supply regulator voltage
1555 * (LDO or SIMO Buck) from 1.1V to 0.9V.
1556 * Call this function optionally after switching the core supply regulator
1557 * voltage from 0.9V to 1.1V in order to improve the CPU performance.
1558 *
1559 * \param ulpMode The device power mode.
1560 * true if the device should be switched to the ULP mode (nominal
1561 * voltage of the core supply regulator should be switched to 0.9V);
1562 * false if the device should be switched to the LP mode (nominal
1563 * voltage of the core supply regulator should be switched to 1.1V).
1564 *
1565 * \note Refer to the device TRM for the low power modes description.
1566 *
1567 * \param clkHfMHz The HFClk0 clock frequency in MHz. Specifying a frequency
1568 * above the supported maximum will set the wait states as for
1569 * the maximum frequency.
1570 *
1571 *******************************************************************************/
1572 void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz);
1573
1574
1575 /*******************************************************************************
1576 * Function Name: Cy_SysLib_EnterCriticalSection
1577 ****************************************************************************//**
1578 *
1579 * Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
1580 * indicating whether the interrupts were previously enabled.
1581 *
1582 * \return Returns the current interrupt status. Returns 0 if the interrupts
1583 * were previously enabled or 1 if the interrupts were previously
1584 * disabled.
1585 *
1586 * \note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
1587 * enable bit with interrupts still enabled.
1588 *
1589 *******************************************************************************/
1590 uint32_t Cy_SysLib_EnterCriticalSection(void);
1591
1592
1593 /*******************************************************************************
1594 * Function Name: Cy_SysLib_ExitCriticalSection
1595 ****************************************************************************//**
1596 *
1597 * Re-enables the interrupts if they were enabled before
1598 * Cy_SysLib_EnterCriticalSection() was called. The argument should be the value
1599 * returned from \ref Cy_SysLib_EnterCriticalSection().
1600 *
1601 * \param savedIntrStatus Puts the saved interrupts status returned by
1602 * the \ref Cy_SysLib_EnterCriticalSection().
1603 *
1604 *******************************************************************************/
1605 void Cy_SysLib_ExitCriticalSection(uint32_t savedIntrStatus);
1606
1607
1608 /*******************************************************************************
1609 * Function Name: Cy_SysLib_GetDeviceRevision
1610 ****************************************************************************//**
1611 *
1612 * This function returns a device Revision ID.
1613 *
1614 * \return A device Revision ID.
1615 *
1616 *******************************************************************************/
1617 uint8_t Cy_SysLib_GetDeviceRevision(void);
1618
1619 /*******************************************************************************
1620 * Function Name: Cy_SysLib_GetDevice
1621 ****************************************************************************//**
1622 *
1623 * This function returns a device Family ID.
1624 *
1625 * \return A device Family ID.
1626 *
1627 *******************************************************************************/
1628 uint16_t Cy_SysLib_GetDevice(void);
1629
1630 #if defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
1631 /*******************************************************************************
1632 * Function Name: Cy_SysLib_GetDeviceLCS
1633 ****************************************************************************//**
1634 *
1635 * This function returns LCS of Device.
1636 *
1637 * \return \ref cy_en_syslib_lcs_mode_t
1638 *
1639 *******************************************************************************/
1640 cy_en_syslib_lcs_mode_t Cy_SysLib_GetDeviceLCS(void);
1641 #endif /* defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) */
1642
1643 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
1644 /*******************************************************************************
1645 * Function Name: Cy_Syslib_SetWarmBootEntryPoint
1646 ****************************************************************************//**
1647 *
1648 * This function will set Warm boot entry point address to a location read by
1649 * BootROM. This function is used only before entering DeepSleep-RAM and not
1650 * effective in any other sleep mode. Before entering CY_SYSPM_MODE_DEEPSLEEP_RAM,
1651 * user needs to set entry point to a function located in RAM Image using
1652 * Cy_Syslib_SetWarmBootEntryPoint(), refer Cy_SysPm_SetDeepSleepMode().
1653 *
1654 * \param entryPoint Address of the function that needs to be entered after
1655 * WARM boot.
1656 *
1657 * \param enable Enables/Disables debugging control after DS-RAM wakeup
1658 * i.e. warmboot
1659 *
1660 * \note
1661 * This API is available for CAT1B devices.
1662 *
1663 *******************************************************************************/
1664 void Cy_Syslib_SetWarmBootEntryPoint(uint32_t *entryPoint, bool enable);
1665
1666 /*******************************************************************************
1667 * Function Name: Cy_SysLib_IsDSRAMWarmBootEntry
1668 ****************************************************************************//**
1669 *
1670 * This function will return true if the system woke up(From DS-RAM) through
1671 * Warm boot, else it will return false.
1672 *
1673 * \return Warm Boot Status.
1674 *
1675 * \note
1676 * This API is available for CAT1B devices.
1677 *
1678 *******************************************************************************/
1679 bool Cy_SysLib_IsDSRAMWarmBootEntry(void);
1680
1681 /*******************************************************************************
1682 * Function Name: Cy_SysLib_ClearDSRAMWarmBootEntryStatus
1683 ****************************************************************************//**
1684 *
1685 * This function clears the Warm Boot entry Status flag.
1686 *
1687 * \note
1688 * This API is available for CAT1B devices.
1689 *
1690 *******************************************************************************/
1691 void Cy_SysLib_ClearDSRAMWarmBootEntryStatus(void);
1692 #endif
1693
1694
1695 /** \cond INTERNAL */
1696 #define CY_SYSLIB_DEVICE_REV_0A (0x21U) /**< The device TO *A Revision ID */
1697 #define CY_SYSLIB_DEVICE_PSOC6ABLE2 (0x100U) /**< The PSoC6 BLE2 device Family ID */
1698
1699 /* SILICON ID Macros */
1700 #define CY_SYSLIB_GET_SILICON_REV_ID (CY_SILICON_ID & 0xFFFFUL)
1701
1702 /* For CAT1B Devices */
1703 #define CY_SYSLIB_20829A0_SILICON_REV (0x1110UL) /**< 20829A0 SILICON ID = <Major Revision((4 bits): Family ID(12 bits)> */
1704 #define CY_SYSLIB_20829B0_SILICON_REV (0x2110UL) /**< 20829B0 SILICON ID = <Major Revision((4 bits): Family ID(12 bits)> */
1705
1706 typedef uint32_t cy_status;
1707 /** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */
1708 typedef uint32_t cystatus;
1709 typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */
1710 typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */
1711 typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */
1712 typedef int8_t int8; /**< Alias to int8_t for backward compatibility */
1713 typedef int16_t int16; /**< Alias to int16_t for backward compatibility */
1714 typedef int32_t int32; /**< Alias to int32_t for backward compatibility */
1715 typedef float float32; /**< Alias to float for backward compatibility */
1716 typedef double float64; /**< Alias to double for backward compatibility */
1717 typedef int64_t int64; /**< Alias to int64_t for backward compatibility */
1718 typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */
1719 /* Signed or unsigned depending on the compiler selection */
1720 typedef char char8; /**< Alias to char for backward compatibility */
1721 typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */
1722 typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */
1723 typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */
1724
1725 /** The ARM 32-bit Return error / status code for backward compatibility.
1726 * Do not use them in your code.
1727 */
1728 #define CY_RET_SUCCESS (0x00U) /* Successful */
1729 #define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */
1730 #define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */
1731 #define CY_RET_MEMORY (0x03U) /* A memory-related failure */
1732 #define CY_RET_LOCKED (0x04U) /* A resource lock failure */
1733 #define CY_RET_EMPTY (0x05U) /* No more objects available */
1734 #define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
1735 #define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
1736 #define CY_RET_FINISHED (0x08U) /* Operation is completed */
1737 #define CY_RET_CANCELED (0x09U) /* Operation is canceled */
1738 #define CY_RET_TIMEOUT (0x10U) /* Operation timed out */
1739 #define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
1740 #define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */
1741
1742 /** ARM 32-bit Return error / status codes for backward compatibility with the UDB components.
1743 * Do not use them in your code.
1744 */
1745 #define CYRET_SUCCESS (0x00U) /* Successful */
1746 #define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */
1747 #define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */
1748 #define CYRET_MEMORY (0x03U) /* A memory-related failure */
1749 #define CYRET_LOCKED (0x04U) /* A resource lock failure */
1750 #define CYRET_EMPTY (0x05U) /* No more objects available */
1751 #define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
1752 #define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
1753 #define CYRET_FINISHED (0x08U) /* Operation is completed */
1754 #define CYRET_CANCELED (0x09U) /* Operation is canceled */
1755 #define CYRET_TIMEOUT (0x10U) /* Operation timed out */
1756 #define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
1757 #define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */
1758
1759 /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
1760 typedef void (* cyisraddress)(void);
1761 #if defined (__ICCARM__)
1762 /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
1763 typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
1764 #endif /* defined (__ICCARM__) */
1765
1766 /** The backward compatibility define for the CyDelay() API for the UDB components.
1767 * Do not use it in your code.
1768 */
1769 #define CyDelay Cy_SysLib_Delay
1770 /** The backward compatibility define for the CyDelayUs() API for the UDB components.
1771 * Do not use it in your code.
1772 */
1773 #define CyDelayUs Cy_SysLib_DelayUs
1774 /** The backward compatibility define for the CyDelayCycles() API for the UDB components.
1775 * Do not use it in your code.
1776 */
1777 #define CyDelayCycles Cy_SysLib_DelayCycles
1778 /** The backward compatibility define for the CyEnterCriticalSection() API for the UDB components.
1779 * Do not use it in your code.
1780 */
1781 #define CyEnterCriticalSection() ((uint8_t) Cy_SysLib_EnterCriticalSection())
1782 /** The backward compatibility define for the CyExitCriticalSection() API for the UDB components.
1783 * Do not use it in your code.
1784 */
1785 #define CyExitCriticalSection(x) (Cy_SysLib_ExitCriticalSection((uint32_t) (x)))
1786 /** \endcond */
1787
1788 /** \} group_syslib_functions */
1789 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
1790 /** \cond INTERNAL */
1791
1792 /** \endcond */
1793
1794
1795 #if defined(__cplusplus)
1796 }
1797 #endif /* defined(__cplusplus) */
1798
1799 #endif /* CY_IP_M33SYSCPUSS, CY_IP_M4CPUSS */
1800
1801 #endif /* CY_SYSLIB_H */
1802
1803 /** \} group_syslib */
1804
1805 /* [] END OF FILE */
1806
