1 /***************************************************************************//** 2 * \file cy_sysint.h 3 * \version 1.120 4 * 5 * \brief 6 * Provides an API declaration of the SysInt driver 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 11 * an affiliate of Cypress Semiconductor Corporation. 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_sysint 29 * \{ 30 * The SysInt driver provides an API to configure the device peripheral interrupts. 31 * It provides a lightweight interface to complement 32 * the <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html">CMSIS core NVIC API</a>. 33 * The provided functions are applicable for all cores in a device and they can 34 * be used to configure and connect device peripheral interrupts to one or more 35 * cores. 36 * 37 * The functions and other declarations used in this driver are in cy_sysint.h. 38 * You can include cy_pdl.h to get access to all functions 39 * and declarations in the PDL. 40 * 41 * \section group_sysint_vector_table Vector Table 42 * \subsection group_sysint_CM0_CM4 CM0+/CM4 43 * The vector table defines the entry addresses of the processor exceptions and 44 * the device specific interrupts. It is located at the start address of the flash 45 * and is copied by the startup code to RAM. The symbol code __Vectors is the 46 * address of the vector table in the startup code and the register SCB->VTOR 47 * holds the start address of the vector table. See \ref group_system_config_device_vector_table 48 * section for the implementation details. 49 * The default interrupt handler functions are defined as weak functions to a dummy handler 50 * in the startup file. The naming convention is \<interrupt_name\>_IRQHandler. 51 * 52 * Defining these in the user application allows the linker to place them in 53 * the vector table in flash/ROM. For example: 54 * \code 55 * void ioss_interrupts_gpio_0_IRQHandler(void) 56 * { 57 * ... 58 * } 59 * \endcode 60 * And can be used like this: 61 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_flashVT 62 * Using this method avoids the need for a RAM vector table. However in this scenario, 63 * interrupt handler re-location at run-time is not possible, unless the vector table is 64 * relocated to RAM. 65 * 66 * \subsection group_sysint_CM33 CM33 67 * CM33 with Security extension supports two vector tables, one for secure world and another 68 * for non-secure world. Secure interrupt vector table is placed in the secure ROM/FLASH, where as 69 * non-secure interrupt vector table is placed in the non-secure ROM/FLASH. In both scenarios, 70 * vector tables are copied by the startup code to secure and non-secure RAM respectively. 71 * The symbol code __s_vector_table is the address of the secure vector table and 72 * __ns_vector_table is for the non-secure world in the startup code. The register SCB->VTOR 73 * holds the start address of the vector table. See \ref group_system_config_device_vector_table 74 * section for the implementation details. 75 * 76 * CM33 without Security extension will support only non-secure interrupts. 77 * 78 * The default interrupt handler functions are defined to a dummy handler in the startup file. 79 * The naming convention is \<interrupt_name\>_IRQHandler. 80 * 81 * \subsection group_sysint_CM55 CM55 82 * CM55 is without Security extension and will support only non-secure interrupts. It is similar to CM33 non-secure part. 83 * Additionally CM55 core has support to block EWIC (External Wakeup Interrupt Controller). EWIC is a peripheral to the processor 84 * and it can be a source of wakeup in the system. EWIC block is disabled by default and needs to be enabled in order for the DS 85 * wakeup source to work. 86 * 87 * \subsection group_sysint_CM0_CM7 CAT1C CM0+/CM7 88 * The vector table defines the entry addresses of the processor exceptions and 89 * the device specific interrupts. Interrupt vector table is placed in the ROM/FLASH. The 90 * vector table is copied by the startup code to RAM. The symbol code __ramVectors is the address of the vector table. 91 * The register SCB->VTOR holds the start address of the vector table. See \ref group_system_config_device_vector_table 92 * section for the implementation details. 93 * Each system interrupt has to be mapped onto one out of eight external CPU interrupts. When a system interrupt is triggered, corresponding mapped 94 * CPU IRQ gets triggered which results in the execution of the default CPU IRQ handler. In this handler the system interrupt mapped to this 95 * CPU interrupt will be fetched and executed. 96 * 97 * The default CPU IRQ handler functions are defined as weak functions in the startup file. 98 * The naming convention followed is \<core\>_CpuIntr\<interrupt_number\>_Handler. 99 * Below is the code snippet. 100 * \code 101 * void Interrupt_Handler_Port0(void) 102 * { 103 * ... //User interrupt handler 104 * } 105 * \endcode 106 107 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init 108 * 109 * \section group_sysint_driver_usage Driver Usage 110 * 111 * \subsection group_sysint_initialization Initialization 112 * 113 * Interrupt numbers are defined in a device-specific header file, such as 114 * cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the 115 * vector table. 116 * 117 * To configure an interrupt, call Cy_SysInt_Init(). Populate 118 * the configuration structure (cy_stc_sysint_t) and pass it as a parameter 119 * along with the ISR address. This initializes the interrupt and 120 * instructs the CPU to jump to the specified ISR vector upon a valid trigger. 121 * For CM0+ core, the configuration structure (cy_stc_sysint_t) 122 * must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC 123 * mux (intrSrc). 124 * 125 * For CM4/CM33/CM55 core, system interrupt source 'n' is connected to the 126 * corresponding IRQn. Deep-sleep capable interrupts are allocated to Deep Sleep 127 * capable IRQn channels. 128 * 129 * For CAT1C CM7/CM0+ core, the configuration structure (cy_stc_sysint_t) must specify 130 * system interrupt source, CPU IRQ and the CPU IRQ priority. The system interrupt source is mapped to bit 0-15 of intrSrc parameter 131 * and CPU IRQ is mapped to bit 16-31 of intrSrc parameter. 132 * 133 * For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR 134 * parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the 135 * capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source 136 * must be connected to one of these muxes to be able to trigger in Deep Sleep. 137 * Refer to the IRQn_Type definition in the device header. 138 * 139 * 1. For CPUSS_ver1 the CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device 140 * interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer 141 * at each of the 32 NVIC channels. 142 * 143 * 2. For CPUSS_ver2 the CM0+ core supports up to 8 hardware interrupt channels (IRQn 0-7) and software-only 144 * interrupt channels (IRQn 8-15). The device has up to 1023 interrupts that can be connected to any of the 145 * hardware interrupt channels. In this structure, multiple interrupt sources can be connected 146 * simultaneously to one NVIC channel. The application must then query the interrupt source on the 147 * channel and service the active interrupt(s). The priority of these interrupts is determined by the 148 * interrupt number as defined in the cy_en_intr_t enum, where the lower number denotes higher priority 149 * over the higher number. 150 * 151 * \subsection group_sysint_enable Enable 152 * 153 * After initializing an interrupt, use the CMSIS Core 154 * <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ()</a> function 155 * to enable it. Given an initialization structure named config, 156 * the function should be called as follows: 157 * \code 158 * NVIC_EnableIRQ(config.intrSrc) 159 * \endcode 160 * 161 * \subsection group_sysint_service Writing an interrupt service routine 162 * 163 * Servicing interrupts in the Peripheral Drivers should follow a prescribed 164 * recipe to ensure all interrupts are serviced and duplicate interrupts are not 165 * received. Any peripheral-specific register that must be written to clear the 166 * source of the interrupt should be written as soon as possible in the interrupt 167 * service routine. However, note that due to buffering on the output bus to the 168 * peripherals, the write clearing of the interrupt may be delayed. After performing 169 * the normal interrupt service that should respond to the interrupting 170 * condition, the interrupt register that was initially written to clear the 171 * register should be read before returning from the interrupt service routine. 172 * This read ensures that the initial write has been flushed out to the hardware. 173 * Note, no additional processing should be performed based on the result of this 174 * read, as this read is intended only to ensure the write operation is flushed. 175 * 176 * This final read may indicate a pending interrupt. What this means is that in 177 * the interval between when the write actually happened at the peripheral and 178 * when the read actually happened at the peripheral, an interrupting condition 179 * occurred. This is ok and a return from the interrupt is still the correct 180 * action. As soon as conditions warrant, meaning interrupts are enabled and 181 * there are no higher priority interrupts pending, the interrupt will be 182 * triggered again to service the additional condition. 183 * 184 * \section group_sysint_section_configuration_considerations Configuration Considerations 185 * 186 * Certain CM0+ <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">NVIC IRQn</a> 187 * channels are reserved for system use: 188 * <table class="doxtable"> 189 * <tr><th>NVIC channel (\ref IRQn_Type)</th><th>Interrupt source (\ref cy_en_intr_t)</th><th>Purpose</th></tr> 190 * <tr><td>#0 (NvicMux0_IRQn)</td><td>IPC Interrupt #0 (cpuss_interrupts_ipc_0_IRQn)</td><td>System Calls to ROM</td></tr> 191 * <tr><td>#1 (NvicMux1_IRQn)</td><td>IPC Interrupt #3 (cpuss_interrupts_ipc_3_IRQn)</td><td>System IPC pipe in the default startup</td></tr> 192 * </table> 193 * 194 * \note For CPUSS_ver2, each NVIC channel can be shared between multiple interrupt sources. 195 * However it is not recommended to share the application NVIC channel with the reserved channels. 196 * 197 * \note In CAT1C, NvicMux0_IRQn and NvicMux1_IRQn are used by ROM and not meant for user. 198 * 199 * \section group_sysint_more_information More Information 200 * 201 * Refer to the technical reference manual (TRM) and the device datasheet. 202 * 203 * \section group_sysint_changelog Changelog 204 * <table class="doxtable"> 205 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 206 * <tr> 207 * <td>1.120</td> 208 * <td>Updated Pre-processor checks.</td> 209 * <td>Code enhancement.</td> 210 * </tr> 211 * <tr> 212 * <td>1.110</td> 213 * <td>Updated API \ref Cy_SysInt_Init.</td> 214 * <td>CM0P interrupt priority bug fix.</td> 215 * </tr> 216 * <tr> 217 * <td>1.100</td> 218 * <td>Added support for TRAVEO™ II Body Entry devices.<br> 219 * Pre-processor check for MXS40SRSS version now groups ver. 2 with ver. 3. Previously ver. 2 was grouped with ver. 1.</td> 220 * Added support for CM0+/CM4 dual core devices. Previously only supported CM0+/CM7 devices.</td> 221 * <td>Code enhancement and support for new devices.</td> 222 * </tr> 223 * <tr> 224 * <td>1.90.1</td> 225 * <td>Fixed MISRA 2012 8.5 and 8.6 violations.</td> 226 * <td>MISRA 2012 compliance..</td> 227 * </tr> 228 * <tr> 229 * <td>1.90</td> 230 * <td>Updated \ref Cy_SysInt_Init, \ref Cy_SysInt_SetVector and \ref Cy_SysInt_GetVector APIs.</td> 231 * <td>Code Clean up.</td> 232 * </tr> 233 * <tr> 234 * <td>1.80</td> 235 * <td>API's Cy_SysInt_SetInterruptSource(), Cy_SysInt_GetInterruptSource(), Cy_SysInt_DisconnectInterruptSource(), 236 * Cy_SysInt_SetNmiSource(), Cy_SysInt_GetNmiSource(), Cy_SysInt_SoftwareTrig(), Cy_SysInt_GetNvicConnection(), 237 * Cy_SysInt_GetInterruptActive(), Cy_SysInt_InitExtIRQ(), Cy_SysInt_InitIntIRQ(), Cy_SysInt_Init(), 238 * Cy_SysInt_SetVector(), Cy_SysInt_GetVector(), Cy_SysInt_SetSystemIrqVector(), Cy_SysInt_EnableSystemInt(), Cy_SysInt_DisableSystemInt() 239 * modified.</td> 240 * <td>New device support, Fix Coverity issues, Documentation enhancement.</td> 241 * </tr> 242 * <tr> 243 * <td>1.70</td> 244 * <td>Support for CAT1C, CAT1D.<br>Newly added API's Cy_SysInt_SetSystemIrqVector() to set the user ISR vector for the System Interrupt, 245 * Cy_SysInt_GetSystemIrqVector() to get the address of the current user ISR vector for the System Interrupt, 246 * Cy_SysInt_EnableSystemInt() to enable system interrupt, Cy_SysInt_DisableSystemInt() to disable system interrupt, 247 * Cy_SysInt_InitExtIRQ() to initialize the referenced external interrupt by setting the CPU IRQ priority and the interrupt vector, 248 * Cy_SysInt_InitIntIRQ() to initialize the referenced internal interrupt by setting the priority and the interrupt vector.</td> 249 * <td>New devices support.</td> 250 * </tr> 251 252 * <tr> 253 * <td>1.60</td> 254 * <td>Support for CM33.</td> 255 * <td>New devices support.</td> 256 * </tr> 257 * <tr> 258 * <td>1.50</td> 259 * <td>Fixed MISRA 2012 violations.</td> 260 * <td>MISRA 2012 compliance.</td> 261 * </tr> 262 * <tr> 263 * <td>1.40</td> 264 * <td>Updated the CY_SYSINT_IS_PC_0 macro to access the protected register 265 * for the secure CYB06xx7 devices via \ref group_pra driver. 266 * </td> 267 * <td>Added PSoC 64 devices support.</td> 268 * </tr> 269 * <tr> 270 * <td>1.30.1</td> 271 * <td>Minor documentation updates.</td> 272 * <td>Documentation enhancement.</td> 273 * </tr> 274 * <tr> 275 * <td>1.30</td> 276 * <td>The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.</td> 277 * <td>User experience enhancement.</td> 278 * </tr> 279 * <tr> 280 * <td>1.20.1</td> 281 * <td>The Vector Table section is extended with a code snippet.</td> 282 * <td>Documentation enhancement.</td> 283 * </tr> 284 * <tr> 285 * <td rowspan="3">1.20</td> 286 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td> 287 * <td>Driver library directory-structure simplification.</td> 288 * </tr> 289 * <tr> 290 * <td>Added CPUSS_ver2 support to the following API functions: 291 * - \ref Cy_SysInt_SetInterruptSource 292 * - \ref Cy_SysInt_SetNmiSource 293 * - \ref Cy_SysInt_GetNmiSource 294 * 295 * Added new API functions: 296 * - \ref Cy_SysInt_DisconnectInterruptSource 297 * - \ref Cy_SysInt_GetNvicConnection 298 * - \ref Cy_SysInt_GetInterruptActive 299 * 300 * Deprecated following functions: 301 * - Cy_SysInt_SetIntSource 302 * - Cy_SysInt_GetIntSource 303 * - Cy_SysInt_SetIntSourceNMI 304 * - Cy_SysInt_GetIntSourceNMI 305 * </td> 306 * <td>New devices support.</td> 307 * </tr> 308 * <tr> 309 * <td>Added register access layer. Use register access macros instead 310 * of direct register access using dereferenced pointers.</td> 311 * <td>Makes register access device-independent, so that the PDL does 312 * not need to be recompiled for each supported part number.</td> 313 * </tr> 314 * <tr> 315 * <td>1.10</td> 316 * <td>Cy_SysInt_GetState() function is redefined to call NVIC_GetEnableIRQ()</td> 317 * <td></td> 318 * </tr> 319 * <tr> 320 * <td>1.0</td> 321 * <td>Initial version</td> 322 * <td></td> 323 * </tr> 324 * </table> 325 * 326 * \defgroup group_sysint_macros Macros 327 * \defgroup group_sysint_globals Global variables 328 * \defgroup group_sysint_functions Functions 329 * \defgroup group_sysint_data_structures Data Structures 330 * \defgroup group_sysint_enums Enumerated Types 331 */ 332 333 334 #if !defined (CY_SYSINT_H) 335 #define CY_SYSINT_H 336 337 #include "cy_device.h" 338 339 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS) 340 341 #include <stddef.h> 342 #include "cy_syslib.h" 343 #if defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) 344 #include "cy_pra.h" 345 #endif /* defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */ 346 #include "cy_device_headers.h" 347 348 #if defined(__cplusplus) 349 extern "C" { 350 #endif 351 352 /*************************************** 353 * Global Variable 354 ***************************************/ 355 356 /** 357 * \addtogroup group_sysint_globals 358 * \{ 359 */ 360 361 #if defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) 362 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 2, \ 363 'Coverity does not check the .S assembly files, the definition is a part of startup_psoc6_04_cm4.s file.') 364 extern const cy_israddress __Vectors[]; /**< Vector table in flash */ 365 extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ 366 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6') 367 368 #endif /* defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) */ 369 /** \} group_sysint_globals */ 370 371 372 /*************************************** 373 * Global Interrupt 374 ***************************************/ 375 376 /** 377 * \addtogroup group_sysint_macros 378 * \{ 379 */ 380 381 /** Driver major version */ 382 #define CY_SYSINT_DRV_VERSION_MAJOR 1 383 384 /** Driver minor version */ 385 #define CY_SYSINT_DRV_VERSION_MINOR 120 386 387 /** SysInt driver ID */ 388 #define CY_SYSINT_ID CY_PDL_DRV_ID (0x15U) 389 390 /** \} group_sysint_macros */ 391 392 393 /*************************************** 394 * Enumeration 395 ***************************************/ 396 397 /** 398 * \addtogroup group_sysint_enums 399 * \{ 400 */ 401 402 /** 403 * SysInt Driver error codes 404 */ 405 typedef enum 406 { 407 CY_SYSINT_SUCCESS = 0x0UL, /**< Returned successful */ 408 CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< Bad parameter was passed */ 409 } cy_en_sysint_status_t; 410 411 /** NMI connection input */ 412 typedef enum 413 { 414 CY_SYSINT_NMI1 = 1UL, /**< NMI source input 1 */ 415 CY_SYSINT_NMI2 = 2UL, /**< NMI source input 2 */ 416 CY_SYSINT_NMI3 = 3UL, /**< NMI source input 3 */ 417 CY_SYSINT_NMI4 = 4UL, /**< NMI source input 4 */ 418 } cy_en_sysint_nmi_t; 419 420 /** \} group_sysint_enums */ 421 422 423 /*************************************** 424 * Configuration Structure 425 ***************************************/ 426 427 /** 428 * \addtogroup group_sysint_data_structures 429 * \{ 430 */ 431 432 /** 433 * Initialization configuration structure for a single interrupt channel 434 */ 435 typedef struct { 436 #if defined (CY_IP_M7CPUSS) 437 uint32_t intrSrc; /**< Bit 0-15 indicate system interrupt and bit 16-31 will indicate the CPU IRQ */ 438 #else 439 IRQn_Type intrSrc; /**< Interrupt source */ 440 #endif 441 #if (CY_CPU_CORTEX_M0P) && defined (CY_IP_M4CPUSS) 442 cy_en_intr_t cm0pSrc; /**< Maps cm0pSrc device interrupt to intrSrc */ 443 #endif /* CY_CPU_CORTEX_M0P */ 444 uint32_t intrPriority; /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */ 445 } cy_stc_sysint_t; 446 447 /** \} group_sysint_data_structures */ 448 449 #if defined (CY_IP_M7CPUSS) 450 #define CY_SYSINT_INTRSRC_MASK (0xFFFFUL) /**< Bit 0-15 indicate system interrupt and bit 16-31 will indicate the CPU IRQ */ 451 #define CY_SYSINT_INTRSRC_MUXIRQ_SHIFT (16UL) /**< Bit 0-15 indicate system interrupt and bit 16-31 will indicate the CPU IRQ */ 452 #else /* Applicable for Mux'ed IRQ CM4 interrupts */ 453 #define CY_SYSINT_INTRSRC_MASK (0x0FFFUL) /**< Bit 0-11 indicate system interrupt and bit 12-15 will indicate the CPU IRQ */ 454 #define CY_SYSINT_INTRSRC_MUXIRQ_SHIFT (12UL) /**< Bit 0-11 indicate system interrupt and bit 12-15 will indicate the CPU IRQ */ 455 #endif /* defined (CY_IP_M7CPUSS) */ 456 457 458 /*************************************** 459 * Constants 460 ***************************************/ 461 462 /** \cond INTERNAL */ 463 464 #define CY_INT_IRQ_BASE (16U) /**< Start location of interrupts in the vector table */ 465 #define CY_SYSINT_STATE_MASK (1UL) /**< Mask for interrupt state */ 466 #define CY_SYSINT_STIR_MASK (0xFFUL) /**< Mask for software trigger interrupt register */ 467 #define CY_SYSINT_DISABLE (0UL) /**< Disable interrupt */ 468 #define CY_SYSINT_ENABLE (1UL) /**< Enable interrupt */ 469 #define CY_SYSINT_INT_STATUS_MSK (0x7UL) 470 471 #if defined (CY_IP_M4CPUSS) 472 /*(CY_IP_M4CPUSS_VERSION == 1u) */ 473 #define CY_SYSINT_CM0P_MUX_MASK (0xFFUL) /**< CM0+ NVIC multiplexer mask */ 474 #define CY_SYSINT_CM0P_MUX_SHIFT (2U) /**< CM0+ NVIC multiplexer shift */ 475 #define CY_SYSINT_CM0P_MUX_SCALE (3U) /**< CM0+ NVIC multiplexer scaling value */ 476 #define CY_SYSINT_CM0P_MUX0 (0U) /**< CM0+ NVIC multiplexer register 0 */ 477 #define CY_SYSINT_CM0P_MUX1 (1U) /**< CM0+ NVIC multiplexer register 1 */ 478 #define CY_SYSINT_CM0P_MUX2 (2U) /**< CM0+ NVIC multiplexer register 2 */ 479 #define CY_SYSINT_CM0P_MUX3 (3U) /**< CM0+ NVIC multiplexer register 3 */ 480 #define CY_SYSINT_CM0P_MUX4 (4U) /**< CM0+ NVIC multiplexer register 4 */ 481 #define CY_SYSINT_CM0P_MUX5 (5U) /**< CM0+ NVIC multiplexer register 5 */ 482 #define CY_SYSINT_CM0P_MUX6 (6U) /**< CM0+ NVIC multiplexer register 6 */ 483 #define CY_SYSINT_CM0P_MUX7 (7U) /**< CM0+ NVIC multiplexer register 7 */ 484 #define CY_SYSINT_MUX_REG_MSK (0x7UL) 485 #endif /* CY_IP_M4CPUSS */ 486 487 /* Parameter validation macros */ 488 #define CY_SYSINT_IS_PRIORITY_VALID(intrPriority) ((uint32_t)(1UL << __NVIC_PRIO_BITS) > (intrPriority)) 489 #define CY_SYSINT_IS_VECTOR_VALID(userIsr) (NULL != (userIsr)) 490 #define CY_SYSINT_IS_NMI_NUM_VALID(nmiNum) (((nmiNum) == CY_SYSINT_NMI1) || \ 491 ((nmiNum) == CY_SYSINT_NMI2) || \ 492 ((nmiNum) == CY_SYSINT_NMI3) || \ 493 ((nmiNum) == CY_SYSINT_NMI4)) 494 #if defined (CY_IP_M4CPUSS) 495 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) 496 #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, \ 497 CY_PRA_REG32_GET(CY_PRA_INDX_PROT_MPU_MS_CTL))) 498 #else 499 #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(0U))) 500 #endif 501 #endif /* CY_IP_M4CPUSS */ 502 /** \endcond */ 503 504 505 /*************************************** 506 * Function Prototypes 507 ***************************************/ 508 509 /** 510 * \addtogroup group_sysint_functions 511 * \{ 512 */ 513 514 515 /******************************************************************************* 516 * Function Name: Cy_SysInt_Init 517 ****************************************************************************//** 518 * 519 * \brief Initializes the referenced interrupt by setting the priority and the 520 * interrupt vector. 521 * In case of CM33 with Security Extension enabled, if this function is called 522 * from secure world then, the parameters are used to configure secure interrupt. 523 * If it is called form non-secure world then the parameters are used to configure 524 * non-secure interrupt. In case of CM33 without Security Extension, this function 525 * always configures the non-secure interrupt. 526 * In case of CM55, this function always configures the non-secure interrupt. 527 * In case of CM7/CM0+ it initializes the external system interrupt, maps it to CPU interrupt and 528 * registers the User ISR vector for the System Interrupt. 529 * 530 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 531 * 532 * \param config 533 * Interrupt configuration structure 534 * 535 * \param userIsr 536 * Address of the ISR 537 * 538 * \return 539 * Initialization status 540 * 541 * \note CM0+/CM4 <br/> 542 * The interrupt vector will be relocated only if the vector table was 543 * moved to __ramVectors in SRAM. Otherwise it is ignored. 544 * 545 * \note CM33<br/> 546 * The interrupt vector will be relocated only if the vector table was 547 * moved to __s_vector_table_rw and __ns_vector_table_rw for secure and 548 * non-secure world respectively. 549 * 550 * \note CM55<br/> 551 * The interrupt vector will be relocated only if the vector table was 552 * moved to __ns_vector_table_rw non-secure world. 553 * 554 * \funcusage 555 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init 556 * 557 *******************************************************************************/ 558 cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr); 559 560 561 /******************************************************************************* 562 * Function Name: Cy_SysInt_SetVector 563 ****************************************************************************//** 564 * 565 * \brief Changes the ISR vector for the interrupt. 566 * 567 * CM0+/CM4 (non-TVIIBE):<br/> 568 * This function relies on the assumption that the vector table is 569 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 570 * return the address of the default ISR location in the flash vector table. 571 * 572 * CM0+/CM7 and TVIIBE CM0+/CM4:<br/> 573 * This function relies on the assumption that the vector table is 574 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 575 * return the address of the default ISR location in the flash vector table. 576 * This function is applicable only to User Interrupts (NvicMux0_IRQn - NvicMux7_IRQn) 577 * and System Interrupts (Internal0_IRQn - Internal0_IRQn). 578 * 579 * CM33:<br/> 580 * When called from secure world. this function relies on the assumption that the 581 * vector table is relocated to __s_vector_table_rw[] in secure SRAM. Otherwise it will 582 * return the address of the default ISR location in the secure flash/ROM vector table. 583 * 584 * When called from non-secure world. this function relies on the assumption that 585 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 586 * Otherwise it will return the address of the default ISR location in the non-secure 587 * flash/ROM vector table. 588 * 589 * CM55:<br/> 590 * This function relies on the assumption that 591 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 592 * Otherwise it will return the address of the default ISR location in the non-secure 593 * flash/ROM vector table. 594 * 595 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 596 * \param IRQn 597 * Interrupt source 598 * 599 * \param userIsr 600 * Address of the ISR to set in the interrupt vector table 601 * 602 * \return 603 * Previous address of the ISR in the interrupt vector table 604 * 605 * \note For CM0+, this function sets the interrupt vector for the interrupt 606 * channel on the NVIC. 607 * 608 * \note In case of CM33 with Security Extension enabled, if this function is called 609 * from secure world then, it sets the interrupt vector for the secure world. 610 * If it is called form non-secure world then it sets the interrupt vector for the 611 * non-secure world. 612 * 613 * \funcusage 614 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector 615 * 616 *******************************************************************************/ 617 cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr); 618 619 620 /******************************************************************************* 621 * Function Name: Cy_SysInt_GetVector 622 ****************************************************************************//** 623 * 624 * \brief Gets the address of the current ISR vector for the interrupt. 625 * 626 * CM0+/CM4:<br/> 627 * This function relies on the assumption that the vector table is 628 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 629 * return the address of the default ISR location in the flash vector table. 630 * 631 * CM0+/CM7:<br/> 632 * This function relies on the assumption that the vector table is 633 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 634 * return the address of the default ISR location in the flash vector table. 635 * This function is applicable only to User Interrupts (NvicMux0_IRQn - NvicMux7_IRQn) 636 * and System Interrupts (Internal0_IRQn - Internal0_IRQn). 637 * 638 * CM33:<br/> 639 * When called from the secure world, this function relies on the assumption that 640 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 641 * Otherwise it will return the address of the default ISR location in the 642 * flash/ROM vector table. 643 * 644 * CM55:<br/> 645 * This function relies on the assumption that 646 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 647 * Otherwise it will return the address of the default ISR location in the 648 * flash/ROM vector table. 649 * 650 * \param IRQn 651 * Interrupt source 652 * 653 * \return 654 * Address of the ISR in the interrupt vector table 655 * 656 * \note CM0+:<br/> This function returns the interrupt vector for the interrupt 657 * channel on the NVIC. 658 * 659 * \note CM33:<br/>In case of CM33 with Security Extension enabled, if this function is called 660 * from secure world then, it returns the interrupt vector for the secure world. 661 * If it is called form non-secure world then it returns the interrupt vector 662 * for the non-secure world. 663 * 664 * \funcusage 665 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector 666 * 667 *******************************************************************************/ 668 cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn); 669 670 671 #if (((CY_CPU_CORTEX_M0P) || defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS)) 672 /******************************************************************************* 673 * Function Name: Cy_SysInt_SetInterruptSource 674 ****************************************************************************//** 675 * 676 * \brief Configures the interrupt selection for the specified NVIC channel. 677 * 678 * To disconnect the interrupt source from the NVIC channel 679 * use the \ref Cy_SysInt_DisconnectInterruptSource. 680 * 681 * \param IRQn 682 * NVIC channel number connected to the CPU core. 683 * 684 * \param devIntrSrc 685 * Device interrupt to be routed to the NVIC channel. 686 * 687 * \note This function is available for CM0+/CM7 core only. 688 * 689 * \funcusage 690 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 691 * 692 *******************************************************************************/ 693 void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc); 694 695 #if (defined (CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P)) || defined (CY_DOXYGEN) 696 /******************************************************************************* 697 * Function Name: Cy_SysInt_GetInterruptSource 698 ****************************************************************************//** 699 * 700 * \brief Gets the interrupt source of the NVIC channel. 701 * 702 * \param IRQn 703 * NVIC channel number connected to the CPU core 704 * 705 * \return 706 * Device interrupt connected to the NVIC channel. A returned value of 707 * "disconnected_IRQn" indicates that the interrupt source is disconnected. 708 * 709 * \note This function is available for CM0+ core only. 710 * 711 * \note This function supports only devices using CPUSS_ver1. For all 712 * other devices, use the Cy_SysInt_GetNvicConnection() function. 713 * 714 * \funcusage 715 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 716 * 717 *******************************************************************************/ 718 cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn); 719 #endif 720 721 /******************************************************************************* 722 * Function Name: Cy_SysInt_GetNvicConnection 723 ****************************************************************************//** 724 * 725 * \brief Gets the NVIC channel to which the interrupt source is connected. 726 * 727 * \param devIntrSrc 728 * Device interrupt that is potentially connected to the NVIC channel. 729 * 730 * \return 731 * NVIC channel number connected to the CPU core. A returned value of 732 * "unconnected_IRQn" indicates that the interrupt source is disabled. 733 * 734 * \note This function is available for CM0+/CM7 core only. 735 * 736 * \note This function supports only devices using CPUSS_ver2 or higher. 737 * 738 * \funcusage 739 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 740 * 741 *******************************************************************************/ 742 IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc); 743 744 745 /******************************************************************************* 746 * Function Name: Cy_SysInt_GetInterruptActive 747 ****************************************************************************//** 748 * 749 * \brief Gets the highest priority active interrupt for the selected NVIC channel. 750 * 751 * The priority of the interrupt in a given channel is determined by the index 752 * value of the interrupt in the cy_en_intr_t enum. The lower the index, the 753 * higher the priority. E.g. Consider a case where an interrupt source with value 754 * 29 and an interrupt source with value 46 both source the same NVIC channel. If 755 * both are active (triggered) at the same time, calling Cy_SysInt_GetInterruptActive() 756 * will return 29 as the active interrupt. 757 * 758 * \param IRQn 759 * NVIC channel number connected to the CPU core 760 * 761 * \return 762 * Device interrupt connected to the NVIC channel. A returned value of 763 * "disconnected_IRQn" indicates that there are no active (pending) interrupts 764 * on this NVIC channel. 765 * 766 * \note This function is available for CM0+/CM7 core only. 767 * 768 * \note This function supports only devices using CPUSS_ver2 or higher. 769 * 770 * \funcusage 771 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_GetInterruptActive 772 * 773 *******************************************************************************/ 774 cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn); 775 #endif 776 777 778 #if defined(CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 779 /******************************************************************************* 780 * Function Name: Cy_SysInt_DisconnectInterruptSource 781 ****************************************************************************//** 782 * 783 * \brief Disconnect the interrupt source from the specified NVIC channel. 784 * 785 * \param IRQn 786 * NVIC channel number connected to the CPU core. 787 * This parameter is ignored for devices using CPUSS_ver2. 788 * 789 * \param devIntrSrc 790 * Device interrupt routed to the NVIC channel. 791 * This parameter is ignored for devices using CPUSS_ver1. 792 * 793 * \note This function is available for CM0+ core only. 794 * 795 * \funcusage 796 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_DisconnectInterruptSource 797 * 798 *******************************************************************************/ 799 void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc); 800 #endif 801 802 #if defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2u) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN) 803 /******************************************************************************* 804 * Function Name: Cy_SysInt_InitExtIRQ 805 ****************************************************************************//** 806 * 807 * \brief Initializes the referenced external interrupt by setting the CPU IRQ priority and the 808 * interrupt vector. 809 * 810 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 811 * 812 * \param config 813 * Interrupt configuration structure 814 * 815 * \param userIsr 816 * Address of the ISR 817 * 818 * \note This function is available for CAT1C CM0/CM7 cores, and CAT1A TVIIBE CM0/CM4 cores. 819 * 820 * \return 821 * Initialization status 822 * 823 * \note CM0+/CM7 <br/> 824 * The interrupt vector will be relocated only if the vector table was 825 * moved to __ramVectors in SRAM. Otherwise it is ignored. 826 * 827 *******************************************************************************/ 828 cy_en_sysint_status_t Cy_SysInt_InitExtIRQ(const cy_stc_sysint_t* config, cy_israddress userIsr); 829 830 831 /******************************************************************************* 832 * Function Name: Cy_SysInt_InitIntIRQ 833 ****************************************************************************//** 834 * 835 * \brief Initializes the referenced internal interrupt by setting the priority and the 836 * interrupt vector. 837 * 838 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 839 * 840 * \param config 841 * Interrupt configuration structure 842 * 843 * \param userIsr 844 * Address of the ISR 845 * 846 * \note This function is available for CAT1C CM0/CM7 cores, and CAT1A TVIIBE CM0/CM4 cores. 847 * 848 * \return 849 * Initialization status 850 * 851 * \note CM0+/CM7 <br/> 852 * The interrupt vector will be relocated only if the vector table was 853 * moved to __ramVectors in SRAM. Otherwise it is ignored. 854 * 855 *******************************************************************************/ 856 cy_en_sysint_status_t Cy_SysInt_InitIntIRQ(const cy_stc_sysint_t* config, cy_israddress userIsr); 857 858 859 #if (defined (CPUSS_SYSTEM_IRQ_PRESENT) && (CPUSS_SYSTEM_IRQ_PRESENT == 1u)) || defined (CY_DOXYGEN) 860 /******************************************************************************* 861 * Function Name: Cy_SysInt_SetSystemIrqVector 862 ****************************************************************************//** 863 * 864 * \brief Sets the User ISR vector for the System Interrupt. 865 * 866 * \param sysIntSrc 867 * Interrupt source 868 * 869 * \note This function is available for CAT1C CM0/CM7 cores. 870 * 871 * \param userIsr 872 * Address of the ISR to set in the interrupt vector table 873 * 874 * \return none 875 * 876 *******************************************************************************/ 877 void Cy_SysInt_SetSystemIrqVector(cy_en_intr_t sysIntSrc, cy_israddress userIsr); 878 879 880 /******************************************************************************* 881 * Function Name: Cy_SysInt_GetSystemIrqVector 882 ****************************************************************************//** 883 * 884 * \brief Gets the address of the current user ISR vector for the System Interrupt. 885 * 886 * \param sysIntSrc 887 * Interrupt source 888 * 889 * \note This function is available for CAT1C CM0/CM7 cores. 890 * 891 * \return 892 * Address of the ISR in the interrupt vector table 893 * 894 *******************************************************************************/ 895 cy_israddress Cy_SysInt_GetSystemIrqVector(cy_en_intr_t sysIntSrc); 896 #endif /* (defined (CPUSS_SYSTEM_IRQ_PRESENT) && (CPUSS_SYSTEM_IRQ_PRESENT == 1u)) || defined (CY_DOXYGEN) */ 897 898 899 /******************************************************************************* 900 * Function Name: Cy_SysInt_EnableSystemInt 901 ****************************************************************************//** 902 * 903 * \brief Enable system interrupt. 904 * 905 * \param sysIntSrc 906 * System interrupt source to be enabled. 907 * 908 * \note This function is available for CAT1C CM0/CM7 cores, and CAT1A TVIIBE CM0/CM4 cores. 909 * 910 * \return none 911 * 912 *******************************************************************************/ 913 void Cy_SysInt_EnableSystemInt(cy_en_intr_t sysIntSrc); 914 915 916 /******************************************************************************* 917 * Function Name: Cy_SysInt_DisableSystemInt 918 ****************************************************************************//** 919 * 920 * \brief Disable system interrupt. 921 * 922 * \param sysIntSrc 923 * System interrupt source to be disabled. 924 * 925 * \note This function is available for CAT1C CM0/CM7 cores, and CAT1A TVIIBE CM0/CM4 cores. 926 * 927 * \return none 928 * 929 *******************************************************************************/ 930 void Cy_SysInt_DisableSystemInt(cy_en_intr_t sysIntSrc); 931 #endif 932 933 /*************************************** 934 * Functions 935 ***************************************/ 936 937 /******************************************************************************* 938 * Function Name: Cy_SysInt_SetNmiSource 939 ****************************************************************************//** 940 * 941 * \brief Sets the interrupt source of the CPU core NMI. 942 * 943 * The interrupt source must be a positive number. Setting the value to 944 * "unconnected_IRQn" or "disconnected_IRQn" disconnects the interrupt source 945 * from the NMI. Depending on the device, the number of interrupt sources that 946 * can provide the NMI trigger signal to the core can vary. 947 * 948 * \param nmiNum 949 * NMI source number. 950 * CPUSS_ver2 allows up to 4 sources to trigger the core NMI. 951 * CPUSS_ver1 allows only one source to trigger the core NMI and 952 * the specified NMI number is ignored. 953 * 954 * \param devIntrSrc 955 * Interrupt source. This parameter can either be of type cy_en_intr_t or IRQn_Type 956 * for CM0+/CM7 and CM4/CM33/CM55 respectively. 957 * 958 * \note CM0+ may call this function only at PC=0, CM4 may set its NMI handler at any PC. 959 * \note The CM0+ NMI is used for performing system calls that execute out of ROM. 960 * 961 * \funcusage 962 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource 963 * 964 *******************************************************************************/ 965 966 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.3', 2, 'Only one prototype will be picked for compilation') 967 #if (((CY_CPU_CORTEX_M0P) || defined (CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS)) 968 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t devIntrSrc); 969 #else 970 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc); 971 #endif 972 973 /******************************************************************************* 974 * Function Name: Cy_SysInt_GetIntSourceNMI 975 ****************************************************************************//** 976 * 977 * \brief Gets the interrupt source of the CPU core NMI for the given NMI source 978 * number. 979 * 980 * \param nmiNum 981 * NMI source number. 982 * CPUSS_ver2 allows up to 4 sources to trigger the core NMI (i.e. #1, 2, 3, 4). 983 * CPUSS_ver1 allows only 1 source to trigger the core NMI (i.e #1). 984 * 985 * \return 986 * Interrupt Source. This parameter can either be of type cy_en_intr_t or IRQn_Type 987 * for CM0+/CM7 and CM4/CM33/CM55 respectively. 988 * 989 * \funcusage 990 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource 991 * 992 *******************************************************************************/ 993 #if (((CY_CPU_CORTEX_M0P) || defined(CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS)) 994 cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum); 995 #else 996 IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum); 997 #endif 998 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.3') 999 1000 #if !(defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P)) && !(defined(CY_IP_M7CPUSS)) 1001 /******************************************************************************* 1002 * Function Name: Cy_SysInt_SoftwareTrig 1003 ****************************************************************************//** 1004 * 1005 * \brief Triggers an interrupt using software (Not applicable for CM0+). 1006 * 1007 * \param IRQn 1008 * Interrupt source 1009 * 1010 * \funcusage 1011 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SoftwareTrig 1012 * 1013 * \note Only privileged software can enable unprivileged access to the 1014 * Software Trigger Interrupt Register (STIR). This function is available for CAT1A, CAT1B and CAT1D devices. 1015 * 1016 * 1017 *******************************************************************************/ 1018 void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn); 1019 #endif 1020 1021 1022 /** \} group_sysint_functions */ 1023 1024 /** \cond INTERNAL */ 1025 1026 /*************************************** 1027 * Deprecated functions 1028 ***************************************/ 1029 1030 /******************************************************************************* 1031 * Function Name: Cy_SysInt_GetState 1032 ****************************************************************************//** 1033 * 1034 * This function is deprecated. It invokes the NVIC_GetEnableIRQ() function. 1035 * 1036 *******************************************************************************/ 1037 #define Cy_SysInt_GetState NVIC_GetEnableIRQ 1038 1039 1040 /******************************************************************************* 1041 * Function Name: Cy_SysInt_SetIntSource 1042 ****************************************************************************//** 1043 * 1044 * This function is deprecated. It invokes the Cy_SysInt_SetInterruptSource() function. 1045 * 1046 *******************************************************************************/ 1047 #define Cy_SysInt_SetIntSource(intrSrc, devIntrSrc) Cy_SysInt_SetInterruptSource(intrSrc, devIntrSrc) 1048 1049 1050 /******************************************************************************* 1051 * Function Name: Cy_SysInt_GetIntSource 1052 ****************************************************************************//** 1053 * 1054 * This function is deprecated. It invokes the Cy_SysInt_GetInterruptSource() function. 1055 * 1056 *******************************************************************************/ 1057 #define Cy_SysInt_GetIntSource(intrSrc) Cy_SysInt_GetInterruptSource(intrSrc) 1058 1059 1060 /******************************************************************************* 1061 * Function Name: Cy_SysInt_SetIntSourceNMI 1062 ****************************************************************************//** 1063 * 1064 * This function is deprecated. It invokes the Cy_SysInt_SetNmiSource() function. 1065 * 1066 *******************************************************************************/ 1067 #define Cy_SysInt_SetIntSourceNMI(srcParam) Cy_SysInt_SetNmiSource(CY_SYSINT_NMI1, srcParam) 1068 1069 1070 /******************************************************************************* 1071 * Function Name: Cy_SysInt_GetIntSourceNMI 1072 ****************************************************************************//** 1073 * 1074 * This function is deprecated. It invokes the Cy_SysInt_GetNmiSource() function. 1075 * 1076 *******************************************************************************/ 1077 #define Cy_SysInt_GetIntSourceNMI() Cy_SysInt_GetNmiSource(CY_SYSINT_NMI1) 1078 1079 /** \endcond */ 1080 1081 #if defined(__cplusplus) 1082 } 1083 #endif 1084 1085 #endif /* defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS) */ 1086 1087 #endif /* CY_SYSINT_H */ 1088 1089 /** \} group_sysint */ 1090 1091 /* [] END OF FILE */ 1092
