1 /***************************************************************************//**
2 * \file cy_scb_uart.h
3 * \version 3.20
4 *
5 * Provides UART API declarations of the SCB driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_scb_uart
27 * \{
28 * Driver API for UART
29 *
30 * The functions and other declarations used in this part of the driver are in
31 * cy_scb_uart.h. You can also include cy_pdl.h to get access
32 * to all functions and declarations in the PDL.
33 *
34 * The Universal Asynchronous Receiver/Transmitter (UART) protocol is an
35 * asynchronous serial interface protocol. UART communication is typically
36 * point-to-point. The UART interface consists of two signals:
37 * * TX: Transmitter output
38 * * RX: Receiver input
39 *
40 * Additionally, two side-band signals are used to implement flow control in
41 * UART. Note that the flow control applies only to TX functionality.
42 * * Clear to Send (CTS): This is an input signal to the transmitter.
43 * When active, it indicates that the slave is ready for the master to
44 * transmit data.
45 * * Ready to Send (RTS): This is an output signal from the receiver. When
46 * active, it indicates that the receiver is ready to receive data
47 *
48 * Features:
49 * * Supports UART protocol
50 * * Standard UART
51 * * Multi-processor mode
52 * * SmartCard (ISO7816) reader
53 * * IrDA
54 * * Data frame size programmable from 4 to 16 bits
55 * * Programmable number of STOP bits, which can be set in terms of half bit
56 * periods between 1 and 4
57 * * Parity support (odd and even parity)
58 * * Median filter on Rx input
59 * * Programmable oversampling
60 * * Start skipping
61 *
62 ********************************************************************************
63 * \section group_scb_uart_configuration Configuration Considerations
64 ********************************************************************************
65 * The UART driver configuration can be divided to number of sequential
66 * steps listed below:
67 * * \ref group_scb_uart_config
68 * * \ref group_scb_uart_pins
69 * * \ref group_scb_uart_clock
70 * * \ref group_scb_uart_data_rate
71 * * \ref group_scb_uart_intr
72 * * \ref group_scb_uart_enable
73 *
74 * \note
75 * UART driver is built on top of the SCB hardware block. The SCB5 instance is
76 * used as an example for all code snippets. Modify the code to match your
77 * design.
78 *
79 ********************************************************************************
80 * \subsection group_scb_uart_config Configure UART
81 ********************************************************************************
82 * To set up the UART driver, provide the configuration parameters in the
83 * \ref cy_stc_scb_uart_config_t structure. For example: provide uartMode,
84 * oversample, dataWidth, enableMsbFirst, parity, and stopBits. The other
85 * parameters are optional. To initialize the driver, call \ref Cy_SCB_UART_Init
86 * function providing a pointer to the populated \ref cy_stc_scb_uart_config_t
87 * structure and the allocated \ref cy_stc_scb_uart_context_t structure.
88 *
89 * \snippet scb/uart_snippet/main.c UART_CFG
90 *
91 ********************************************************************************
92 * \subsection group_scb_uart_pins Assign and Configure Pins
93 ********************************************************************************
94 * Only dedicated SCB pins can be used for UART operation. The HSIOM
95 * register must be configured to connect dedicated SCB UART pins to the
96 * SCB block. Also, the UART output pins must be configured in Strong Drive
97 * Input Off mode and UART input pins in Digital High-Z:
98 *
99 * \snippet scb/uart_snippet/main.c UART_CFG_PINS
100 *
101 ********************************************************************************
102 * \subsection group_scb_uart_clock Assign Clock Divider
103 ********************************************************************************
104 * A clock source must be connected to the SCB block to oversample input and
105 * output signals, in this document this clock will be referred as clk_scb.
106 * You must use one of available integer or fractional dividers. Use the
107 * \ref group_sysclk driver API to do this.
108 *
109 * \snippet scb/uart_snippet/main.c UART_CFG_ASSIGN_CLOCK
110 *
111 ********************************************************************************
112 * \subsection group_scb_uart_data_rate Configure Baud Rate
113 ********************************************************************************
114 * To get the UART to operate with the desired baud rate, the clk_scb frequency
115 * and the oversample must be configured. Use the \ref group_sysclk driver API
116 * to configure clk_scb frequency. Set the <em><b>oversample parameter
117 * in configuration structure</b></em> to define the number of the SCB clocks
118 * within one UART bit-time.
119 *
120 * \snippet scb/uart_snippet/main.c UART_CFG_DATA_RATE
121 *
122 * <b>Refer to the technical reference manual (TRM) section UART sub-section
123 * Clocking and Oversampling to get information about how to configure the UART to run with
124 * desired baud rate.</b>
125 *
126 ********************************************************************************
127 * \subsection group_scb_uart_intr Configure Interrupt
128 ********************************************************************************
129 * The interrupt is optional for the UART operation. To configure interrupt
130 * the \ref Cy_SCB_UART_Interrupt function must be called in the interrupt
131 * handler for the selected SCB instance. Also, this interrupt must be enabled
132 * in the NVIC.
133 * The interrupt must be configured when \ref group_scb_uart_hl will be used.
134 *
135 * \snippet scb/uart_snippet/main.c UART_INTR_A
136 * \snippet scb/uart_snippet/main.c UART_INTR_B
137 *
138 ********************************************************************************
139 * \subsection group_scb_uart_enable Enable UART
140 ********************************************************************************
141 * Finally, enable the UART operation by calling \ref Cy_SCB_UART_Enable.
142 *
143 * \snippet scb/uart_snippet/main.c UART_ENABLE
144 *
145 ********************************************************************************
146 * \section group_scb_uart_use_cases Common Use Cases
147 ********************************************************************************
148 * The UART API is divided into two categories: \ref group_scb_uart_low_level_functions
149 * and \ref group_scb_uart_high_level_functions. \n
150 * <em>Do not mix <b>High-Level</b> and <b>Low-Level</b> API because a Low-Level
151 * API can adversely affect the operation of a High-Level API.</em>
152 *
153 ********************************************************************************
154 * \subsection group_scb_uart_ll Low-Level API
155 ********************************************************************************
156 * The \ref group_scb_uart_low_level_functions functions allow
157 * interacting directly with the hardware and do not use \ref Cy_SCB_UART_Interrupt.
158 * These functions do not require context for operation. Thus, NULL can be
159 * passed for context parameter in \ref Cy_SCB_UART_Init and \ref Cy_SCB_UART_Disable
160 * instead of a pointer to the context structure.
161 *
162 * * To write data into the TX FIFO, use one of the provided functions:
163 * \ref Cy_SCB_UART_Put, \ref Cy_SCB_UART_PutArray,
164 * \ref Cy_SCB_UART_PutArrayBlocking or \ref Cy_SCB_UART_PutString.
165 * Note that putting data into the TX FIFO starts data transfer.
166 *
167 * * To read data from the RX FIFO, use one of the provided functions:
168 * \ref Cy_SCB_UART_Get, \ref Cy_SCB_UART_GetArray or
169 * \ref Cy_SCB_UART_GetArrayBlocking.
170 *
171 * * The statuses can be polled using: \ref Cy_SCB_UART_GetRxFifoStatus and
172 * \ref Cy_SCB_UART_GetTxFifoStatus.
173 * <em>The statuses are <b>W1C (Write 1 to Clear)</b> and after a status
174 * is set, it must be cleared.</em> Note that there are statuses evaluated as level.
175 * These statuses remain set until an event is true. Therefore, after the clear
176 * operation, the status is cleared but then it is restored (if event is still
177 * true).
178 * Also, the following functions can be used for polling as well
179 * \ref Cy_SCB_UART_IsTxComplete, \ref Cy_SCB_UART_GetNumInRxFifo and
180 * \ref Cy_SCB_UART_GetNumInTxFifo.
181 *
182 * \snippet scb/uart_snippet/main.c UART_TRANSMIT_DATA_LL
183 *
184 ********************************************************************************
185 * \subsection group_scb_uart_hl High-Level API
186 ********************************************************************************
187 * The \ref group_scb_uart_high_level_functions API use \ref Cy_SCB_UART_Interrupt
188 * to execute the transfer. Call \ref Cy_SCB_UART_Transmit to start transmission.
189 * Call \ref Cy_SCB_UART_Receive to start receive operation. After the
190 * operation is started the \ref Cy_SCB_UART_Interrupt handles the data
191 * transfer until its completion.
192 * Therefore \ref Cy_SCB_UART_Interrupt must be called inside the user
193 * interrupt handler to make the High-Level API work. To monitor status
194 * of transmit operation, use \ref Cy_SCB_UART_GetTransmitStatus and
195 * \ref Cy_SCB_UART_GetReceiveStatus to monitor receive status appropriately.
196 * Alternatively use \ref Cy_SCB_UART_RegisterCallback to register callback
197 * function to be notified about \ref group_scb_uart_macros_callback_events.
198 *
199 * <b>Receive Operation</b>
200 * \snippet scb/uart_snippet/main.c UART_RECEIVE_DATA_HL
201 *
202 * <b>Transmit Operation</b>
203 * \snippet scb/uart_snippet/main.c UART_TRANSMIT_DATA_HL
204 *
205 * There is also capability to insert a receive ring buffer that operates between
206 * the RX FIFO and the user buffer. The received data is copied into the ring
207 * buffer from the RX FIFO. This process runs in the background after the ring
208 * buffer operation is started by \ref Cy_SCB_UART_StartRingBuffer.
209 * When \ref Cy_SCB_UART_Receive is called, it first reads data from the ring
210 * buffer and then sets up an interrupt to receive more data if the required
211 * amount has not yet been read.
212 *
213 ********************************************************************************
214 * \section group_scb_uart_dma_trig DMA Trigger
215 ********************************************************************************
216 * The SCB provides TX and RX output trigger signals that can be routed to the
217 * DMA controller inputs. These signals are assigned based on the data availability
218 * in the TX and RX FIFOs appropriately.
219 *
220 * * The RX trigger signal is active while the number of data
221 * elements in the RX FIFO is greater than the value of RX FIFO level. Use
222 * function \ref Cy_SCB_SetRxFifoLevel or set configuration structure
223 * rxFifoTriggerLevel parameter to configure RX FIFO level value. \n
224 * <em>For example, the RX FIFO has 8 data elements and the RX FIFO level is 0.
225 * The RX trigger signal is active until DMA reads all data from
226 * the RX FIFO.</em>
227 *
228 * * The TX trigger signal is active while the number of data elements
229 * in the TX FIFO is less than the value of TX FIFO level. Use function
230 * \ref Cy_SCB_SetTxFifoLevel or set configuration structure txFifoTriggerLevel
231 * parameter to configure TX FIFO level value. \n
232 * <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
233 * is 7. The TX trigger signal is active until DMA loads TX FIFO
234 * with 8 data elements (note that after the first TX load operation, the data
235 * element goes to the shift register and TX FIFO is empty).</em>
236 *
237 * To route SCB TX or RX trigger signals to DMA controller use \ref group_trigmux
238 * driver API.
239 *
240 * \note
241 * To properly handle DMA level request signal activation and de-activation from the SCB
242 * peripheral block the DMA Descriptor typically must be configured to re-trigger
243 * after 16 Clk_Slow cycles.
244 *
245 ********************************************************************************
246 * \section group_scb_uart_lp Low Power Support
247 ********************************************************************************
248 * The UART driver provides callback functions to handle power mode
249 * transition. The callback \ref Cy_SCB_UART_DeepSleepCallback must be called
250 * during execution of \ref Cy_SysPm_CpuEnterDeepSleep \ref Cy_SCB_UART_HibernateCallback
251 * must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. To trigger the
252 * callback execution, the callback must be registered before calling the
253 * power mode transition function. Refer to \ref group_syspm driver for more
254 * information about power mode transitions and callback registration.
255 *
256 * The UART is disabled during Deep Sleep and Hibernate and stops driving
257 * the output pins. The state of the UART output pins TX and RTS is High-Z,
258 * which can cause unexpected behavior of the UART receiver due to possible
259 * glitches on these lines. These pins must be set to the inactive state before
260 * entering Deep Sleep or Hibernate mode.
261 * These pins must keep the inactive level (the same state
262 * when UART TX is enabled and does not transfer data) before entering Deep
263 * Sleep or Hibernate mode. To do that, write the GPIO data register of each pin
264 * to the inactive level for each output pin. Then configure High-Speed Input
265 * Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use
266 * \ref group_gpio driver API). After exiting Deep Sleep mode the UART
267 * must be enabled and the pins configuration restored to return the
268 * UART control of the pins (after exiting Hibernate mode, the
269 * system initialization code does the same). Copy either or
270 * both \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback
271 * as appropriate, and make the changes described above inside the function.
272 * Alternately, external pull-up or pull-down resistors can be connected
273 * to the appropriate UART lines to keep them inactive during Deep-Sleep or
274 * Hibernate.
275 *
276 * \defgroup group_scb_uart_macros Macros
277 * \defgroup group_scb_uart_functions Functions
278 * \{
279 * \defgroup group_scb_uart_general_functions General
280 * \defgroup group_scb_uart_high_level_functions High-Level
281 * \defgroup group_scb_uart_low_level_functions Low-Level
282 * \defgroup group_scb_uart_interrupt_functions Interrupt
283 * \defgroup group_scb_uart_low_power_functions Low Power Callbacks
284 * \}
285 * \defgroup group_scb_uart_data_structures Data Structures
286 * \defgroup group_scb_uart_enums Enumerated Types
287 */
288
289 #if !defined(CY_SCB_UART_H)
290 #define CY_SCB_UART_H
291
292 #include "cy_device.h"
293
294 #if (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB))
295
296 #include "cy_scb_common.h"
297
298 #if defined(__cplusplus)
299 extern "C" {
300 #endif
301
302 /***************************************
303 * Enumerated Types
304 ***************************************/
305
306 /**
307 * \addtogroup group_scb_uart_enums
308 * \{
309 */
310
311 /** UART status codes */
312 typedef enum
313 {
314 /** Operation completed successfully */
315 CY_SCB_UART_SUCCESS = 0U,
316
317 /** One or more of input parameters are invalid */
318 CY_SCB_UART_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 1U),
319
320 /**
321 * The UART is busy processing a receive operation.
322 */
323 CY_SCB_UART_RECEIVE_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 2U),
324
325 /**
326 * The UART is busy processing a transmit operation.
327 */
328 CY_SCB_UART_TRANSMIT_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 3U)
329 } cy_en_scb_uart_status_t;
330
331 /** UART Mode */
332 typedef enum
333 {
334 CY_SCB_UART_STANDARD = 0U, /**< Configures the SCB for Standard UART operation */
335 CY_SCB_UART_SMARTCARD = 1U, /**< Configures the SCB for SmartCard operation */
336 CY_SCB_UART_IRDA = 2U, /**< Configures the SCB for IrDA operation */
337 } cy_en_scb_uart_mode_t;
338
339 /** UART Stop Bits */
340 typedef enum
341 {
342 CY_SCB_UART_STOP_BITS_1 = 2U, /**< UART looks for 1 Stop Bit */
343 CY_SCB_UART_STOP_BITS_1_5 = 3U, /**< UART looks for 1.5 Stop Bits */
344 CY_SCB_UART_STOP_BITS_2 = 4U, /**< UART looks for 2 Stop Bits */
345 CY_SCB_UART_STOP_BITS_2_5 = 5U, /**< UART looks for 2.5 Stop Bits */
346 CY_SCB_UART_STOP_BITS_3 = 6U, /**< UART looks for 3 Stop Bits */
347 CY_SCB_UART_STOP_BITS_3_5 = 7U, /**< UART looks for 3.5 Stop Bits */
348 CY_SCB_UART_STOP_BITS_4 = 8U, /**< UART looks for 4 Stop Bits */
349 } cy_en_scb_uart_stop_bits_t;
350
351 /** UART Parity */
352 typedef enum
353 {
354 CY_SCB_UART_PARITY_NONE = 0U, /**< UART has no parity check */
355 CY_SCB_UART_PARITY_EVEN = 2U, /**< UART has even parity check */
356 CY_SCB_UART_PARITY_ODD = 3U, /**< UART has odd parity check */
357 } cy_en_scb_uart_parity_t;
358
359 /** UART Polarity */
360 typedef enum
361 {
362 CY_SCB_UART_ACTIVE_LOW = 0U, /**< Signal is active low */
363 CY_SCB_UART_ACTIVE_HIGH = 1U, /**< Signal is active high */
364 } cy_en_scb_uart_polarity_t;
365 /** \} group_scb_uart_enums */
366
367
368 /*******************************************************************************
369 * Type Definitions
370 *******************************************************************************/
371
372 /**
373 * \addtogroup group_scb_uart_data_structures
374 * \{
375 */
376
377 /**
378 * Provides the typedef for the callback function called in the
379 * \ref Cy_SCB_UART_Interrupt to notify the user about occurrences of
380 * \ref group_scb_uart_macros_callback_events.
381 */
382 typedef void (* cy_cb_scb_uart_handle_events_t)(uint32_t event);
383
384 /** UART configuration structure */
385 typedef struct stc_scb_uart_config
386 {
387 /** Specifies the UART's mode of operation */
388 cy_en_scb_uart_mode_t uartMode;
389
390 #if ((defined(CY_IP_MXSCB_VERSION)) && (CY_IP_MXSCB_VERSION >= 4))
391 /** Single Wire Half-Duplex Mode */
392 bool halfDuplexMode;
393 #endif
394
395 /**
396 * Oversample factor for UART.
397 * * The UART baud rate is the SCB Clock frequency / oversample
398 * (valid range is 8-16).
399 * * For IrDA, the oversample is always 16, unless
400 * \ref irdaEnableLowPowerReceiver is enabled. Then the oversample is
401 * reduced to the \ref group_scb_uart_macros_irda_lp_ovs set.
402 */
403 uint32_t oversample;
404
405 /** The width of UART data (valid range is 5 to 9) */
406 uint32_t dataWidth;
407
408 /**
409 * Enables the hardware to shift out data element MSB first; otherwise,
410 * LSB first
411 */
412 bool enableMsbFirst;
413
414 /**
415 * Specifies the number of stop bits in the UART transaction, in half-bit
416 * increments
417 */
418 cy_en_scb_uart_stop_bits_t stopBits;
419
420 /** Configures the UART parity */
421 cy_en_scb_uart_parity_t parity;
422
423 /**
424 * Enables a digital 3-tap median filter (2 out of 3 voting) to be applied
425 * to the input of the RX FIFO to filter glitches on the line (for IrDA,
426 * this parameter is ignored)
427 *
428 */
429 bool enableInputFilter;
430
431 /**
432 * Enables the hardware to drop data in the RX FIFO when a parity error is
433 * detected
434 */
435 bool dropOnParityError;
436
437 /**
438 * Enables the hardware to drop data in the RX FIFO when a frame error is
439 * detected
440 */
441 bool dropOnFrameError;
442
443 /**
444 * Enables the UART operation in Multi-Processor mode which requires
445 * dataWidth to be 9 bits (the 9th bit is used to indicate address byte)
446 */
447 bool enableMutliProcessorMode;
448
449 /**
450 * If Multi Processor mode is enabled, this is the address of the RX
451 * FIFO. If the address matches, data is accepted into the FIFO. If
452 * it does not match, the data is ignored.
453 */
454 uint32_t receiverAddress;
455
456 /**
457 * This is the address mask for the Multi Processor address. 1 indicates
458 * that the incoming address must match the corresponding bit in the slave
459 * address. A 0 in the mask indicates that the incoming address does
460 * not need to match.
461 */
462 uint32_t receiverAddressMask;
463
464 /**
465 * Enables the hardware to accept the matching address in the RX FIFO.
466 * This is useful when the device supports more than one address.
467 */
468 bool acceptAddrInFifo;
469
470 /** Inverts the IrDA RX input */
471 bool irdaInvertRx;
472
473 /**
474 * Enables the low-power receive for IrDA mode.
475 * Note that the transmission must be disabled if this mode is enabled.
476 */
477 bool irdaEnableLowPowerReceiver;
478
479 /**
480 * Enables retransmission of the frame placed in the TX FIFO when
481 * NACK is received in SmartCard mode (for Standard and IrDA , this parameter
482 * is ignored)
483 */
484 bool smartCardRetryOnNack;
485
486 /**
487 * Enables the usage of the CTS input signal for the transmitter. The
488 * transmitter waits for CTS to be active before sending data
489 */
490 bool enableCts;
491
492 /** Sets the CTS Polarity */
493 cy_en_scb_uart_polarity_t ctsPolarity;
494
495 /**
496 * When the RX FIFO has fewer entries than rtsRxFifoLevel, the
497 * RTS signal is active (note to disable RTS, set this field to zero)
498 */
499 uint32_t rtsRxFifoLevel;
500
501 /** Sets the RTS Polarity */
502 cy_en_scb_uart_polarity_t rtsPolarity;
503
504 /** Specifies the number of bits to detect a break condition */
505 uint32_t breakWidth;
506 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
507 /** Specifies the low or high level pulse detection for break condition */
508 /**
509 * \note
510 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
511 **/
512 bool breaklevel;
513 #endif /* (((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN)) */
514 /**
515 * When there are more entries in the RX FIFO than this level
516 * the RX trigger output goes high. This output can be connected
517 * to a DMA channel through a trigger mux.
518 * Also, it controls the \ref CY_SCB_UART_RX_TRIGGER interrupt source.
519 */
520 uint32_t rxFifoTriggerLevel;
521
522 /**
523 * The bits set in this mask allow the event to cause an interrupt
524 * (See \ref group_scb_uart_macros_rx_fifo_status for the set of constants)
525 */
526 uint32_t rxFifoIntEnableMask;
527
528 /**
529 * When there are fewer entries in the TX FIFO then this level
530 * the TX trigger output goes high. This output can be connected
531 * to a DMA channel through a trigger mux.
532 * Also, it controls \ref CY_SCB_UART_TX_TRIGGER interrupt source.
533 */
534 uint32_t txFifoTriggerLevel;
535
536 /**
537 * Bits set in this mask allows the event to cause an interrupt
538 * (See \ref group_scb_uart_macros_tx_fifo_status for the set of constants)
539 */
540 uint32_t txFifoIntEnableMask;
541 } cy_stc_scb_uart_config_t;
542
543 /** UART context structure.
544 * All fields for the context structure are internal. Firmware never reads or
545 * writes these values. Firmware allocates the structure and provides the
546 * address of the structure to the driver in function calls. Firmware must
547 * ensure that the defined instance of this structure remains in scope
548 * while the drive is in use.
549 */
550 typedef struct cy_stc_scb_uart_context
551 {
552 /** \cond INTERNAL */
553 uint32_t volatile txStatus; /**< The transmit status */
554 uint32_t volatile rxStatus; /**< The receive status */
555
556 void *rxRingBuf; /**< The pointer to the ring buffer */
557 uint32_t rxRingBufSize; /**< The ring buffer size */
558 uint32_t volatile rxRingBufHead; /**< The ring buffer head index */
559 uint32_t volatile rxRingBufTail; /**< The ring buffer tail index */
560
561 void *rxBuf; /**< The pointer to the receive buffer */
562 uint32_t rxBufSize; /**< The receive buffer size */
563 uint32_t volatile rxBufIdx; /**< The current location in the receive buffer */
564
565 void *txBuf; /**< The pointer to the transmit buffer */
566 uint32_t txBufSize; /**< The transmit buffer size */
567 uint32_t volatile txLeftToTransmit; /**< The number of data elements left to be transmitted */
568
569 /**
570 * Enables the low-power receive for IrDA mode.
571 * Note that the transmission must be disabled if this mode is enabled.
572 */
573 bool irdaEnableLowPowerReceiver;
574
575 /** The pointer to an event callback that is called when any of
576 * \ref group_scb_uart_macros_callback_events occurs
577 */
578 cy_cb_scb_uart_handle_events_t cbEvents;
579
580 #if !defined(NDEBUG)
581 uint32_t initKey; /**< Tracks the context initialization */
582 #endif /* !(NDEBUG) */
583 /** \endcond */
584 } cy_stc_scb_uart_context_t;
585 /** \} group_scb_uart_data_structures */
586
587
588 /*******************************************************************************
589 * Function Prototypes
590 *******************************************************************************/
591
592 /**
593 * \addtogroup group_scb_uart_general_functions
594 * \{
595 */
596 cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config,
597 cy_stc_scb_uart_context_t *context);
598 void Cy_SCB_UART_DeInit (CySCB_Type *base);
599 __STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base);
600 void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
601
602 __STATIC_INLINE void Cy_SCB_UART_EnableCts (CySCB_Type *base);
603 __STATIC_INLINE void Cy_SCB_UART_DisableCts (CySCB_Type *base);
604 __STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level);
605 __STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base);
606
607 __STATIC_INLINE void Cy_SCB_UART_EnableSkipStart (CySCB_Type *base);
608 __STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base);
609 #if ((defined(CY_IP_MXSCB_VERSION)) && (CY_IP_MXSCB_VERSION >= 4))
610 __STATIC_INLINE void Cy_SCB_UART_EnableSingleWireHalfDuplex(CySCB_Type *base);
611 __STATIC_INLINE void Cy_SCB_UART_DisableSingleWireHalfDuplex(CySCB_Type *base);
612 #endif/* ((defined(CY_IP_MXSCB_VERSION)) && (CY_IP_MXSCB_VERSION >= 4)) */
613 /** \} group_scb_uart_general_functions */
614
615 /**
616 * \addtogroup group_scb_uart_high_level_functions
617 * \{
618 */
619 void Cy_SCB_UART_StartRingBuffer (CySCB_Type *base, void *buffer, uint32_t size,
620 cy_stc_scb_uart_context_t *context);
621 void Cy_SCB_UART_StopRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
622 uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
623 void Cy_SCB_UART_ClearRingBuffer (CySCB_Type const *base, cy_stc_scb_uart_context_t *context);
624
625 cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint32_t size,
626 cy_stc_scb_uart_context_t *context);
627 void Cy_SCB_UART_AbortReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
628 uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
629 uint32_t Cy_SCB_UART_GetNumReceived (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
630
631 cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *buffer, uint32_t size,
632 cy_stc_scb_uart_context_t *context);
633 void Cy_SCB_UART_AbortTransmit (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
634 uint32_t Cy_SCB_UART_GetTransmitStatus (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
635 uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
636 /** \} group_scb_uart_high_level_functions */
637
638 /**
639 * \addtogroup group_scb_uart_low_level_functions
640 * \{
641 */
642 __STATIC_INLINE uint32_t Cy_SCB_UART_Put (CySCB_Type *base, uint32_t data);
643 __STATIC_INLINE uint32_t Cy_SCB_UART_PutArray (CySCB_Type *base, void *buffer, uint32_t size);
644 __STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
645 __STATIC_INLINE void Cy_SCB_UART_PutString (CySCB_Type *base, char_t const string[]);
646 void Cy_SCB_UART_SendBreakBlocking(CySCB_Type *base, uint32_t breakWidth);
647
648 __STATIC_INLINE uint32_t Cy_SCB_UART_Get (CySCB_Type const *base);
649 __STATIC_INLINE uint32_t Cy_SCB_UART_GetArray (CySCB_Type const *base, void *buffer, uint32_t size);
650 __STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size);
651
652 __STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus (CySCB_Type const *base);
653 __STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask);
654
655 __STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus (CySCB_Type const *base);
656 __STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask);
657
658 __STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo (CySCB_Type const *base);
659 __STATIC_INLINE bool Cy_SCB_UART_IsTxComplete (CySCB_Type const *base);
660
661 __STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo (CySCB_Type const *base);
662
663 __STATIC_INLINE void Cy_SCB_UART_ClearRxFifo (CySCB_Type *base);
664 __STATIC_INLINE void Cy_SCB_UART_ClearTxFifo (CySCB_Type *base);
665
666 __STATIC_INLINE uint32_t Cy_SCB_UART_GetOverSample(CySCB_Type const *base);
667 cy_en_scb_uart_status_t Cy_SCB_UART_SetOverSample(CySCB_Type *base, uint32_t overSample, cy_stc_scb_uart_context_t *context);
668
669 __STATIC_INLINE uint32_t Cy_SCB_UART_GetDataWidth(CySCB_Type const *base);
670 void Cy_SCB_UART_SetDataWidth(CySCB_Type *base, uint32_t dataWidth);
671
672 __STATIC_INLINE uint32_t Cy_SCB_UART_GetParity(CySCB_Type const *base);
673 void Cy_SCB_UART_SetParity(CySCB_Type *base, cy_en_scb_uart_parity_t parity);
674
675 __STATIC_INLINE uint32_t Cy_SCB_UART_GetStopBits(CySCB_Type const *base);
676 void Cy_SCB_UART_SetStopBits(CySCB_Type *base, cy_en_scb_uart_stop_bits_t stopBits);
677
678 __STATIC_INLINE bool Cy_SCB_UART_GetDropOnParityError(CySCB_Type const *base);
679 void Cy_SCB_UART_SetDropOnParityError(CySCB_Type *base, bool dropOnParityError);
680
681 __STATIC_INLINE bool Cy_SCB_UART_GetEnableMsbFirst(CySCB_Type const *base);
682 void Cy_SCB_UART_SetEnableMsbFirst(CySCB_Type *base, bool enableMsbFirst);
683 /** \} group_scb_uart_low_level_functions */
684
685 /**
686 * \addtogroup group_scb_uart_interrupt_functions
687 * \{
688 */
689 void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
690
691 __STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base, cy_cb_scb_uart_handle_events_t callback,
692 cy_stc_scb_uart_context_t *context);
693 /** \} group_scb_uart_interrupt_functions */
694
695 /**
696 * \addtogroup group_scb_uart_low_power_functions
697 * \{
698 */
699 cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
700 cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
701 /** \} group_scb_uart_low_power_functions */
702
703
704 /*******************************************************************************
705 * API Constants
706 *******************************************************************************/
707
708 /**
709 * \addtogroup group_scb_uart_macros
710 * \{
711 */
712
713 /**
714 * \defgroup group_scb_uart_macros_irda_lp_ovs UART IRDA Low Power Oversample factors
715 * \{
716 */
717 #define CY_SCB_UART_IRDA_LP_OVS16 (1UL) /**< IrDA in low-power mode oversampled by 16 */
718 #define CY_SCB_UART_IRDA_LP_OVS32 (2UL) /**< IrDA in low-power mode oversampled by 32 */
719 #define CY_SCB_UART_IRDA_LP_OVS48 (3UL) /**< IrDA in low-power mode oversampled by 48 */
720 #define CY_SCB_UART_IRDA_LP_OVS96 (4UL) /**< IrDA in low-power mode oversampled by 96 */
721 #define CY_SCB_UART_IRDA_LP_OVS192 (5UL) /**< IrDA in low-power mode oversampled by 192 */
722 #define CY_SCB_UART_IRDA_LP_OVS768 (6UL) /**< IrDA in low-power mode oversampled by 768 */
723 #define CY_SCB_UART_IRDA_LP_OVS1536 (7UL) /**< IrDA in low-power mode oversampled by 1536 */
724 /** \} group_scb_uart_macros_irda_lp_ovs */
725
726 /**
727 * \defgroup group_scb_uart_macros_rx_fifo_status UART RX FIFO status.
728 * \{
729 * Macros to check UART RX FIFO status returned by \ref Cy_SCB_UART_GetRxFifoStatus
730 * function or assign mask for \ref Cy_SCB_UART_ClearRxFifoStatus function.
731 * Each UART RX FIFO status is encoded in a separate bit, therefore multiple
732 * bits may be set to indicate the current status.
733 */
734
735 /** The number of entries in the RX FIFO is more than the RX FIFO trigger level
736 * value
737 */
738 #define CY_SCB_UART_RX_TRIGGER (SCB_INTR_RX_TRIGGER_Msk)
739
740 /** The RX FIFO is not empty, there is data to read */
741 #define CY_SCB_UART_RX_NOT_EMPTY (SCB_INTR_RX_NOT_EMPTY_Msk)
742
743 /**
744 * The RX FIFO is full, there is no more space for additional data, and
745 * any additional data will be dropped
746 */
747 #define CY_SCB_UART_RX_FULL (SCB_INTR_RX_FULL_Msk)
748
749 /**
750 * The RX FIFO was full and there was an attempt to write to it.
751 * That additional data was dropped.
752 */
753 #define CY_SCB_UART_RX_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
754
755 /** An attempt to read from an empty RX FIFO */
756 #define CY_SCB_UART_RX_UNDERFLOW (SCB_INTR_RX_UNDERFLOW_Msk)
757
758 /** The RX FIFO detected a frame error, either a stop or stop-bit error */
759 #define CY_SCB_UART_RX_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk)
760
761 /** The RX FIFO detected a parity error */
762 #define CY_SCB_UART_RX_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk)
763
764 /** The RX FIFO detected a break transmission from the transmitter */
765 #define CY_SCB_UART_RX_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk)
766 /** \} group_scb_uart_macros_rx_fifo_status */
767
768 /**
769 * \defgroup group_scb_uart_macros_tx_fifo_status UART TX FIFO Statuses
770 * \{
771 * Macros to check UART TX FIFO status returned by \ref Cy_SCB_UART_GetTxFifoStatus
772 * function or assign mask for \ref Cy_SCB_UART_ClearTxFifoStatus function.
773 * Each UART TX FIFO status is encoded in a separate bit, therefore multiple bits
774 * may be set to indicate the current status.
775 */
776
777 /** The number of entries in the TX FIFO is less than the TX FIFO trigger level
778 * value
779 */
780 #define CY_SCB_UART_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk)
781
782 /** The TX FIFO is not full, there is a space for more data */
783 #define CY_SCB_UART_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk)
784
785 /** The TX FIFO is empty, note there may still be data in the shift register.*/
786 #define CY_SCB_UART_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk)
787
788 /** An attempt to write to the full TX FIFO */
789 #define CY_SCB_UART_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk)
790
791 /** An attempt to read from an empty transmitter FIFO (hardware reads). */
792 #define CY_SCB_UART_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)
793
794 /** All data has been transmitted out of the FIFO, including shifter */
795 #define CY_SCB_UART_TX_DONE (SCB_INTR_TX_UART_DONE_Msk)
796
797 /** SmartCard only: the transmitter received a NACK */
798 #define CY_SCB_UART_TX_NACK (SCB_INTR_TX_UART_NACK_Msk)
799
800 /** SmartCard only: the transmitter lost arbitration */
801 #define CY_SCB_UART_TX_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk)
802 /** \} group_scb_uart_macros_tx_fifo_status */
803
804 /**
805 * \defgroup group_scb_uart_macros_receive_status UART Receive Statuses
806 * \{
807 * Macros to check current UART receive status returned by
808 * \ref Cy_SCB_UART_GetReceiveStatus function.
809 * Each UART receive status is encoded in a separate bit, therefore multiple bits
810 * may be set to indicate the current status.
811 */
812 /** The receive operation started by \ref Cy_SCB_UART_Receive is in progress */
813 #define CY_SCB_UART_RECEIVE_ACTIVE (0x01UL)
814
815 /**
816 * The hardware RX FIFO was full and there was an attempt to write to it.
817 * That additional data was dropped.
818 */
819 #define CY_SCB_UART_RECEIVE_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
820
821 /** The receive hardware detected a frame error, either a start or
822 * stop bit error
823 */
824 #define CY_SCB_UART_RECEIVE_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk)
825
826 /** The receive hardware detected a parity error */
827 #define CY_SCB_UART_RECEIVE_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk)
828
829 /** The receive hardware detected a break transmission from transmitter */
830 #define CY_SCB_UART_RECEIVE_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk)
831 /** \} group_scb_uart_macros_receive_status */
832
833 /**
834 * \defgroup group_scb_uart_macros_transmit_status UART Transmit Status
835 * \{
836 * Macros to check current UART transmit status returned by
837 * \ref Cy_SCB_UART_GetTransmitStatus function.
838 * Each UART transmit status is encoded in a separate bit, therefore multiple bits
839 * may be set to indicate the current status.
840 */
841
842 /** The transmit operation started by \ref Cy_SCB_UART_Transmit is in progress */
843 #define CY_SCB_UART_TRANSMIT_ACTIVE (0x01UL)
844
845 /**
846 * All data elements specified by \ref Cy_SCB_UART_Transmit have been loaded
847 * into the TX FIFO
848 */
849 #define CY_SCB_UART_TRANSMIT_IN_FIFO (0x02UL)
850
851 /** SmartCard only: the transmitter received a NACK */
852 #define CY_SCB_UART_TRANSMIT_NACK (SCB_INTR_TX_UART_NACK_Msk)
853
854 /** SmartCard only: the transmitter lost arbitration */
855 #define CY_SCB_UART_TRANSMIT_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk)
856 /** \} group_scb_uart_macros_transmit_status */
857
858 /**
859 * \defgroup group_scb_uart_macros_callback_events UART Callback Events
860 * \{
861 * Macros to check UART events passed by \ref cy_cb_scb_uart_handle_events_t callback.
862 * Note that only single event is notified by the callback when it is called.
863 */
864
865 /**
866 * All data elements specified by \ref Cy_SCB_UART_Transmit have been loaded
867 * into the TX FIFO
868 */
869 #define CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT (0x01UL)
870
871 /** The transmit operation started by \ref Cy_SCB_UART_Transmit is complete */
872 #define CY_SCB_UART_TRANSMIT_DONE_EVENT (0x02UL)
873
874 /** The receive operation started by \ref Cy_SCB_UART_Receive is complete */
875 #define CY_SCB_UART_RECEIVE_DONE_EVENT (0x04UL)
876
877 /**
878 * The ring buffer is full, there is no more space for additional data.
879 * Additional data is stored in the RX FIFO until it becomes full, at which
880 * point data is dropped.
881 */
882 #define CY_SCB_UART_RB_FULL_EVENT (0x08UL)
883
884 /**
885 * An error was detected during the receive operation. This includes overflow,
886 * frame error, or parity error. Check \ref Cy_SCB_UART_GetReceiveStatus to
887 * determine the source of the error.
888 */
889 #define CY_SCB_UART_RECEIVE_ERR_EVENT (0x10UL)
890
891 /**
892 * An error was detected during the transmit operation. This includes a NACK
893 * or lost arbitration. Check \ref Cy_SCB_UART_GetTransmitStatus to determine
894 * the source of the error
895 */
896 #define CY_SCB_UART_TRANSMIT_ERR_EVENT (0x20UL)
897
898 /** The receive fifo is not empty. To use this event the \ref CY_SCB_RX_INTR_NOT_EMPTY interrupt must be enabled by the user. */
899 #define CY_SCB_UART_RECEIVE_NOT_EMTPY (0x40UL)
900
901 /** The transmit fifo is empty. To use this event the \ref CY_SCB_UART_TX_EMPTY interrupt must be enabled by the user. */
902 #define CY_SCB_UART_TRANSMIT_EMTPY (0x80UL)
903 /** \} group_scb_uart_macros_callback_events */
904
905
906 /** Data returned by the hardware when an empty RX FIFO is read */
907 #define CY_SCB_UART_RX_NO_DATA (0xFFFFFFFFUL)
908
909
910 /*******************************************************************************
911 * Internal Constants
912 *******************************************************************************/
913
914 /** \cond INTERNAL */
915 #define CY_SCB_UART_TX_INTR_MASK (CY_SCB_UART_TX_TRIGGER | CY_SCB_UART_TX_NOT_FULL | CY_SCB_UART_TX_EMPTY | \
916 CY_SCB_UART_TX_OVERFLOW | CY_SCB_UART_TX_UNDERFLOW | CY_SCB_UART_TX_DONE | \
917 CY_SCB_UART_TX_NACK | CY_SCB_UART_TX_ARB_LOST)
918
919 #define CY_SCB_UART_RX_INTR_MASK (CY_SCB_UART_RX_TRIGGER | CY_SCB_UART_RX_NOT_EMPTY | CY_SCB_UART_RX_FULL | \
920 CY_SCB_UART_RX_OVERFLOW | CY_SCB_UART_RX_UNDERFLOW | CY_SCB_UART_RX_ERR_FRAME | \
921 CY_SCB_UART_RX_ERR_PARITY | CY_SCB_UART_RX_BREAK_DETECT)
922
923 #define CY_SCB_UART_TX_INTR (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
924
925 #define CY_SCB_UART_RX_INTR (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \
926 CY_SCB_RX_INTR_UART_PARITY_ERROR | CY_SCB_RX_INTR_UART_BREAK_DETECT)
927
928 #define CY_SCB_UART_RECEIVE_ERR (CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \
929 CY_SCB_RX_INTR_UART_PARITY_ERROR)
930
931 #define CY_SCB_UART_TRANSMIT_ERR (CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
932
933 #define CY_SCB_UART_INIT_KEY (0x00ABCDEFUL)
934
935 #define CY_SCB_UART_IS_MODE_VALID(mode) ( (CY_SCB_UART_STANDARD == (mode)) || \
936 (CY_SCB_UART_SMARTCARD == (mode)) || \
937 (CY_SCB_UART_IRDA == (mode)) )
938
939 #define CY_SCB_UART_IS_STOP_BITS_VALID(stopBits) ( (CY_SCB_UART_STOP_BITS_1 == (stopBits)) || \
940 (CY_SCB_UART_STOP_BITS_1_5 == (stopBits)) || \
941 (CY_SCB_UART_STOP_BITS_2 == (stopBits)) || \
942 (CY_SCB_UART_STOP_BITS_2_5 == (stopBits)) || \
943 (CY_SCB_UART_STOP_BITS_3 == (stopBits)) || \
944 (CY_SCB_UART_STOP_BITS_3_5 == (stopBits)) || \
945 (CY_SCB_UART_STOP_BITS_4 == (stopBits)) )
946
947 #define CY_SCB_UART_IS_PARITY_VALID(parity) ( (CY_SCB_UART_PARITY_NONE == (parity)) || \
948 (CY_SCB_UART_PARITY_EVEN == (parity)) || \
949 (CY_SCB_UART_PARITY_ODD == (parity)) )
950
951 #define CY_SCB_UART_IS_POLARITY_VALID(polarity) ( (CY_SCB_UART_ACTIVE_LOW == (polarity)) || \
952 (CY_SCB_UART_ACTIVE_HIGH == (polarity)) )
953
954 #define CY_SCB_UART_IS_IRDA_LP_OVS_VALID(ovs) ( (CY_SCB_UART_IRDA_LP_OVS16 == (ovs)) || \
955 (CY_SCB_UART_IRDA_LP_OVS32 == (ovs)) || \
956 (CY_SCB_UART_IRDA_LP_OVS48 == (ovs)) || \
957 (CY_SCB_UART_IRDA_LP_OVS96 == (ovs)) || \
958 (CY_SCB_UART_IRDA_LP_OVS192 == (ovs)) || \
959 (CY_SCB_UART_IRDA_LP_OVS768 == (ovs)) || \
960 (CY_SCB_UART_IRDA_LP_OVS1536 == (ovs)) )
961
962 #define CY_SCB_UART_IS_ADDRESS_VALID(addr) ((addr) <= 0xFFUL)
963 #define CY_SCB_UART_IS_ADDRESS_MASK_VALID(mask) ((mask) <= 0xFFUL)
964 #define CY_SCB_UART_IS_DATA_WIDTH_VALID(width) ( ((width) >= 5UL) && ((width) <= 9UL) )
965 #define CY_SCB_UART_IS_OVERSAMPLE_VALID(ovs, mode, lpRx) ( ((CY_SCB_UART_STANDARD == (mode)) || (CY_SCB_UART_SMARTCARD == (mode))) ? \
966 (((ovs) >= 8UL) && ((ovs) <= 16UL)) : \
967 (bool) ((lpRx) ? CY_SCB_UART_IS_IRDA_LP_OVS_VALID(ovs) : true) )
968
969 #define CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, width) ( ((width) >= (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, (base)->RX_CTRL) + 3UL)) && \
970 ((width) <= 16UL) )
971 #define CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 16UL) )
972
973 #define CY_SCB_UART_IS_MUTLI_PROC_VALID(mp, mode, width, parity) ( (mp) ? ((CY_SCB_UART_STANDARD == (mode)) && ((width) == 9UL) && \
974 (CY_SCB_UART_PARITY_NONE == (parity))) : true)
975 /** \endcond */
976
977 /** \} group_scb_uart_macros */
978
979
980 /*******************************************************************************
981 * In-line Function Implementation
982 *******************************************************************************/
983
984 /**
985 * \addtogroup group_scb_uart_general_functions
986 * \{
987 */
988
989 /*******************************************************************************
990 * Function Name: Cy_SCB_UART_Enable
991 ****************************************************************************//**
992 *
993 * Enables the SCB block for the UART operation.
994 *
995 * \param base
996 * The pointer to the UART SCB instance.
997 *
998 *******************************************************************************/
Cy_SCB_UART_Enable(CySCB_Type * base)999 __STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base)
1000 {
1001 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk;
1002 }
1003
1004
1005 /*******************************************************************************
1006 * Function Name: Cy_SCB_UART_EnableCts
1007 ****************************************************************************//**
1008 *
1009 * Enables the Clear to Send (CTS) input for the UART. The UART will not transmit
1010 * data while this signal is inactive.
1011 *
1012 * \param base
1013 * The pointer to the UART SCB instance.
1014 *
1015 *******************************************************************************/
Cy_SCB_UART_EnableCts(CySCB_Type * base)1016 __STATIC_INLINE void Cy_SCB_UART_EnableCts(CySCB_Type *base)
1017 {
1018 SCB_UART_FLOW_CTRL(base) |= SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk;
1019 }
1020
1021
1022 /*******************************************************************************
1023 * Function Name: Cy_SCB_UART_DisableCts
1024 ****************************************************************************//**
1025 *
1026 * Disables the Clear to Send (CTS) input for the UART.
1027 * See \ref Cy_SCB_UART_EnableCts for the details.
1028 *
1029 * \param base
1030 * The pointer to the UART SCB instance.
1031 *
1032 *******************************************************************************/
Cy_SCB_UART_DisableCts(CySCB_Type * base)1033 __STATIC_INLINE void Cy_SCB_UART_DisableCts(CySCB_Type *base)
1034 {
1035 SCB_UART_FLOW_CTRL(base) &= (uint32_t) ~SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk;
1036 }
1037
1038
1039 /*******************************************************************************
1040 * Function Name: Cy_SCB_UART_SetRtsFifoLevel
1041 ****************************************************************************//**
1042 *
1043 * Sets a level for the Ready To Send (RTS) signal activation.
1044 * When the number of data elements in the receive FIFO is below this level,
1045 * then the RTS output is active. Otherwise, the RTS signal is inactive.
1046 * To disable the RTS signal generation, set this level to zero.
1047 *
1048 * \param base
1049 * The pointer to the UART SCB instance.
1050 *
1051 * \param level
1052 * The level in the RX FIFO for RTS signal activation.
1053 *
1054 *******************************************************************************/
Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type * base,uint32_t level)1055 __STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level)
1056 {
1057 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
1058
1059 CY_REG32_CLR_SET(SCB_UART_FLOW_CTRL(base), SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, level);
1060 }
1061
1062
1063 /*******************************************************************************
1064 * Function Name: Cy_SCB_UART_GetRtsFifoLevel
1065 ****************************************************************************//**
1066 *
1067 * Returns the level in the RX FIFO for the RTS signal activation.
1068 *
1069 * \param base
1070 * The pointer to the UART SCB instance.
1071 *
1072 * \return
1073 * The level in the RX FIFO for RTS signal activation.
1074 *
1075 *******************************************************************************/
Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const * base)1076 __STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base)
1077 {
1078 return _FLD2VAL(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, SCB_UART_FLOW_CTRL(base));
1079 }
1080
1081
1082 /*******************************************************************************
1083 * Function Name: Cy_SCB_UART_EnableSkipStart
1084 ****************************************************************************//**
1085 *
1086 * Enables the skip start-bit functionality.
1087 * When skip start is enabled the UART hardware does not synchronize to a
1088 * start bit but synchronizes to the first rising edge. To create a rising edge,
1089 * the first data bit must be a 1. This feature is useful when the start bit
1090 * falling edge is used to wake the device through a GPIO interrupt.
1091 *
1092 * \param base
1093 * The pointer to the UART SCB instance.
1094 *
1095 * \note
1096 * When skip start-bit feature is enabled, it is applied (UART synchronizes
1097 * to the first rising edge after start bit) whenever the SCB is enabled.
1098 * This can cause incorrect UART synchronization and data reception when
1099 * the first data bit is not a 1. Therefore, disable the skip start-bit
1100 * when it should not be applied.
1101 * Note that SCB is disabled before enter Deep Sleep mode or after calling
1102 * \ref Cy_SCB_UART_Disable.
1103 *
1104 *******************************************************************************/
Cy_SCB_UART_EnableSkipStart(CySCB_Type * base)1105 __STATIC_INLINE void Cy_SCB_UART_EnableSkipStart(CySCB_Type *base)
1106 {
1107 SCB_UART_RX_CTRL(base) |= SCB_UART_RX_CTRL_SKIP_START_Msk;
1108 }
1109
1110
1111 /*******************************************************************************
1112 * Function Name: Cy_SCB_UART_DisableSkipStart
1113 ****************************************************************************//**
1114 *
1115 * Disable the skip start-bit functionality.
1116 * See \ref Cy_SCB_UART_EnableSkipStart for the details.
1117 *
1118 * \param base
1119 * The pointer to the UART SCB instance.
1120 *
1121 *******************************************************************************/
Cy_SCB_UART_DisableSkipStart(CySCB_Type * base)1122 __STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base)
1123 {
1124 SCB_UART_RX_CTRL(base) &= (uint32_t) ~SCB_UART_RX_CTRL_SKIP_START_Msk;
1125 }
1126
1127 #if ((defined(CY_IP_MXSCB_VERSION)) && (CY_IP_MXSCB_VERSION >= 4)) || defined (CY_DOXYGEN)
1128 /*******************************************************************************
1129 * Function Name: Cy_SCB_UART_EnableSingleWireHalfDuplex
1130 ****************************************************************************//**
1131 *
1132 * Enables Single Wire Half Duplex Communication.
1133 * \note This is applicable in standard UART submode only.
1134 *
1135 * \param base
1136 * The pointer to the UART SCB instance.
1137 *
1138 * \note
1139 * This API is available for PSoC C3 (CAT1B) devices.
1140 *
1141 *******************************************************************************/
Cy_SCB_UART_EnableSingleWireHalfDuplex(CySCB_Type * base)1142 __STATIC_INLINE void Cy_SCB_UART_EnableSingleWireHalfDuplex(CySCB_Type *base)
1143 {
1144 SCB_UART_RX_CTRL(base) |= SCB_UART_RX_CTRL_HDRXEN_Msk;
1145 }
1146
1147
1148 /*******************************************************************************
1149 * Function Name: Cy_SCB_UART_DisableSingleWireHalfDuplex
1150 ****************************************************************************//**
1151 *
1152 * Disables Single Wire Half Duplex Communication.
1153 * \note This is applicable in standard UART submode only.
1154 *
1155 * \param base
1156 * The pointer to the UART SCB instance.
1157 *
1158 * \note
1159 * This API is available for PSoC C3 (CAT1B) devices.
1160 *
1161 *******************************************************************************/
Cy_SCB_UART_DisableSingleWireHalfDuplex(CySCB_Type * base)1162 __STATIC_INLINE void Cy_SCB_UART_DisableSingleWireHalfDuplex(CySCB_Type *base)
1163 {
1164 SCB_UART_RX_CTRL(base) &= (uint32_t) ~SCB_UART_RX_CTRL_HDRXEN_Msk;
1165 }
1166 #endif /* ((defined(CY_IP_MXSCB_VERSION)) && (CY_IP_MXSCB_VERSION >= 4)) */
1167
1168 /** \} group_scb_uart_general_functions */
1169
1170
1171 /**
1172 * \addtogroup group_scb_uart_low_level_functions
1173 * \{
1174 */
1175
1176
1177 /*******************************************************************************
1178 * Function Name: Cy_SCB_UART_GetOverSample
1179 ****************************************************************************//**
1180 *
1181 * Returns the value of oversample.
1182 *
1183 * \param base
1184 * The pointer to the UART SCB instance.
1185 *
1186 * \return
1187 * The value of oversample.
1188 *
1189 * \snippet scb/uart_snippet/main.c UART_GET_OVS
1190 *
1191 *******************************************************************************/
Cy_SCB_UART_GetOverSample(CySCB_Type const * base)1192 __STATIC_INLINE uint32_t Cy_SCB_UART_GetOverSample(CySCB_Type const *base)
1193 {
1194 return (_FLD2VAL(SCB_CTRL_OVS, SCB_CTRL(base))+1UL);
1195 }
1196
1197
1198 /*******************************************************************************
1199 * Function Name: Cy_SCB_UART_GetDataWidth
1200 ****************************************************************************//**
1201 *
1202 * Returns the value of datawidth.
1203 *
1204 * \param base
1205 * The pointer to the UART SCB instance.
1206 *
1207 * \return
1208 * The value of datawidth.
1209 *
1210 * \note
1211 * Values of Tx and Rx datawidth are same.
1212 *
1213 * \snippet scb/uart_snippet/main.c UART_GET_DATA_WIDTH
1214 *
1215 *******************************************************************************/
Cy_SCB_UART_GetDataWidth(CySCB_Type const * base)1216 __STATIC_INLINE uint32_t Cy_SCB_UART_GetDataWidth(CySCB_Type const *base)
1217 {
1218 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base))+1UL);
1219 }
1220
1221
1222 /*******************************************************************************
1223 * Function Name: Cy_SCB_UART_GetParity
1224 ****************************************************************************//**
1225 *
1226 * Returns the value of parity.
1227 *
1228 * \param base
1229 * The pointer to the UART SCB instance.
1230 *
1231 * \return
1232 * The value of parity.
1233 *
1234 * \note
1235 * Values of Tx and Rx parity are same.
1236 *
1237 * \snippet scb/uart_snippet/main.c UART_GET_PARITY
1238 *
1239 *******************************************************************************/
Cy_SCB_UART_GetParity(CySCB_Type const * base)1240 __STATIC_INLINE uint32_t Cy_SCB_UART_GetParity(CySCB_Type const *base)
1241 {
1242 return _FLD2VAL(CY_SCB_UART_TX_CTRL_SET_PARITY, SCB_UART_TX_CTRL(base));
1243 }
1244
1245
1246 /*******************************************************************************
1247 * Function Name: Cy_SCB_UART_GetStopBits
1248 ****************************************************************************//**
1249 *
1250 * Returns the value of stop bits.
1251 *
1252 * \param base
1253 * The pointer to the UART SCB instance.
1254 *
1255 * \return
1256 * The value of stop bits.
1257 *
1258 * \note
1259 * Values of Tx and Rx stop bits are same.
1260 *
1261 * \snippet scb/uart_snippet/main.c UART_GET_STOP_BITS
1262 *
1263 *******************************************************************************/
Cy_SCB_UART_GetStopBits(CySCB_Type const * base)1264 __STATIC_INLINE uint32_t Cy_SCB_UART_GetStopBits(CySCB_Type const *base)
1265 {
1266 return (_FLD2VAL(SCB_UART_TX_CTRL_STOP_BITS, SCB_UART_TX_CTRL(base))+1UL);
1267 }
1268
1269
1270 /*******************************************************************************
1271 * Function Name: Cy_SCB_UART_GetDropOnParityError
1272 ****************************************************************************//**
1273 *
1274 * Returns the value of SetDropOnParityError.
1275 *
1276 * \param base
1277 * The pointer to the UART SCB instance.
1278 *
1279 * \return
1280 * The value of SetDropOnParityError.
1281 *
1282 * \snippet scb/uart_snippet/main.c UART_GET_DROP_ON_PARITY_ERROR
1283 *
1284 *******************************************************************************/
Cy_SCB_UART_GetDropOnParityError(CySCB_Type const * base)1285 __STATIC_INLINE bool Cy_SCB_UART_GetDropOnParityError(CySCB_Type const *base)
1286 {
1287 return _FLD2BOOL(SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR, SCB_UART_RX_CTRL(base));
1288 }
1289
1290
1291 /*******************************************************************************
1292 * Function Name: Cy_SCB_UART_GetEnableMsbFirst
1293 ****************************************************************************//**
1294 *
1295 * Returns the value of enableMsbFirst.
1296 *
1297 * \param base
1298 * The pointer to the UART SCB instance.
1299 *
1300 * \return
1301 * The value of enableMsbFirst.
1302 *
1303 * \note
1304 * Values of Tx and Rx enableMsbFirst are same.
1305 *
1306 * \snippet scb/uart_snippet/main.c UART_GET_ENABLE_MSB_FIRST
1307 *
1308 *******************************************************************************/
Cy_SCB_UART_GetEnableMsbFirst(CySCB_Type const * base)1309 __STATIC_INLINE bool Cy_SCB_UART_GetEnableMsbFirst(CySCB_Type const *base)
1310 {
1311 return _FLD2BOOL(SCB_TX_CTRL_MSB_FIRST, SCB_TX_CTRL(base));
1312 }
1313
1314
1315 /*******************************************************************************
1316 * Function Name: Cy_SCB_UART_Get
1317 ****************************************************************************//**
1318 *
1319 * Reads a single data element from the UART RX FIFO.
1320 * This function does not check whether the RX FIFO has data before reading it.
1321 * If the RX FIFO is empty, the function returns \ref CY_SCB_UART_RX_NO_DATA.
1322 *
1323 * \param base
1324 * The pointer to the UART SCB instance.
1325 *
1326 * \return
1327 * Data from the RX FIFO.
1328 * The data element size is defined by the configured data width.
1329 *
1330 *******************************************************************************/
Cy_SCB_UART_Get(CySCB_Type const * base)1331 __STATIC_INLINE uint32_t Cy_SCB_UART_Get(CySCB_Type const *base)
1332 {
1333 return Cy_SCB_ReadRxFifo(base);
1334 }
1335
1336
1337 /*******************************************************************************
1338 * Function Name: Cy_SCB_UART_GetArray
1339 ****************************************************************************//**
1340 *
1341 * Reads an array of data out of the UART RX FIFO.
1342 * This function does not block. It returns how many data elements were read
1343 * from the RX FIFO.
1344 *
1345 * \param base
1346 * The pointer to the UART SCB instance.
1347 *
1348 * \param buffer
1349 * The pointer to the location to place the data read from the RX FIFO.
1350 * The element size is defined by the data type, which depends on the configured
1351 * data width.
1352 *
1353 * \param size
1354 * The number of data elements to read from the RX FIFO.
1355 *
1356 * \return
1357 * The number of data elements read from the RX FIFO.
1358 *
1359 *******************************************************************************/
Cy_SCB_UART_GetArray(CySCB_Type const * base,void * buffer,uint32_t size)1360 __STATIC_INLINE uint32_t Cy_SCB_UART_GetArray(CySCB_Type const *base, void *buffer, uint32_t size)
1361 {
1362 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
1363
1364 return Cy_SCB_ReadArray(base, buffer, size);
1365 }
1366
1367
1368 /*******************************************************************************
1369 * Function Name: Cy_SCB_UART_GetArrayBlocking
1370 ****************************************************************************//**
1371 *
1372 * Reads an array of data out of the UART RX FIFO.
1373 * This function blocks until the number of data elements specified by the
1374 * size has been read from the RX FIFO.
1375 *
1376 * \param base
1377 * The pointer to the UART SCB instance.
1378 *
1379 * \param buffer
1380 * The pointer to the location to place the data read from the RX FIFO.
1381 * The element size is defined by the data type, which depends on the configured
1382 * data width.
1383 *
1384 * \param size
1385 * The number of data elements to read from the RX FIFO.
1386 *
1387 *******************************************************************************/
Cy_SCB_UART_GetArrayBlocking(CySCB_Type const * base,void * buffer,uint32_t size)1388 __STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size)
1389 {
1390 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
1391
1392 Cy_SCB_ReadArrayBlocking(base, buffer, size);
1393 }
1394
1395
1396 /*******************************************************************************
1397 * Function Name: Cy_SCB_UART_GetRxFifoStatus
1398 ****************************************************************************//**
1399 *
1400 * Returns the current status of the RX FIFO.
1401 *
1402 * \param base
1403 * The pointer to the UART SCB instance.
1404 *
1405 * \return
1406 * \ref group_scb_uart_macros_rx_fifo_status
1407 *
1408 *******************************************************************************/
Cy_SCB_UART_GetRxFifoStatus(CySCB_Type const * base)1409 __STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus(CySCB_Type const *base)
1410 {
1411 return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_UART_RX_INTR_MASK);
1412 }
1413
1414
1415 /*******************************************************************************
1416 * Function Name: Cy_SCB_UART_ClearRxFifoStatus
1417 ****************************************************************************//**
1418 *
1419 * Clears the selected statuses of the RX FIFO.
1420 *
1421 * \param base
1422 * The pointer to the UART SCB instance.
1423 *
1424 * \param clearMask
1425 * The mask whose statuses to clear.
1426 * See \ref group_scb_uart_macros_rx_fifo_status for the set of constants.
1427 *
1428 * \note
1429 * * This status is also used for interrupt generation, so clearing it also
1430 * clears the interrupt sources.
1431 * * Level-sensitive statuses such as \ref CY_SCB_UART_RX_TRIGGER,
1432 * \ref CY_SCB_UART_RX_NOT_EMPTY and \ref CY_SCB_UART_RX_FULL are set high again after
1433 * being cleared if the condition remains true.
1434 *
1435 *******************************************************************************/
Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type * base,uint32_t clearMask)1436 __STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask)
1437 {
1438 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_RX_INTR_MASK));
1439
1440 Cy_SCB_ClearRxInterrupt(base, clearMask);
1441 }
1442
1443
1444 /*******************************************************************************
1445 * Function Name: Cy_SCB_UART_GetNumInRxFifo
1446 ****************************************************************************//**
1447 *
1448 * Returns the number of data elements in the UART RX FIFO.
1449 *
1450 * \param base
1451 * The pointer to the UART SCB instance.
1452 *
1453 * \return
1454 * The number of data elements in the RX FIFO.
1455 * The size of date element defined by the configured data width.
1456 *
1457 *******************************************************************************/
Cy_SCB_UART_GetNumInRxFifo(CySCB_Type const * base)1458 __STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo(CySCB_Type const *base)
1459 {
1460 return Cy_SCB_GetNumInRxFifo(base);
1461 }
1462
1463 /*******************************************************************************
1464 * Function Name: Cy_SCB_UART_ClearRxFifo
1465 ****************************************************************************//**
1466 *
1467 * Clears all data out of the UART RX FIFO.
1468 *
1469 * \param base
1470 * The pointer to the UART SCB instance.
1471 *
1472 * \sideeffect
1473 * Any data currently in the shifter is cleared and lost.
1474 *
1475 *******************************************************************************/
Cy_SCB_UART_ClearRxFifo(CySCB_Type * base)1476 __STATIC_INLINE void Cy_SCB_UART_ClearRxFifo(CySCB_Type *base)
1477 {
1478 Cy_SCB_ClearRxFifo(base);
1479 }
1480
1481
1482 /*******************************************************************************
1483 * Function Name: Cy_SCB_UART_Put
1484 ****************************************************************************//**
1485 *
1486 * Places a single data element in the UART TX FIFO.
1487 * This function does not block and returns how many data elements were placed
1488 * in the TX FIFO.
1489 *
1490 * \param base
1491 * The pointer to the UART SCB instance.
1492 *
1493 * \param data
1494 * Data to put in the TX FIFO.
1495 * The element size is defined by the data type, which depends on the configured
1496 * data width.
1497 *
1498 * \return
1499 * The number of data elements placed in the TX FIFO: 0 or 1.
1500 *
1501 *******************************************************************************/
Cy_SCB_UART_Put(CySCB_Type * base,uint32_t data)1502 __STATIC_INLINE uint32_t Cy_SCB_UART_Put(CySCB_Type *base, uint32_t data)
1503 {
1504 return Cy_SCB_Write(base, data);
1505 }
1506
1507
1508 /*******************************************************************************
1509 * Function Name: Cy_SCB_UART_PutArray
1510 ****************************************************************************//**
1511 *
1512 * Places an array of data in the UART TX FIFO.
1513 * This function does not block. It returns how many data elements were
1514 * placed in the TX FIFO.
1515 *
1516 * \param base
1517 * The pointer to the UART SCB instance.
1518 *
1519 * \param buffer
1520 * The pointer to data to place in the TX FIFO.
1521 * The element size is defined by the data type, which depends on the configured
1522 * TX data width.
1523 *
1524 * \param size
1525 * The number of data elements to TX.
1526 *
1527 * \return
1528 * The number of data elements placed in the TX FIFO.
1529 *
1530 *******************************************************************************/
Cy_SCB_UART_PutArray(CySCB_Type * base,void * buffer,uint32_t size)1531 __STATIC_INLINE uint32_t Cy_SCB_UART_PutArray(CySCB_Type *base, void *buffer, uint32_t size)
1532 {
1533 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
1534
1535 return Cy_SCB_WriteArray(base, buffer, size);
1536 }
1537
1538
1539 /*******************************************************************************
1540 * Function Name: Cy_SCB_UART_PutArrayBlocking
1541 ****************************************************************************//**
1542 *
1543 * Places an array of data in the UART TX FIFO.
1544 * This function blocks until the number of data elements specified by the size
1545 * is placed in the TX FIFO.
1546 *
1547 * \param base
1548 * The pointer to the UART SCB instance.
1549 *
1550 * \param buffer
1551 * The pointer to data to place in the TX FIFO.
1552 * The element size is defined by the data type, which depends on the configured
1553 * data width.
1554 *
1555 * \param size
1556 * The number of data elements to write into the TX FIFO.
1557 *
1558 *******************************************************************************/
Cy_SCB_UART_PutArrayBlocking(CySCB_Type * base,void * buffer,uint32_t size)1559 __STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size)
1560 {
1561 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
1562
1563 Cy_SCB_WriteArrayBlocking(base, buffer, size);
1564 }
1565
1566
1567 /*******************************************************************************
1568 * Function Name: Cy_SCB_UART_PutString
1569 ****************************************************************************//**
1570 *
1571 * Places a NULL terminated string in the UART TX FIFO.
1572 * This function blocks until the entire string is placed in the TX FIFO.
1573 *
1574 * \param base
1575 * The pointer to the UART SCB instance.
1576 *
1577 * \param string
1578 * The pointer to the null terminated string array.
1579 *
1580 *******************************************************************************/
Cy_SCB_UART_PutString(CySCB_Type * base,char_t const string[])1581 __STATIC_INLINE void Cy_SCB_UART_PutString(CySCB_Type *base, char_t const string[])
1582 {
1583 CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(string, 1UL));
1584
1585 Cy_SCB_WriteString(base, string);
1586 }
1587
1588
1589 /*******************************************************************************
1590 * Function Name: Cy_SCB_UART_GetTxFifoStatus
1591 ****************************************************************************//**
1592 *
1593 * Returns the current status of the TX FIFO.
1594 *
1595 * \param base
1596 * The pointer to the UART SCB instance.
1597 *
1598 * \return
1599 * \ref group_scb_uart_macros_tx_fifo_status
1600 *
1601 *******************************************************************************/
Cy_SCB_UART_GetTxFifoStatus(CySCB_Type const * base)1602 __STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus(CySCB_Type const *base)
1603 {
1604 return (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_UART_TX_INTR_MASK);
1605 }
1606
1607
1608 /*******************************************************************************
1609 * Function Name: Cy_SCB_UART_ClearTxFifoStatus
1610 ****************************************************************************//**
1611 *
1612 * Clears the selected statuses of the TX FIFO.
1613 *
1614 * \param base
1615 * The pointer to the UART SCB instance.
1616 *
1617 * \param clearMask
1618 * The mask whose statuses to clear.
1619 * See \ref group_scb_uart_macros_tx_fifo_status for the set of constants.
1620 *
1621 * \note
1622 * * The status is also used for interrupt generation, so clearing it also
1623 * clears the interrupt sources.
1624 * * Level-sensitive statuses such as \ref CY_SCB_UART_TX_TRIGGER,
1625 * \ref CY_SCB_UART_TX_EMPTY and \ref CY_SCB_UART_TX_NOT_FULL are set high again after
1626 * being cleared if the condition remains true.
1627 *
1628 *******************************************************************************/
Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type * base,uint32_t clearMask)1629 __STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask)
1630 {
1631 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_TX_INTR_MASK));
1632
1633 Cy_SCB_ClearTxInterrupt(base, clearMask);
1634 }
1635
1636
1637 /*******************************************************************************
1638 * Function Name: Cy_SCB_UART_GetNumInTxFifo
1639 ****************************************************************************//**
1640 *
1641 * Returns the number of data elements in the UART TX FIFO.
1642 *
1643 * \param base
1644 * The pointer to the UART SCB instance.
1645 *
1646 * \return
1647 * The number of data elements in the TX FIFO.
1648 * The size of date element defined by the configured data width.
1649 *
1650 * \note
1651 * This number does not include any data currently in the TX shifter.
1652 *
1653 *******************************************************************************/
Cy_SCB_UART_GetNumInTxFifo(CySCB_Type const * base)1654 __STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo(CySCB_Type const *base)
1655 {
1656 return Cy_SCB_GetNumInTxFifo(base);
1657 }
1658
1659
1660 /*******************************************************************************
1661 * Function Name: Cy_SCB_UART_IsTxComplete
1662 ****************************************************************************//**
1663 *
1664 * Checks whether the TX FIFO and Shifter are empty and there is no more data to send
1665 *
1666 * \param base
1667 * Pointer to the UART SCB instance.
1668 *
1669 * \return
1670 * If true, transmission complete. If false, transmission is not complete.
1671 *
1672 *******************************************************************************/
Cy_SCB_UART_IsTxComplete(CySCB_Type const * base)1673 __STATIC_INLINE bool Cy_SCB_UART_IsTxComplete(CySCB_Type const *base)
1674 {
1675 return Cy_SCB_IsTxComplete(base);
1676 }
1677
1678
1679 /*******************************************************************************
1680 * Function Name: Cy_SCB_UART_ClearTxFifo
1681 ****************************************************************************//**
1682 *
1683 * Clears all data out of the UART TX FIFO.
1684 *
1685 * \param base
1686 * The pointer to the UART SCB instance.
1687 *
1688 * \sideeffect
1689 * The TX FIFO clear operation also clears the shift register, so that
1690 * the shifter could be cleared in the middle of a data element transfer,
1691 * corrupting it. The data element corruption means that all bits that have
1692 * not been transmitted are transmitted as 1s on the bus.
1693 *
1694 *******************************************************************************/
Cy_SCB_UART_ClearTxFifo(CySCB_Type * base)1695 __STATIC_INLINE void Cy_SCB_UART_ClearTxFifo(CySCB_Type *base)
1696 {
1697 Cy_SCB_ClearTxFifo(base);
1698 }
1699 /** \} group_scb_uart_low_level_functions */
1700
1701 /**
1702 * \addtogroup group_scb_uart_interrupt_functions
1703 * \{
1704 */
1705 /*******************************************************************************
1706 * Function Name: Cy_SCB_UART_RegisterCallback
1707 ****************************************************************************//**
1708 *
1709 * Registers a callback function that notifies that
1710 * \ref group_scb_uart_macros_callback_events occurred in the
1711 * \ref Cy_SCB_UART_Interrupt.
1712 *
1713 * \param base
1714 * The pointer to the UART SCB instance.
1715 *
1716 * \param callback
1717 * The pointer to the callback function.
1718 * See \ref cy_cb_scb_uart_handle_events_t for the function prototype.
1719 *
1720 * \param context
1721 * The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
1722 * by the user. The structure is used during the UART operation for internal
1723 * configuration and data retention. The user should not modify anything
1724 * in this structure.
1725 *
1726 * \note
1727 * To remove the callback, pass NULL as the pointer to the callback function.
1728 *
1729 *******************************************************************************/
Cy_SCB_UART_RegisterCallback(CySCB_Type const * base,cy_cb_scb_uart_handle_events_t callback,cy_stc_scb_uart_context_t * context)1730 __STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base,
1731 cy_cb_scb_uart_handle_events_t callback, cy_stc_scb_uart_context_t *context)
1732 {
1733 /* Suppress a compiler warning about unused variables */
1734 (void) base;
1735
1736 context->cbEvents = callback;
1737 }
1738 /** \} group_scb_uart_interrupt_functions */
1739
1740 #if defined(__cplusplus)
1741 }
1742 #endif
1743
1744 /** \} group_scb_uart */
1745
1746 #endif /* (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB)) */
1747
1748 #endif /* (CY_SCB_UART_H) */
1749 /* [] END OF FILE */
1750
