1 /***************************************************************************//** 2 * \file cy_flash.h 3 * \version 3.110 4 * 5 * Provides the API declarations of the Flash driver. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2016-2021 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 #if !defined (CY_FLASH_H) 26 #define CY_FLASH_H 27 28 /** 29 * \addtogroup group_flash 30 * \{ 31 * Internal flash memory programming 32 * 33 * The functions and other declarations used in this driver are in cy_flash.h. 34 * You can include cy_pdl.h to get access to all functions 35 * and declarations in the PDL. 36 * 37 * Flash memory in PSoC devices provides non-volatile storage for user firmware, 38 * user configuration data, and bulk data storage. 39 * 40 * Flash operations are implemented as system calls. System calls are executed 41 * out of SROM in the privileged mode of operation. Users have no access to read 42 * or modify the SROM code. The driver API requests the system call by acquiring 43 * the Inter-processor communication (IPC) and writing the SROM function opcode 44 * and parameters to its input registers. As a result, an NMI interrupt is invoked 45 * and the requested SROM function is executed. The operation status is returned 46 * to the driver context and a release interrupt is triggered. 47 * 48 * Writing to flash can take up to 20 milliseconds. During this time, 49 * the device should not be reset (including XRES pin, software reset, and 50 * watchdog) or unexpected changes may be made to portions of the flash. 51 * Also, the low-voltage detect circuits should be configured to generate an 52 * interrupt instead of a reset. 53 * 54 * A Read while Write violation occurs when a flash Read operation is initiated 55 * in the same or neighboring (neighboring restriction is applicable just for the 56 * CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or 57 * Program operation is working. This violation may cause a HardFault exception. 58 * To avoid the Read while Write violation, carefully split the 59 * Read and Write operation on flash sectors which are not neighboring, 60 * considering both cores in the multi-processor device. If the flash is divided 61 * into four equal sectors, you may edit the linker script to place the code 62 * into neighboring sectors. For example, use sectors number 0 and 1 for code 63 * and sectors 2 and 3 for data storage. 64 * 65 * \section group_flash_configuration Configuration Considerations 66 * 67 * \subsection group_flash_config_intro Introduction: 68 * The CAT1A devices user-programmable Flash consists of: 69 * - Application flash memory (from 2 to 8 sectors) - 128KB/256KB each. 70 * - EE emulation flash memory - 32KB. 71 * 72 * The CAT1C devices user-programmable Flash consists of: 73 * - Work flash region has 48 large sectors of 2 KB and 256 small sectors of 128 B. 74 * 75 * Write operation may be done as Blocking or Partially Blocking, 76 * defined as follows: 77 * 78 * \subsection group_flash_config_blocking Blocking: 79 * In this case, the entire Flash block is not available for the duration of the 80 * Write (∼16ms). Therefore, no Flash accesses (from any Bus Master) can 81 * occur during that time. CPU execution can be performed from SRAM. All 82 * pre-fetching must be disabled. Code execution from Flash is blocked for the 83 * Flash Write duration for both cores. 84 * 85 * \subsection group_flash_config_block_const Constraints for Blocking Flash operations: 86 * -# During write to flash, the device should not be reset (including XRES pin, 87 * software reset, and watchdog), or unexpected changes may be made to portions 88 * of the flash. 89 * -# The low-voltage detect circuits should be configured to generate an 90 * interrupt instead of a reset. 91 * -# Flash write operation in CAT1A devices is allowed only in one of the following CM4 states: 92 * -# CM4 is Active and initialized:<br> 93 * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". 94 * <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time 95 * after calling Cy_SysEnableCM4(). 96 * -# CM4 is Off and disabled:<br> 97 * call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not 98 * supported. 99 * 100 * -# Flash Write cannot be performed in Ultra Low Power (core voltage 0.9V) mode. 101 * -# Interrupts must be enabled on both active cores. Do not enter a critical 102 * section during flash operation. 103 * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe 104 * interrupts (IPC interrupts 3 and 4) have the highest priority, or 105 * at least that pipe interrupts are not interrupted or in a pending state 106 * for more than 700 µs. 107 * -# For CAT1A devices user must guarantee that during flash write operation no flash read 108 * operations are performed by bus masters other than CM0+ and CM4 (DMA and 109 * Crypto). 110 * -# For the CY8C6xx6, CY8C6xx7 devices if you do not use the default startup, perform the following steps 111 * before any flash write/erase operations: 112 * \snippet flash/snippet/main.c Flash Initialization 113 * 114 * \subsection group_flash_config_rww Partially Blocking: 115 * This method has a much shorter time window during which Flash accesses are not 116 * allowed. Application code execution from Flash is blocked for only a part of 117 * Flash Write duration, for both cores. Blocking duration depends upon the API 118 * sequence used. 119 * 120 * For CAT1A Devices API sequence Cy_Flash_StartEraseRow() + Cy_Flash_StartProgram() there are 121 * four block-out regions during which Read is blocked. See <b>Figure 1</b>. 122 * 123 * For CAT1C devices Flash memory controller has the dual bank mode feature. When using dual bank mode, 124 * flash memory region is split into two half banks. One is called Logical Bank 0 and the other is called Logical Bank 1 125 * User will be able to read from a different logical bank while writing to one logical bank. 126 * 127 * For CAT1C devices Erase ROW is not supported. User has to erase the entire sector before writing to the sector. 128 * 129 * CM7 cores in CAT1C devices support Data Cache. Data Cache line is 32 bytes. 130 * User needs to make sure that the pointer passed to the following functions points to 32 byte aligned data. 131 * Cy_Flash_StartWrite, Cy_Flash_ProgramRow, Cy_Flash_Program and Cy_Flash_Program_WorkFlash. 132 * User can use CY_ALIGN(32) macro for 32 byte alignment. 133 * 134 * CAT1B devices run on single core and hence IPC is not used for erase and write operations on flash memory. 135 * 136 * <center> 137 * <table class="doxtable"> 138 * <caption>Table 1 - Block-out periods (timing values are valid just for the 139 * CY8C6xx6, CY8C6xx7 devices) </caption> 140 * <tr> 141 * <th>Block-out</th> 142 * <th>Phase</th> 143 * <th>Duration</th> 144 * </tr> 145 * <tr> 146 * <td>A</td> 147 * <td>The beginning of the Erase operation</td> 148 * <td>2ms + 9500 SlowClk cycles</td> 149 * </tr> 150 * <tr> 151 * <td>B</td> 152 * <td>The end of the Erase operation</td> 153 * <td>0.13ms + 1000 SlowClk cycles</td> 154 * </tr> 155 * <tr> 156 * <td>C</td> 157 * <td>The beginning of the Program operation</td> 158 * <td>0.8ms + 6000 SlowClk cycles</td> 159 * </tr> 160 * <tr> 161 * <td>D</td> 162 * <td>The end of the Program operation</td> 163 * <td>0.13ms + 1000 SlowClk cycles</td> 164 * </tr> 165 * </table> 166 * </center> 167 * 168 * This allows both cores to execute for about 80% of Flash Write 169 * operation - see <b>Figure 1</b>. 170 * This capability is important for communication protocols that rely on fast 171 * response. 172 * 173 * \image html flash-rww-diagram.png "Figure 1 - Blocking Intervals in Flash Write operation" 174 * 175 * For the Cy_Flash_StartWrite() function, the block-out period is different for 176 * the two cores. The core that initiates Cy_Flash_StartWrite() is blocked for 177 * two periods: 178 * - From start of Erase operation (start of A on Figure 1) till the start of 179 * Program operation (end of C on Figure 1). 180 * - During D period on <b>Figure 1</b>. 181 * 182 * The core that performs read/execute is blocked identically to the previous 183 * scenario - see <b>Figure 1</b>. 184 * 185 * This allows the core that initiates Cy_Flash_StartWrite() to execute for about 186 * 20% of Flash Write operation. The other core executes for about 80% of Flash 187 * Write operation. 188 * 189 * In CAT1B devices with flash IP CY_IP_MXS40FLASHC 190 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 191 * User need to make sure that this data is not corrupted while writing and erasing the row data. 192 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 193 * 194 * Some constraints must be planned for in the Partially Blocking mode which are 195 * described in detail below. 196 * 197 * \subsection group_flash_config_rww_const Constraints for Partially Blocking Flash operations: 198 * -# During write to flash, the device should not be reset (including XRES pin, 199 * software reset, and watchdog) or unexpected changes may be made to portions 200 * of the flash. 201 * -# The low-voltage detect circuits should be configured to generate an 202 * interrupt instead of a reset. 203 * -# During write to flash, application code should not change the clock 204 * settings. Use Cy_Flash_IsOperationComplete() to ensure flash write 205 * operation is finished. 206 * -# During write to flash, application code should not start the clock 207 * measurements (should not call Cy_SysClk_StartClkMeasurementCounters()). 208 * -# For CAT1A devices Flash write operation is allowed only in one of the following CM4 states: 209 * -# CM4 is Active and initialized:<br> 210 * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". 211 * <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time 212 * after calling Cy_SysEnableCM4(). 213 * -# CM4 is Off and disabled:<br> 214 * call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not 215 * supported. 216 * . 217 * -# For CAT1C devices flash write operation is only allowed after the sector in erased. 218 * -# For CAT1A devices use the following rules for split by sectors. (In this context, read means 219 * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) 220 * -# Do not write to and read/execute from the same flash sector at the same 221 * time. This is true for all sectors. 222 * -# Writing rules in application flash (this restriction is applicable just 223 * for CY8C6xx6, CY8C6xx7 devices): 224 * -# Any bus master can read/execute from UFLASH S0 and/or S1, during 225 * flash write to UFLASH S2 or S3. 226 * -# Any bus master can read/execute from UFLASH S2 and/or S3, during 227 * flash write to UFLASH S0 or S1. 228 * 229 * <b>Suggestion:</b> in case of bootloading, it is recommended to place 230 * code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data 231 * to S2 and S3 sections. 232 * . 233 * -# Flash Write cannot be performed in Ultra Low Power mode (core voltage 0.9V). 234 * -# Interrupts must be enabled on both active cores. Do not enter a critical 235 * section during flash operation. 236 * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe 237 * interrupts (IPC interrupts 3 and 4) have the highest priority, or at 238 * least that pipe interrupts are not interrupted or in a pending state 239 * for more than 700 µs. 240 * -# For the CY8C6xx6, CY8C6xx7 devices if you do not use the default startup, perform the following steps 241 * before any flash write/erase operations: 242 * \snippet flash/snippet/main.c Flash Initialization 243 * 244 * \subsection group_flash_config_emeeprom EEPROM section use: 245 * If you plan to use "cy_em_eeprom" section for different purposes for both of 246 * device cores or use <b>Em_EEPROM Middleware</b> together with flash driver 247 * write operations you must modify the linker scripts.<br> 248 * For more information, refer to the <b>Middleware/Cypress Em_EEPROM Middleware 249 * Library</b> section of the PDL documentation. 250 * 251 * \section group_flash_more_information More Information 252 * 253 * See the technical reference manual (TRM) for more information about the Flash 254 * architecture. 255 * 256 * \section group_flash_changelog Changelog 257 * 258 * <table class="doxtable"> 259 * <tr><th>Version</th><th style="width: 52%;">Changes</th><th>Reason for Change</th></tr> 260 * <tr> 261 * <td>3.110</td> 262 * <td>In Cy_Flash_SendCmd, waiting for CM0 to be ready to accept command.</td> 263 * <td></td> 264 * </tr> 265 * <tr> 266 * <td>3.100</td> 267 * <td>Added support for PSoC C3 (CAT1B).<br> 268 * Added flash refresh feature.<br> 269 * Added inject ecc disable and corrected address in inject ecc.</td> 270 * <td>Added support for new devices, added new feature and code enhancement.</td> 271 * </tr> 272 * <tr> 273 * <td>3.90</td> 274 * <td>Added support for TRAVEO™ II Body Entry devices.<br> 275 * Updated pre-processor check to only include code if ECT flash is not used.<br> 276 * In cy_flash_srom, changed pre-processor checks from using CM7 availability to using MXFLASHC ver. to determine flash hardware availability.<br> 277 * In cy_flash_srom, added interrupt compatibility for CM4 devices.</td> 278 * <td>Code enhancement and support for new devices.</td> 279 * </tr> 280 * <tr> 281 * <td>3.80</td> 282 * <td>Dual bank support added for CAT1A devices.</td> 283 * <td>Newly added APIs \ref Cy_Flashc_SetMain_Flash_Mapping , \ref Cy_Flashc_SetWork_Flash_Mapping for CAT1A and CAT1C devices.</td> 284 * </tr> 285 * <tr> 286 * <td>3.70</td> 287 * <td>Fixed MISRA 2012 violations and Documentation Update.</td> 288 * <td>MISRA 2012 compliance.</td> 289 * </tr> 290 * <tr> 291 * <td>3.60</td> 292 * <td>Added API's to support new product family. Enhancement for support of eCT flash.</td> 293 * <td>eCT flash's contains Code flash and Work flash. New API's to program/erase both work flash and code flash are added.</td> 294 * </tr> 295 * <tr> 296 * <td>3.50.1</td> 297 * <td>Updated documentation to limit devices with the restrictions.</td> 298 * <td>User experience enhancement.</td> 299 * </tr> 300 * <tr> 301 * <td rowspan="2">3.50</td> 302 * <td>Updated attribute usage for the linker section placement.</td> 303 * <td>Enhancement based on usability feedback.</td> 304 * </tr> 305 * <tr> 306 * <td>Fixed/documented MISRA 2012 violations.</td> 307 * <td>MISRA 2012 compliance.</td> 308 * </tr> 309 * <tr> 310 * <td rowspan="1">3.40</td> 311 * <td>Updated Cy_Flash_OperationStatus() to access protected registers.</td> 312 * <td>Added PSoC 64 device support.</td> 313 * </tr> 314 * <tr> 315 * <td rowspan="1">3.30.4</td> 316 * <td>Improved documentation.</td> 317 * <td>User experience enhancement.</td> 318 * </tr> 319 * <tr> 320 * <td rowspan="1">3.30.3</td> 321 * <td>Updated documentation to limit devices with the restrictions. Improved calculation of the CY_FLASH_DELAY_CORRECTIVE macro.</td> 322 * <td>User experience enhancement.</td> 323 * </tr> 324 * <tr> 325 * <td rowspan="1">3.30.2</td> 326 * <td>Updated documentation to limit devices with the neighboring restriction.</td> 327 * <td>User experience enhancement.</td> 328 * </tr> 329 * <tr> 330 * <td rowspan="1">3.30.1</td> 331 * <td>Used the CY_RAMFUNC_BEGIN and CY_RAMFUNC_END macros that allocate the function in RAM instead of using the CY_SECTION(".cy_ramfunc") macros.</td> 332 * <td>Removed the code duplication.</td> 333 * </tr> 334 * <tr> 335 * <td rowspan="3">3.30</td> 336 * <td>Moved ipcWaitMessageStc structure to the RAM section called ".cy_sharedmem".</td> 337 * <td>Support Secure Boot devices.</td> 338 * </tr> 339 * <tr> 340 * <td>Renamed Function Cy_Flash_StartErase() to Cy_Flash_StartEraseRow().</td> 341 * <td>The driver improvements based on the usability feedback.</td> 342 * </tr> 343 * <tr> 344 * <td>Added new API functions \ref Cy_Flash_EraseSector, 345 * \ref Cy_Flash_StartEraseSector, \ref Cy_Flash_EraseSubsector, 346 * \ref Cy_Flash_StartEraseSubsector </td> 347 * <td>The driver improvements based on the usability feedback.</td> 348 * </tr> 349 * <tr> 350 * <td rowspan="3">3.20</td> 351 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td> 352 * <td>Driver library directory-structure simplification.</td> 353 * </tr> 354 * <tr> 355 * <td>Added new API function \ref Cy_Flash_InitExt</td> 356 * <td>The driver improvements based on the usability feedback</td> 357 * </tr> 358 * <tr> 359 * <td>Added register access layer. Use register access macros instead 360 * of direct register access using dereferenced pointers.</td> 361 * <td>Makes register access device-independent, so that the PDL does 362 * not need to be recompiled for each supported part number.</td> 363 * </tr> 364 * <tr> 365 * <td>3.11</td> 366 * <td>Updated driver functionality to correctly use the SysClk measurement 367 * counters while partially blocking flash operations</td> 368 * <td>Added arbiter mechanism for correct usage of the SysClk measurement 369 * counters</td> 370 * </tr> 371 * <tr> 372 * <td>3.10</td> 373 * <td>Updated Cy_Flash_SendCmd() code to support single core devices.</td> 374 * <td>Support new devices</td> 375 * </tr> 376 * <tr> 377 * <td>3.0</td> 378 * <td>New function - Cy_Flash_ProgramRow();<br> 379 * Updated Cy_Flash_RowChecksum(): changed input parameter to take the 380 * <b>row address</b> (rowAddr) instead of the <b>row number</b> 381 * (rowNum);<br> 382 * Renamed macro for disabling RWW support in driver to 383 * <b>CY_FLASH_RWW_DRV_SUPPORT_DISABLED</b>.<br> 384 * Updated \ref group_flash_configuration documentation section with 385 * flash usage constraints.</td> 386 * <td>Improvements made based on usability feedback to use a common 387 * interface</td> 388 * </tr> 389 * <tr> 390 * <td rowspan="3">2.0</td> 391 * <td>Added non-blocking erase function - Cy_Flash_StartErase(). 392 * Removed the clear cache function call.</td> 393 * <td>The clear cache operation is removed from the blocking Write/Erase 394 * function because in this case it is performed by the hardware. 395 * Otherwise it is documented that it is the user's responsibility to 396 * clear the cache after executing the non-blocking Write/Erase flash 397 * operation.</td> 398 * </tr> 399 * <tr> 400 * <td>Added new Cy_Flash_IsOperationComplete() function to check completeness. 401 * Obsoleted Cy_Flash_IsWriteComplete(), Cy_Flash_IsProgramComplete(), 402 * and Cy_Flash_IsEraseComplete() functions.<br> 403 * Added Cy_Flash_GetExternalStatus() function to get unparsed status where 404 * flash driver will be used in security applications with other modules 405 * as SecureImage.<br> 406 * Added Cy_Flash_Init() function to initialize all needed prerequisites 407 * for Erase/Write operations.</td> 408 * <td>Updated driver design to improve user experience.</td> 409 * </tr> 410 * <tr> 411 * <td>Updated driver implementation to remove MISRA rules deviations.</td> 412 * <td>Driver implementation quality improvement.</td> 413 * </tr> 414 * <tr> 415 * <td>1.0</td> 416 * <td>Initial version</td> 417 * <td></td> 418 * </tr> 419 * </table> 420 * 421 * \defgroup group_flash_macros Macros 422 * \{ 423 * \defgroup group_flash_general_macros Flash general parameters 424 * Provides general information about flash 425 * 426 * \defgroup group_flash_config_macros Flash configuration 427 * Specifies the parameter values passed to SROM API 428 * \} 429 * \defgroup group_flash_functions Functions 430 * \defgroup group_flash_enumerated_types Enumerated Types 431 * \defgroup group_flash_srom_config_structure Structures 432 */ 433 434 #include "cy_device.h" 435 436 #if defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined (CY_IP_MXS40FLASHC) 437 438 #include "cy_ipc_drv.h" 439 #include "cy_syslib.h" 440 #if defined(CY_IP_MXFLASHC_VERSION_ECT) 441 #include "cy_flash_srom.h" 442 #endif 443 444 #if defined(__cplusplus) 445 extern "C" { 446 #endif 447 448 /*************************************** 449 * Macro definitions 450 ***************************************/ 451 /** 452 * \addtogroup group_flash_macros 453 * \{ 454 */ 455 456 /** Driver major version */ 457 #define CY_FLASH_DRV_VERSION_MAJOR 3 458 459 /** Driver minor version */ 460 #define CY_FLASH_DRV_VERSION_MINOR 110 461 462 #define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */ 463 464 #define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */ 465 #define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */ 466 #define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */ 467 468 /** \} group_flash_macros */ 469 470 471 /** 472 * \addtogroup group_flash_general_macros 473 * \{ 474 */ 475 476 #if !defined (CY_IP_MXS40FLASHC) 477 /** Flash row size */ 478 #define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4U) 479 /** Long words flash row size */ 480 #define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)) 481 482 #else 483 /** Flash row size is 512 bytes. When refresh feature is enabled then extra 16 bytes are used to store column 33 related information.*/ 484 #define CY_FLASH_SIZEOF_ROW 512U 485 /** Main NVM region start address */ 486 #define CY_FLASH_MAIN_START_ADDRESS CPUSS_FLASHC_MAIN_START_ADDRESS 487 /** Main NVM region end address */ 488 #define CY_FLASH_MAIN_END_ADDRESS CY_FLASH_MAIN_START_ADDRESS + (0x400UL * 8UL * CPUSS_RRAMC_MAIN_N) /* Main NVM region size in multiples of 8KB */ 489 490 491 #endif /* !defined (CY_IP_MXS40FLASHC) */ 492 493 /** \} group_flash_general_macros */ 494 495 #if defined(CY_IP_MXFLASHC_VERSION_ECT) 496 497 /** \cond INTERNAL */ 498 499 /** Flash bounds */ 500 typedef enum 501 { 502 CY_FLASH_IN_BOUNDS, 503 CY_FLASH_OUT_OF_BOUNDS, 504 } en_flash_bounds_t; 505 506 #define CY_FLASH_NUMBER_ROWS (CPUSS_FLASH_SIZE/CY_FLASH_SIZEOF_ROW) /** Number of flash rows */ 507 508 #define CY_WFLASH_LG_SBM_TOP CY_WFLASH_LG_SBM_BASE 509 #define CY_WFLASH_LG_SBM_END (CY_WFLASH_LG_SBM_BASE + CY_WFLASH_LG_SBM_SIZE) 510 511 #define CY_WFLASH_SM_SBM_TOP CY_WFLASH_SM_SBM_BASE 512 #define CY_WFLASH_SM_SBM_END (CY_WFLASH_SM_SBM_BASE + CY_WFLASH_SM_SBM_SIZE) 513 514 #define CY_WFLASH_LG_DBM0_TOP CY_WFLASH_LG_DBM0_BASE 515 #define CY_WFLASH_LG_DBM0_END (CY_WFLASH_LG_DBM0_BASE + CY_WFLASH_LG_DBM0_SIZE) 516 517 #define CY_WFLASH_SM_DBM0_TOP CY_WFLASH_SM_DBM0_BASE 518 #define CY_WFLASH_SM_DBM0_END (CY_WFLASH_SM_DBM0_BASE + CY_WFLASH_SM_DBM0_SIZE) 519 520 #define CY_WFLASH_LG_DBM1_TOP CY_WFLASH_LG_DBM1_BASE 521 #define CY_WFLASH_LG_DBM1_END (CY_WFLASH_LG_DBM1_BASE + CY_WFLASH_LG_DBM1_SIZE) 522 523 #define CY_WFLASH_SM_DBM1_TOP CY_WFLASH_SM_DBM1_BASE 524 #define CY_WFLASH_SM_DBM1_END (CY_WFLASH_SM_DBM1_BASE + CY_WFLASH_SM_DBM1_SIZE) 525 526 #define CY_FLASH_LG_SBM_TOP CY_FLASH_LG_SBM_BASE 527 #define CY_FLASH_LG_SBM_END (CY_FLASH_LG_SBM_BASE + CY_FLASH_LG_SBM_SIZE) 528 529 #define CY_FLASH_SM_SBM_TOP CY_FLASH_SM_SBM_BASE 530 #define CY_FLASH_SM_SBM_END (CY_FLASH_SM_SBM_BASE + CY_FLASH_SM_SBM_SIZE) 531 532 #define CY_FLASH_LG_DBM0_TOP CY_FLASH_LG_DBM0_BASE 533 #define CY_FLASH_LG_DBM0_END (CY_FLASH_LG_DBM0_BASE + CY_FLASH_LG_DBM0_SIZE) 534 535 #define CY_FLASH_SM_DBM0_TOP CY_FLASH_SM_DBM0_BASE 536 #define CY_FLASH_SM_DBM0_END (CY_FLASH_SM_DBM0_BASE + CY_FLASH_SM_DBM0_SIZE) 537 538 #define CY_FLASH_LG_DBM1_TOP CY_FLASH_LG_DBM1_BASE 539 #define CY_FLASH_LG_DBM1_END (CY_FLASH_LG_DBM1_BASE + CY_FLASH_LG_DBM1_SIZE) 540 541 #define CY_FLASH_SM_DBM1_TOP CY_FLASH_SM_DBM1_BASE 542 #define CY_FLASH_SM_DBM1_END (CY_FLASH_SM_DBM1_BASE + CY_FLASH_SM_DBM1_SIZE) 543 544 #define CY_SFLASH_TOP CY_SFLASH_BASE 545 #define CY_SFLASH_END (CY_SFLASH_BASE + CY_SFLASH_SIZE) 546 547 #define CY_SFLASH1_TOP CY_SFLASH1_BASE 548 #define CY_SFLASH1_END (CY_SFLASH1_BASE + CY_SFLASH1_SIZE) 549 550 #define CY_WORK_LES_SIZE_IN_BYTE (0x00000800UL) 551 #define CY_WORK_LES_SIZE_IN_WORD (0x00000800UL / 4UL) 552 #define CY_WORK_SES_SIZE_IN_BYTE (0x00000080UL) 553 #define CY_WORK_SES_SIZE_IN_WORD (0x00000080UL / 4UL) 554 555 #define CY_CODE_LES_SIZE_IN_BYTE (0x00008000UL) 556 #define CY_CODE_LES_SIZE_IN_WORD (0x00008000UL / 4UL) 557 #define CY_CODE_SES_SIZE_IN_BYTE (0x00002000UL) 558 #define CY_CODE_SES_SIZE_IN_WORD (0x00002000UL / 4UL) 559 560 561 typedef enum 562 { 563 CY_FLASH_MAIN_REGION = 0U, 564 CY_FLASH_WORK_REGION, 565 CY_FLASH_CA_CM0P_REGION 566 } cy_en_region_t; 567 568 /** \endcond */ 569 #endif // (defined(CY_IP_MXFLASHC_VERSION_ECT)) 570 571 572 573 /** 574 * \addtogroup group_flash_enumerated_types 575 * \{ 576 */ 577 578 /** This enum has the return values of the Flash driver */ 579 typedef enum cy_en_flashdrv_status 580 { 581 CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */ 582 CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */ 583 CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */ 584 CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */ 585 CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */ 586 CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */ 587 CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */ 588 CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */ 589 CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error code. See \ref Cy_Flash_GetExternalStatus() */ 590 CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */ 591 CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */ 592 CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL), /**< Flash is under operation */ 593 CY_FLASH_DRV_CHECKSUM_NON_ZERO = ( CY_FLASH_ID_ERROR + 0x4UL), /**< Checksum of FLASH resulted in non-zero (SROM STATUS CODE: 0xF000000A) */ 594 CY_FLASH_DRV_NO_ERASE_SUSPEND = ( CY_FLASH_ID_ERROR + 0x7UL), /**< Returned when EraseResume is called when no sector is suspended from erase (SROM STATUS CODE: 0xF0000092) */ 595 CY_FLASH_DRV_FLASH_NOT_ERASED = ( CY_FLASH_ID_ERROR + 0x8UL), /**< Returned when ProgramRow is invoked on unerased cells or blank check fails (SROM STATUS CODE: 0xF00000A4) */ 596 CY_FLASH_DRV_NO_ERASE_ONGOING = ( CY_FLASH_ID_ERROR + 0x9UL), /**< Returned by EraseSuspend when called with no ongoing erase operation (SROM STATUS CODE: 0xF00000A5) */ 597 CY_FLASH_DRV_ACTIVE_ERASE = ( CY_FLASH_ID_ERROR + 0xAUL), /**< Returned by ProgramRow when active erase operation is going on (SROM STATUS CODE: 0xF00000A6) */ 598 CY_FLASH_DRV_INVALID_DATA_WIDTH = ( CY_FLASH_ID_ERROR + 0xBUL), /**< Returned by ProgramRow API if invalid program width option is provided (SROM STATUS CODE: 0xF00000A8) */ 599 CY_FLASH_DRV_FLASH_SAFTEY_ENABLED = ( CY_FLASH_ID_ERROR + 0xCUL), /**< Returned by FLASH program/erase APIs when writes are disabled in safety register (SROM STATUS CODE: 0xF00000AA) */ 600 CY_FLASH_DRV_INVALID_SFLASH_ADDR = ( CY_FLASH_ID_ERROR + 0xDUL), /**< Returned when WriteRow is called on invalid SFLASH rows in NORMAL state (SROM STATUS CODE: 0xF00000B2) */ 601 CY_FLASH_DRV_SFLASH_BACKUP_ERASED = ( CY_FLASH_ID_ERROR + 0xEUL), /**< Returned by Sflash programming APIs when backup sector is in erased state (SROM STATUS CODE: 0xF00000BB) */ 602 CY_FLASH_DRV_SECTOR_SUSPEND = ( CY_FLASH_ID_ERROR + 0xFUL), /**< Returned when Program operation is called on sector which is suspended from erase (SROM STATUS CODE: 0xF0000091) */ 603 CY_FLASH_DRV_SROM_API_TIMEOUT = ( CY_FLASH_ID_ERROR + 0x10UL), /**< Time out happens after calling srom API driver */ 604 #if defined (CY_IP_MXS40FLASHC) 605 CY_FLASH_DRV_REFRESH_NOT_SUPPORTED = ( CY_FLASH_ID_ERROR + 0x11UL), /**< Refresh on this sector is not supported. */ 606 CY_FLASH_DRV_REFRESH_FAILED = ( CY_FLASH_ID_ERROR + 0x12UL), /**< Refresh Operation failed. */ 607 CY_FLASH_DRV_REFRESH_NOT_ENABLED = ( CY_FLASH_ID_ERROR + 0x13UL), /**< Refresh Feature not enabled. */ 608 CY_FLASH_DRV_INIT_FAILED = ( CY_FLASH_ID_ERROR + 0x14UL), /**< Refresh Feature not enabled. */ 609 #endif /* defined (CY_IP_MXS40FLASHC) */ 610 } cy_en_flashdrv_status_t; 611 612 #if defined (CY_IP_MXS40FLASHC) 613 /** No of errors when ECC error injection is enabled. */ 614 typedef enum 615 { 616 CY_FLASH_ECC_ERRORS_LESS_THAN_TWO = (0x00UL), /**< Number of non-recoverable errors are less than two */ 617 CY_FLASH_ECC_ERRORS_MORE_THAN_ONE = (0x01UL) /**< Number of non-recoverable errors are more than or equal to two */ 618 } cy_en_flash_ecc_inject_errors_t; 619 #endif 620 621 #if (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION >=2)) || defined (CY_IP_M7CPUSS) 622 /** Flash Dual bank mode configuration */ 623 typedef enum 624 { 625 CY_FLASH_SINGLE_BANK_MODE = 0U, /**< Single Bank Mode */ 626 CY_FLASH_DUAL_BANK_MODE = 1U /**< Dual Bank Mode */ 627 } cy_en_bankmode_t; 628 629 /** Flash Dual bank mode Mapping configuration */ 630 typedef enum 631 { 632 CY_FLASH_MAPPING_A = 0U, /**< Mapping A */ 633 CY_FLASH_MAPPING_B = 1U /**< Mapping B */ 634 } cy_en_maptype_t; 635 #endif /* (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION >=2)) || defined (CY_IP_M7CPUSS) */ 636 637 #if defined (CY_IP_MXS40FLASHC) 638 /** Flash Dual bank mode mapping configuration */ 639 typedef enum 640 { 641 CY_FLASH_MAPPING_MAIN_A_WORK_A = (0x00UL), /**< MAIN (Mapping A), WORK (Mapping A). */ 642 CY_FLASH_MAPPING_MAIN_B_WORK_A = (0x01UL), /**< MAIN (Mapping B), WORK (Mapping A). */ 643 CY_FLASH_MAPPING_MAIN_A_WORK_B = (0x10UL), /**< MAIN (Mapping A), WORK (Mapping B). */ 644 CY_FLASH_MAPPING_MAIN_B_WORK_B = (0x11UL) /**< MAIN (Mapping B), WORK (Mapping B). */ 645 } cy_en_flash_dual_bank_mapping_t; 646 #endif /* defined (CY_IP_MXS40FLASHC) */ 647 648 #if !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) 649 /** Flash notification configuration structure */ 650 typedef struct 651 { 652 uint8_t clientID; /**< Client ID */ 653 uint8_t pktType; /**< Message Type */ 654 uint16_t intrRelMask; /**< Mask */ 655 } cy_stc_flash_notify_t; 656 #endif /* !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ 657 658 /** \} group_flash_enumerated_types */ 659 660 #if (defined(CY_IP_MXFLASHC_VERSION_ECT)) 661 662 /** 663 * \addtogroup group_flash_enumerated_types 664 * \{ 665 */ 666 /** Flash Program row data size configuration */ 667 typedef enum 668 { 669 CY_FLASH_PROGRAMROW_DATA_SIZE_8BIT = (0x00UL), /**< Set program row data size 8 bit */ 670 CY_FLASH_PROGRAMROW_DATA_SIZE_16BIT = (0x01UL), /**< Set program row data size 16 bit */ 671 CY_FLASH_PROGRAMROW_DATA_SIZE_32BIT = (0x02UL), /**< Set program row data size 32 bit */ 672 CY_FLASH_PROGRAMROW_DATA_SIZE_64BIT = (0x03UL), /**< Set program row data size 64 bit */ 673 CY_FLASH_PROGRAMROW_DATA_SIZE_128BIT = (0x04UL), /**< Set program row data size 128 bit */ 674 CY_FLASH_PROGRAMROW_DATA_SIZE_256BIT = (0x05UL), /**< Set program row data size 256 bit */ 675 CY_FLASH_PROGRAMROW_DATA_SIZE_512BIT = (0x06UL), /**< Set program row data size 512 bit */ 676 CY_FLASH_PROGRAMROW_DATA_SIZE_1024BIT = (0x07UL), /**< Set program row data size 1024 bit */ 677 CY_FLASH_PROGRAMROW_DATA_SIZE_2048BIT = (0x08UL), /**< Set program row data size 2048 bit */ 678 CY_FLASH_PROGRAMROW_DATA_SIZE_4096BIT = (0x09UL) /**< Set program row data size 4096 bit */ 679 } cy_en_flash_programrow_datasize_t; 680 681 /** Flash Program row function execution type configuration */ 682 typedef enum 683 { 684 CY_FLASH_PROGRAMROW_NON_BLOCKING = (0x00UL), /**< Set program row API in non blocking mode */ 685 CY_FLASH_PROGRAMROW_BLOCKING = (0x01UL) /**< Set program row API in blocking mode */ 686 } cy_en_flash_programrow_blocking_t; 687 688 /** Flash blank check on Program row configuration */ 689 typedef enum 690 { 691 CY_FLASH_PROGRAMROW_BLANK_CHECK = (0x00UL), /**< Performs blank check on Program Row */ 692 CY_FLASH_PROGRAMROW_SKIP_BLANK_CHECK = (0x01UL) /**< Does not perform blank check on Program Row */ 693 } cy_en_flash_programrow_skipblankcheck_t; 694 695 /** Flash Program row data location configuration */ 696 typedef enum 697 { 698 CY_FLASH_PROGRAMROW_DATA_LOCATION_SRAM = (0x01UL) /**< Program Row data location is sram */ 699 } cy_en_flash_programrow_location_t; 700 701 /** Flash Program row interrupt mask configuration */ 702 typedef enum 703 { 704 CY_FLASH_PROGRAMROW_NOT_SET_INTR_MASK = (0x00UL), /**< Program Row API interrupt is not set */ 705 CY_FLASH_PROGRAMROW_SET_INTR_MASK = (0x01UL) /**< Program Row API interrupt is set */ 706 } cy_en_flash_programrow_intrmask_t; 707 708 /** Flash Erase sector function execution type configuration */ 709 typedef enum 710 { 711 CY_FLASH_ERASESECTOR_NON_BLOCKING = (0x00UL), /**< Erase sector API executed in non blocking mode */ 712 CY_FLASH_ERASESECTOR_BLOCKING = (0x01UL) /**< Erase sector API executed in blocking mode */ 713 } cy_en_flash_erasesector_blocking_t; 714 715 /** Flash Erase sector interrupt mask configuration */ 716 typedef enum 717 { 718 CY_FLASH_ERASESECTOR_NOT_SET_INTR_MASK = (0x00UL), /**< Erase sector API interrupt is not set */ 719 CY_FLASH_ERASESECTOR_SET_INTR_MASK = (0x01UL) /**< Erase sector API interrupt is set */ 720 } cy_en_flash_erasesector_intrmask_t; 721 722 /** Flash checksum bank configuration */ 723 typedef enum 724 { 725 CY_FLASH_CHECKSUM_BANK0 = (0x00UL), /**< Checksum calculated for Bank0 */ 726 CY_FLASH_CHECKSUM_BANK1 = (0x01UL) /**< Checksum calculated for Bank1 */ 727 } cy_en_flash_checksum_bank_t; 728 729 /** Flash checksum page configuration */ 730 typedef enum 731 { 732 CY_FLASH_CHECKSUM_PAGE = (0x00UL), /**< Checksum calculated for that page */ 733 CY_FLASH_CHECKSUM_WHOLE = (0x01UL) /**< Checksum calculated for whole region */ 734 } cy_en_flash_checksum_scope_t; 735 736 /** Flash checksum region configuration */ 737 typedef enum 738 { 739 CY_FLASH_CHECKSUM_MAIN = (0x00UL), /**< Checksum calculated for Main flash region */ 740 CY_FLASH_CHECKSUM_WORK = (0x01UL), /**< Checksum calculated for Work flash region */ 741 CY_FLASH_CHECKSUM_SUPERVISORY = (0x02UL) /**< Checksum calculated for Supervisory flash region */ 742 } cy_en_flash_checksum_region_t; 743 744 /** Flash compute hash configuration */ 745 typedef enum 746 { 747 CY_FLASH_COMPUTEHASH_BASIC = (0x00UL), /**< Compute Basic hash */ 748 CY_FLASH_COMPUTEHASH_CRC8 = (0x01UL) /**< Compute CRC8 hash */ 749 } cy_en_flash_computehash_type_t; 750 751 /** Flash Erase resume interrupt mask configuration */ 752 typedef enum 753 { 754 CY_FLASH_ERASERESUME_NOT_SET_INTR_MASK = (0x00UL), /**< Erase resume API interrupt is not set */ 755 CY_FLASH_ERASERESUME_SET_INTR_MASK = (0x01UL) /**< Erase resume API interrupt is set */ 756 } cy_en_flash_eraseresume_setintr_t; 757 758 /** Flash Erase resume function execution type configuration */ 759 typedef enum 760 { 761 CY_FLASH_ERASERESUME_NON_BLOCKING = (0x00UL), /**< Set erase resume API in non blocking mode */ 762 CY_FLASH_ERASERESUME_BLOCKING = (0x01UL) /**< Set erase resume API in blocking mode */ 763 } cy_en_flash_eraseresume_blocking_t; 764 765 /** Flash driver function execution type configuration */ 766 typedef enum 767 { 768 CY_FLASH_DRIVER_NON_BLOCKING = (0x00UL), /**< Set SROM API in non blocking mode */ 769 CY_FLASH_DRIVER_BLOCKING = (0x01UL) /**< Set SROM API in blocking mode */ 770 } cy_en_flash_driver_blocking_t; 771 772 /** \} group_flash_enumerated_types */ 773 #endif // (defined(CY_IP_MXFLASHC_VERSION_ECT)) 774 775 /*************************************** 776 * Data Structure definitions 777 ***************************************/ 778 #if (defined(CY_IP_MXFLASHC_VERSION_ECT)) 779 780 /** 781 * \addtogroup group_flash_srom_config_structure 782 * \{ 783 */ 784 /** Flash program row configuration structure */ 785 typedef struct 786 { 787 const uint32_t* destAddr; /**< Destination address of flash */ 788 const uint32_t* dataAddr; /**< pointer to 32byte aligned source data to be written to the flash */ 789 cy_en_flash_programrow_blocking_t blocking; /**< blocking or non blocking mode. \ref cy_en_flash_programrow_blocking_t */ 790 cy_en_flash_programrow_skipblankcheck_t skipBC; /**< blank check operation \ref cy_en_flash_programrow_skipblankcheck_t */ 791 cy_en_flash_programrow_datasize_t dataSize; /**< size of the data to be written. \ref cy_en_flash_programrow_datasize_t */ 792 cy_en_flash_programrow_location_t dataLoc; /**< data location for the operation \ref cy_en_flash_programrow_location_t */ 793 cy_en_flash_programrow_intrmask_t intrMask; /**< interrupt mask to be set. \ref cy_en_flash_programrow_intrmask_t */ 794 }cy_stc_flash_programrow_config_t; 795 796 /** Flash erase row configuration structure */ 797 typedef struct 798 { 799 const uint32_t* sectorAddr; /**< Sector address to be erased */ 800 cy_en_flash_erasesector_blocking_t blocking; /**< blocking or non blocking mode \ref cy_en_flash_erasesector_blocking_t */ 801 cy_en_flash_erasesector_intrmask_t intrMask; /**< interrupt mask to be set. \ref cy_en_flash_erasesector_intrmask_t */ 802 }cy_stc_flash_erasesector_config_t; 803 804 /** Flash checksum configuration structure */ 805 typedef struct 806 { 807 uint8_t rowId; /**< row id for checksum */ 808 cy_en_flash_checksum_bank_t bank; /**< Checksum calculated for Bank0 or Bank1 \ref cy_en_flash_checksum_bank_t */ 809 cy_en_flash_checksum_scope_t whole; /**< Checksum calculated for whole region or page \ref cy_en_flash_checksum_scope_t */ 810 cy_en_flash_checksum_region_t region; /**< Specifies the configuration of flash operation \ref cy_en_flash_checksum_region_t */ 811 } cy_stc_flash_checksum_config_t; 812 813 /** Flash compute hash configuration structure */ 814 typedef struct 815 { 816 const uint32_t* startAddr; /**< Address for computing hash */ 817 uint32_t numOfByte; /**< Number of Bytes for computing hash */ 818 cy_en_flash_computehash_type_t type; /**< Compute CRC8 hash or basic hash. /ref cy_en_flash_computehash_type_t*/ 819 } cy_stc_flash_computehash_config_t; 820 821 /** Flash erase resume configuration structure */ 822 typedef struct 823 { 824 cy_en_flash_eraseresume_setintr_t intrMask; /**< Interrupt mask for erase resume operation \ref cy_en_flash_eraseresume_setintr_t */ 825 cy_en_flash_eraseresume_blocking_t blocking; /**< Blocking or non blocking mode. \ref cy_en_flash_eraseresume_blocking_t */ 826 } cy_stc_flash_eraseresume_config_t; 827 828 /** Flash blank check configuration structure */ 829 typedef struct 830 { 831 const uint32_t* addrToBeChecked; /**< Address for which blank check to be performed. */ 832 uint32_t numOfWordsToBeChecked; /**< No of words to be checked. */ 833 } cy_stc_flash_blankcheck_config_t; 834 835 /** \} group_flash_srom_config_structure */ 836 837 #endif // (defined(CY_IP_MXFLASHC_VERSION_ECT)) 838 839 840 /*************************************** 841 * Function Prototypes 842 ***************************************/ 843 #if (defined(CY_IP_MXFLASHC_VERSION_ECT)) 844 845 846 /** 847 * \addtogroup group_flash_functions 848 * \{ 849 */ 850 851 852 /******************************************************************************* 853 * Function Name: Cy_Flashc_MainWriteEnable 854 ****************************************************************************//** 855 * 856 * \brief Enable writing to main flash. 857 * Enables writing to main flash. 858 * 859 * \note This function is applicable for CAT1C devices. 860 * 861 * \return none 862 * 863 *******************************************************************************/ 864 void Cy_Flashc_MainWriteEnable(void); 865 866 867 /******************************************************************************* 868 * Function Name: Cy_Flashc_MainWriteDisable 869 ****************************************************************************//** 870 * 871 * \brief Disable writing to main flash 872 * Disables writing to main flash. 873 * 874 * \note This function is applicable for CAT1C devices. 875 * 876 * \return none 877 * 878 *******************************************************************************/ 879 void Cy_Flashc_MainWriteDisable(void); 880 881 882 /******************************************************************************* 883 * Function Name: Cy_Flashc_WorkWriteEnable 884 ****************************************************************************//** 885 * 886 * \brief Enable writing work flash 887 * Work Flash embedded operations are enabled. 888 * 889 * \note This function is applicable for CAT1C devices. 890 * 891 * \return none 892 * 893 *******************************************************************************/ 894 void Cy_Flashc_WorkWriteEnable(void); 895 896 897 /******************************************************************************* 898 * Function Name: Cy_Flashc_WorkWriteDisable 899 ****************************************************************************//** 900 * 901 * \brief Disable writing work flash 902 * Work Flash embedded operations are blocked 903 * 904 * \note This function is applicable for CAT1C devices. 905 * 906 * \return none 907 * 908 *******************************************************************************/ 909 void Cy_Flashc_WorkWriteDisable(void); 910 911 912 /******************************************************************************* 913 * Function Name: Cy_Flashc_WorkECCEnable 914 ****************************************************************************//** 915 * 916 * \brief Enables ECC for work flash 917 * ECC checking/reporting on FLASH work interface is enabled. 918 * Correctable or non-correctable faults are reported by enabling ECC. 919 * 920 * \note This function is applicable for CAT1C devices. 921 * 922 * \return none 923 * 924 *******************************************************************************/ 925 void Cy_Flashc_WorkECCEnable(void); 926 927 /******************************************************************************* 928 * Function Name: Cy_Flashc_WorkECCDisable 929 ****************************************************************************//** 930 * 931 * \brief Disables ECC for work flash 932 * ECC checking/reporting on FLASH work interface is disabled. 933 * No correctable or non-correctable faults are reported by disabling ECC. 934 * 935 * \note This function is applicable for CAT1C devices. 936 * 937 * \return none 938 * 939 *******************************************************************************/ 940 void Cy_Flashc_WorkECCDisable(void); 941 942 943 /******************************************************************************* 944 * Function Name: Cy_Flashc_MainECCEnable 945 ****************************************************************************//** 946 * 947 * \brief Enables ECC for main flash 948 * ECC checking/reporting on FLASH main interface is enabled. 949 * Correctable or non-correctable faults are reported by enabling ECC. 950 * 951 * \note This function is applicable for CAT1C devices. 952 * 953 * \return none 954 * 955 *******************************************************************************/ 956 void Cy_Flashc_MainECCEnable(void); 957 958 /******************************************************************************* 959 * Function Name: Cy_Flashc_MainECCDisable 960 ****************************************************************************//** 961 * 962 * \brief Disables ECC for main flash. 963 * ECC checking/reporting on FLASH main interface is disabled. 964 * No correctable or non-correctable faults are reported by disabling ECC. 965 * 966 * \note This function is applicable for CAT1C devices. 967 * 968 * \return none 969 * 970 *******************************************************************************/ 971 void Cy_Flashc_MainECCDisable(void); 972 973 /******************************************************************************* 974 * Function Name: Cy_Flash_Program_WorkFlash 975 ****************************************************************************//** 976 * 977 * This function writes an array data to work flash. Reports success or 978 * or a reason for failure. User should only pass work flash address else it will return an error. 979 * This function executes in blocking mode only. 980 * 981 * Returns immediately and reports a CY_FLASH_DRV_IPC_BUSY error in the case when another 982 * process is operating flash. User firmware should not enter the hibernate 983 * mode until flash Write is complete. The Flash operation is allowed in Sleep and 984 * Deep-sleep modes. During the Flash operation, the device should not be reset, 985 * including the XRES pin, a software reset, and watchdog reset sources. Also, 986 * low-voltage detect circuits should be configured to generate an interrupt instead 987 * of a reset. Otherwise, portions of flash may undergo unexpected changes. 988 * \note A Read while Write violation occurs when a flash Read operation is initiated 989 * in the same or neighboring flash sector where the flash Write, Erase, or 990 * Program operation is working. This violation may cause a HardFault exception. 991 * To avoid the Read while Write violation, 992 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 993 * 994 * \note This function is applicable for CAT1C devices. 995 * 996 * \note User needs to make sure that the data pointer passed to this function points to 32 byte aligned data. 997 * 998 * \param config configuration of this function. 999 * This parameter is defined by the cy_stc_flash_programrow_config_t 1000 * in \ref group_flash_srom_config_structure macro. 1001 * 1002 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1003 * 1004 * \funcusage 1005 * \snippet flash/snippet/main.c snippet_Cy_Flash_Program_WorkFlash 1006 * 1007 *******************************************************************************/ 1008 cy_en_flashdrv_status_t Cy_Flash_Program_WorkFlash(const cy_stc_flash_programrow_config_t* config); 1009 1010 /******************************************************************************* 1011 * Function Name: Cy_Flash_Program 1012 ****************************************************************************//** 1013 * 1014 * This function writes an array of data to flash. Reports success or 1015 * or a reason for failure. 1016 * Returns immediately and reports a CY_FLASH_DRV_IPC_BUSY error in the case when another 1017 * process is operating flash. User firmware should not enter the hibernate 1018 * mode until flash Write is complete. The Flash operation is allowed in Sleep and 1019 * Deep-sleep modes. During the Flash operation, the device should not be reset, 1020 * including the XRES pin, a software reset, and watchdog reset sources. Also, 1021 * low-voltage detect circuits should be configured to generate an interrupt instead 1022 * of a reset. Otherwise, portions of flash may undergo unexpected changes. 1023 * \note A Read while Write violation occurs when a flash Read operation is initiated 1024 * in the same or neighboring flash sector where the flash Write, Erase, or 1025 * Program operation is working. This violation may cause a HardFault exception. 1026 * To avoid the Read while Write violation, 1027 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1028 * 1029 * \note This function is applicable for CAT1C devices. 1030 * 1031 * \note User needs to make sure that the data pointer passed to this function points to 32 byte aligned data. 1032 * 1033 * \param config configuration of this function. 1034 * This parameter is defined by the cy_stc_flash_programrow_config_t 1035 * in \ref group_flash_srom_config_structure macro. 1036 * 1037 * \param block specifies if the function to execute in blocking or non blocking mode. 1038 * 1039 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1040 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error in non blocking mode. 1041 * returns CY_FLASH_DRV_SUCCESS in blocking mode. 1042 * 1043 * \funcusage 1044 * \snippet flash/snippet/main.c snippet_Cy_Flash_Program 1045 *******************************************************************************/ 1046 cy_en_flashdrv_status_t Cy_Flash_Program(const cy_stc_flash_programrow_config_t* config, cy_en_flash_driver_blocking_t block); 1047 1048 /******************************************************************************* 1049 * Function Name: Cy_Flash_Checksum 1050 ****************************************************************************//** 1051 * 1052 * Returns a checksum value of the specified flash row. supports only blocking 1053 * mode for now. 1054 * 1055 * \note This function is applicable for CAT1C devices. 1056 * 1057 * \param config configuration of this function. 1058 * This parameter is defined by the cy_stc_flash_checksum_config_t 1059 * in \ref cy_stc_flash_checksum_config_t macro. 1060 * 1061 * \param checksumPtr The pointer to the address where checksum is to be stored 1062 * 1063 * \return Returns the status of the Flash operation. 1064 * 1065 * \funcusage 1066 * \snippet flash/snippet/main.c snippet_Cy_Flash_Checksum 1067 *******************************************************************************/ 1068 cy_en_flashdrv_status_t Cy_Flash_Checksum (const cy_stc_flash_checksum_config_t *config, uint32_t* checksumPtr); 1069 1070 /******************************************************************************* 1071 * Function Name: Cy_Flash_EraseSuspend 1072 ****************************************************************************//** 1073 * 1074 * This function suspends an ongoing erase operation. User should not read from a 1075 * sector which is suspended from an erase operation. Cy_Flash_ProgramRow function 1076 * will return error if invoked on suspended sector. 1077 * This function cannot be called on SFLASH. Reports success 1078 * or a reason for failure. Does not return until the Erase operation is complete. 1079 * Returns immediately and reports a CY_FLASH_DRV_IPC_BUSY error in the case when another 1080 * process is operating flash. 1081 * This function supports only blocking mode for now. 1082 * 1083 * \note This function is applicable for CAT1C devices. 1084 * 1085 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1086 * 1087 *******************************************************************************/ 1088 cy_en_flashdrv_status_t Cy_Flash_EraseSuspend(void); 1089 1090 /******************************************************************************* 1091 * Function Name: Cy_Flash_EraseResume 1092 ****************************************************************************//** 1093 * 1094 * This function calls to resume a suspended erase operation. 1095 * Reports success or a reason for failure. 1096 * Returns immediately and reports a CY_FLASH_DRV_IPC_BUSY error in the case when another 1097 * process is operating flash. 1098 * \note A Read while Write violation occurs when a flash Read operation is initiated 1099 * in the same or neighboring flash sector where the flash Write, Erase, or 1100 * Program operation is working. This violation may cause a HardFault exception. 1101 * To avoid the Read while Write violation, 1102 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1103 * 1104 * \note This function is applicable for CAT1C devices. 1105 * 1106 * \param config configuration of this function. 1107 * This parameter is defined by the cy_stc_flash_eraseresume_config_t 1108 * in \ref group_flash_srom_config_structure macro. 1109 * 1110 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1111 * 1112 *******************************************************************************/ 1113 cy_en_flashdrv_status_t Cy_Flash_EraseResume(const cy_stc_flash_eraseresume_config_t *config); 1114 1115 /******************************************************************************* 1116 * Function Name: Cy_Flash_BlankCheck 1117 ****************************************************************************//** 1118 * 1119 * This function performs blank check on the addressed work FLASH. 1120 * Reports success or a reason for failure. 1121 * Returns immediately and reports a CY_FLASH_DRV_IPC_BUSY error in the case when another 1122 * process is operating flash. 1123 * 1124 * \note This function is applicable for CAT1C devices. 1125 * 1126 * \param config configuration of this function. 1127 * This parameter is defined by the cy_stc_flash_blankcheck_config_t 1128 * in \ref group_flash_srom_config_structure macro. 1129 * 1130 * \param block specifies if the function to execute in blocking or non blocking mode. 1131 * 1132 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1133 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error in non blocking mode. 1134 * returns CY_FLASH_DRV_SUCCESS in blocking mode. 1135 * 1136 * \funcusage 1137 * \snippet flash/snippet/main.c snippet_Flashc_test_code 1138 *******************************************************************************/ 1139 cy_en_flashdrv_status_t Cy_Flash_BlankCheck(const cy_stc_flash_blankcheck_config_t *config, cy_en_flash_driver_blocking_t block); 1140 1141 /******************************************************************************* 1142 * Function Name: Cy_Flash_OperationStatus 1143 ****************************************************************************//** 1144 * 1145 * Checks the status of the Flash Operation, and returns it. 1146 * 1147 * \return Driver status. 1148 * returns CY_FLASH_DRV_OPERATION_STARTED if operation in non blocking mode is not complete. 1149 * returns CY_FLASH_DRV_SUCCESS if the operation is complete. 1150 * 1151 * \funcusage 1152 * \snippet flash/snippet/main.c snippet_Flashc_test_code 1153 *******************************************************************************/ 1154 cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void); 1155 1156 /******************************************************************************* 1157 * Function Name: Cy_Flashc_InjectECC 1158 ****************************************************************************//** 1159 * 1160 * This function enables ECC injection and sets the address where a parity will be injected 1161 * and the parity value. 1162 * Reports success or a reason for failure. 1163 * 1164 * \note This function is applicable for CAT1C devices. 1165 * 1166 * \param region An indicator which region (Code/Work/Cache) ECC parity will be injected to. 1167 * This parameter is defined by the cy_en_region_t 1168 * in \ref group_flash_macros macro. 1169 * 1170 * \param address The address where ECC parity will be injected. 1171 * 1172 * \param parity The parity value which will be injected. 1173 * 1174 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1175 * 1176 *******************************************************************************/ 1177 cy_en_flashdrv_status_t Cy_Flashc_InjectECC(cy_en_region_t region, uint32_t address, uint8_t parity); 1178 1179 /******************************************************************************* 1180 * Function Name: Cy_Flashc_InjectECC_Disable 1181 ****************************************************************************//** 1182 * 1183 * This function disables ECC injection for the region specified. 1184 * 1185 * \param region : ECC injection is disabled for this region (Code/Work/Cache). 1186 * This parameter is defined by the cy_en_region_t 1187 * in \ref group_flash_macros macro. 1188 * 1189 * \note This function is applicable for CAT1C devices. 1190 *******************************************************************************/ 1191 void Cy_Flashc_InjectECC_Disable(cy_en_region_t region); 1192 1193 /** \} group_flash_functions */ 1194 1195 #endif 1196 1197 #if ((!defined(CY_IP_MXFLASHC_VERSION_ECT)) || defined(CY_DOXYGEN)) 1198 1199 /** 1200 * \addtogroup group_flash_functions 1201 * \{ 1202 */ 1203 1204 /******************************************************************************* 1205 * Function Name: Cy_Flash_EraseRow 1206 ****************************************************************************//** 1207 * 1208 * This function erases a single row of flash. Reports success or 1209 * a reason for failure. Does not return until the Write operation is 1210 * complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in 1211 * the case when another process is writing to flash or erasing the row. 1212 * User firmware should not enter the Hibernate or Deep Sleep mode until flash Erase 1213 * is complete. The Flash operation is allowed in Sleep mode. 1214 * During the Flash operation, the device should not be reset, including the 1215 * XRES pin, a software reset, and watchdog reset sources. Also, low-voltage 1216 * detect circuits should be configured to generate an interrupt instead of a 1217 * reset. Otherwise, portions of flash may undergo unexpected changes. 1218 * \note A Read while Write violation occurs when a flash Read operation is initiated 1219 * in the same or neighboring flash sector where the flash Write, Erase, ors 1220 * Program operation is working. This violation may cause a HardFault exception. 1221 * To avoid the Read while Write violation, 1222 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1223 * \note This function is applicable for CAT1A and CAT1B devices. 1224 * \note CAT1B devices doesn't use IPC for any flash operations. 1225 * 1226 * \param rowAddr Address of the flash row number. 1227 * The Read-while-Write violation occurs when the flash read operation is 1228 * initiated in the same flash sector where the flash write operation is 1229 * performing. Refer to the device datasheet for the details. 1230 * Address must match row start address. 1231 * 1232 * \note In CAT1B devices with flash IP CY_IP_MXS40FLASHC 1233 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 1234 * User need to make sure that this data is not corrupted while writing and erasing the row data. 1235 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 1236 * 1237 * \return Returns the status of the Flash operation, 1238 * see \ref cy_en_flashdrv_status_t. 1239 * 1240 *******************************************************************************/ 1241 cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr); 1242 1243 /******************************************************************************* 1244 * Function Name: Cy_Flash_StartEraseRow 1245 ****************************************************************************//** 1246 * 1247 * Starts erasing a single row of flash. Returns immediately 1248 * and reports a successful start or reason for failure. 1249 * Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked 1250 * by another process. User firmware should not enter the Hibernate or Deep Sleep mode until 1251 * flash Erase is complete. The Flash operation is allowed in Sleep mode. 1252 * During the flash operation, the device should not be reset, including the 1253 * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage 1254 * detect circuits should be configured to generate an interrupt instead of a reset. 1255 * Otherwise, portions of flash may undergo unexpected changes. 1256 * \note To avoid situation of reading data from cache memory - before 1257 * reading data from previously programmed/erased flash rows, the user must 1258 * clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() 1259 * function. 1260 * \note A Read while Write violation occurs when a flash Read operation is initiated 1261 * in the same or neighboring flash sector where the flash Write, Erase, or 1262 * Program operation is working. This violation may cause a HardFault exception. 1263 * To avoid the Read while Write violation, 1264 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1265 * \note This function is applicable for CAT1A and CAT1B devices. 1266 * \note CAT1B devices doesn't use IPC for any flash operations. 1267 * 1268 * \param rowAddr Address of the flash row number. 1269 * The Read-while-Write violation occurs when the flash read operation is 1270 * initiated in the same flash sector where the flash erase operation is 1271 * performing. Refer to the device datasheet for the details. 1272 * Address must match row start address. 1273 * 1274 * \note In CAT1B devices with flash IP CY_IP_MXS40FLASHC 1275 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 1276 * User need to make sure that this data is not corrupted while writing and erasing the row data. 1277 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 1278 * 1279 * \return Returns the status of the Flash operation, 1280 * see \ref cy_en_flashdrv_status_t. 1281 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error. 1282 * 1283 *******************************************************************************/ 1284 cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr); 1285 1286 #if !defined(CY_IP_MXS40FLASHC) || defined(CY_DOXYGEN) 1287 /******************************************************************************* 1288 * Function Name: Cy_Flash_EraseSubsector 1289 ****************************************************************************//** 1290 * 1291 * This function erases an 8-row subsector of flash. Reports success or 1292 * a reason for failure. Does not return until the Write operation is 1293 * complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in 1294 * the case when another process is writing to flash or erasing the row. 1295 * User firmware should not enter the Hibernate or Deep-Sleep mode until flash Erase 1296 * is complete. The Flash operation is allowed in Sleep mode. 1297 * During the Flash operation, the device should not be reset, including the 1298 * XRES pin, a software reset, and watchdog reset sources. Also, low-voltage 1299 * detect circuits should be configured to generate an interrupt instead of a 1300 * reset. Otherwise, portions of flash may undergo unexpected changes. 1301 ** \note A Read while Write violation occurs when a flash Read operation is initiated 1302 * in the same or neighboring flash sector where the flash Write, Erase, or 1303 * Program operation is working. This violation may cause a HardFault exception. 1304 * To avoid the Read while Write violation, 1305 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1306 * \note This function is applicable for CAT1A and CAT1B devices. 1307 * \note CAT1B devices doesn't use IPC for any flash operations. 1308 * 1309 * \param subSectorAddr Address of the flash row number. 1310 * The Read-while-Write violation occurs when the flash read operation is 1311 * initiated in the same flash sector where the flash write operation is 1312 * performing. Refer to the device datasheet for the details. 1313 * Address must match row start address. 1314 * 1315 * \return Returns the status of the Flash operation, 1316 * see \ref cy_en_flashdrv_status_t. 1317 * 1318 *******************************************************************************/ 1319 cy_en_flashdrv_status_t Cy_Flash_EraseSubsector(uint32_t subSectorAddr); 1320 1321 /******************************************************************************* 1322 * Function Name: Cy_Flash_StartEraseSubsector 1323 ****************************************************************************//** 1324 * 1325 * Starts erasing an 8-row subsector of flash. Returns immediately 1326 * and reports a successful start or reason for failure. 1327 * Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked 1328 * by another process. User firmware should not enter the Hibernate or Deep-Sleep mode until 1329 * flash Erase is complete. The Flash operation is allowed in Sleep mode. 1330 * During the flash operation, the device should not be reset, including the 1331 * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage 1332 * detect circuits should be configured to generate an interrupt instead of a reset. 1333 * Otherwise, portions of flash may undergo unexpected changes. 1334 * \note Before reading data from previously programmed/erased flash rows, the 1335 * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() 1336 * function. 1337 * \note A Read while Write violation occurs when a flash Read operation is initiated 1338 * in the same or neighboring flash sector where the flash Write, Erase, or 1339 * Program operation is working. This violation may cause a HardFault exception. 1340 * To avoid the Read while Write violation, 1341 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1342 * \note This function is applicable for CAT1A devices. 1343 * 1344 * \param subSectorAddr Address of the flash row number. 1345 * The Read-while-Write violation occurs when the flash read operation is 1346 * initiated in the same flash sector where the flash erase operation is 1347 * performing. Refer to the device datasheet for the details. 1348 * Address must match row start address. 1349 * 1350 * \return Returns the status of the Flash operation, 1351 * see \ref cy_en_flashdrv_status_t. 1352 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error. 1353 * 1354 *******************************************************************************/ 1355 cy_en_flashdrv_status_t Cy_Flash_StartEraseSubsector(uint32_t subSectorAddr); 1356 1357 #endif /* !defined (CY_IP_MXS40FLASHC) */ 1358 1359 /******************************************************************************* 1360 * Function Name: Cy_Flash_WriteRow 1361 ****************************************************************************//** 1362 * 1363 * This function writes an array of data to a single row of flash. This is done 1364 * in three steps - pre-program, erase and then program flash row with the input 1365 * data. Reports success or a reason for failure. Does not return until the Write 1366 * operation is complete. 1367 * Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case 1368 * when another process is writing to flash. User firmware should not enter the 1369 * Hibernate or Deep-sleep mode until flash Write is complete. The Flash operation 1370 * is allowed in Sleep mode. During the Flash operation, the 1371 * device should not be reset, including the XRES pin, a software 1372 * reset, and watchdog reset sources. Also, low-voltage detect 1373 * circuits should be configured to generate an interrupt 1374 * instead of a reset. Otherwise, portions of flash may undergo 1375 * unexpected changes. 1376 * \note A Read while Write violation occurs when a flash Read operation is initiated 1377 * in the same or neighboring flash sector where the flash Write, Erase, or 1378 * Program operation is working. This violation may cause a HardFault exception. 1379 * To avoid the Read while Write violation, 1380 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1381 * 1382 * \note This is a blocking function and will not return until the Write operation is complete. 1383 * \note This function is applicable for CAT1A and CAT1B devices. 1384 * \note CAT1B devices doesn't use IPC for any flash operations. 1385 * 1386 * \param rowAddr Address of the flash row number. 1387 * The Read-while-Write violation occurs when the flash read operation is 1388 * initiated in the same flash sector where the flash write operation is 1389 * performing. Refer to the device datasheet for the details. 1390 * Address must match row start address. 1391 * 1392 * \param data The pointer to the data which has to be written to flash. The size 1393 * of the data array must be equal to the flash row size. The flash row size for 1394 * the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to 1395 * the device datasheet for the details. 1396 * 1397 * \note In CAT1B devices with flash IP CY_IP_MXS40FLASHC 1398 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 1399 * User need to make sure that this data is not corrupted while writing and erasing the row data. 1400 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 1401 * 1402 * \return Returns the status of the Flash operation, 1403 * see \ref cy_en_flashdrv_status_t. 1404 * 1405 *******************************************************************************/ 1406 cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data); 1407 1408 /******************************************************************************* 1409 * Function Name: Cy_Flash_StartProgram 1410 ****************************************************************************//** 1411 * 1412 * Starts writing an array of data to a single row of flash. Returns immediately 1413 * and reports a successful start or reason for failure. 1414 * Reports a \ref CY_FLASH_DRV_IPC_BUSY error if another process is writing 1415 * to flash. The user firmware should not enter Hibernate or Deep-Sleep mode until flash 1416 * Program is complete. The Flash operation is allowed in Sleep mode. 1417 * During the Flash operation, the device should not be reset, including the 1418 * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage 1419 * detect circuits should be configured to generate an interrupt instead of a reset. 1420 * Otherwise, portions of flash may undergo unexpected changes.\n 1421 * Before calling this function, the target flash region must be erased by 1422 * the StartEraseRow/EraseRow function.\n 1423 * Data to be programmed must be located in the SRAM memory region. 1424 * \note Before reading data from previously programmed/erased flash rows, the 1425 * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() 1426 * function. 1427 * \note A Read while Write violation occurs when a flash Read operation is initiated 1428 * in the same or neighboring flash sector where the flash Write, Erase, or 1429 * Program operation is working. This violation may cause a HardFault exception. 1430 * To avoid the Read while Write violation, 1431 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1432 * 1433 * \note This is a non blocking function and will not wait until the Write operation is complete. 1434 * \note This function is applicable for CAT1A and CAT1B devices. 1435 * \note CAT1B devices doesn't use IPC for any flash operations. 1436 * 1437 * \param rowAddr The address of the flash row number. 1438 * The Read-while-Write violation occurs when the Flash Write operation is 1439 * performing. Refer to the device datasheet for the details. 1440 * The address must match the row start address. 1441 * 1442 * \param data The pointer to the data to be written to flash. The size 1443 * of the data array must be equal to the flash row size. The flash row size for 1444 * the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to 1445 * the device datasheet for the details. 1446 * 1447 * \note In CAT1B devices with flash IP CY_IP_MXS40FLASHC 1448 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 1449 * User need to make sure that this data is not corrupted while writing and erasing the row data. 1450 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 1451 * 1452 * \return Returns the status of the Flash operation, 1453 * see \ref cy_en_flashdrv_status_t. 1454 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error. 1455 * 1456 *******************************************************************************/ 1457 cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data); 1458 1459 1460 /******************************************************************************* 1461 * Function Name: Cy_Flash_GetExternalStatus 1462 ****************************************************************************//** 1463 * 1464 * This function handles the case where a module such as security image captures 1465 * a system call from this driver and reports its own status or error code, 1466 * for example protection violation. In that case, a function from this 1467 * driver returns an unknown error (see cy_en_flashdrv_status_t). After receipt 1468 * of an unknown error, the user may call this function to get the status 1469 * of the capturing module. 1470 * 1471 * The user is responsible for parsing the content of the returned value 1472 * and casting it to the appropriate enumeration. 1473 * \note This function is applicable for CAT1A devices. 1474 * 1475 * \return Returns the status of the Flash operation code. 1476 *******************************************************************************/ 1477 uint32_t Cy_Flash_GetExternalStatus(void); 1478 1479 1480 #if ((!defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) && !defined (CY_IP_MXS40FLASHC)) || defined(CY_DOXYGEN)) 1481 /******************************************************************************* 1482 * Function Name: Cy_Flash_InitExt 1483 ****************************************************************************//** 1484 * 1485 * Initiates all needed prerequisites to support flash erase/write. 1486 * Should be called from each core. Defines the address of the message structure. 1487 * 1488 * Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and 1489 * Cy_IPC_Pipe_Init() functions before use. 1490 * 1491 * \note This function is applicable for CAT1A devices. 1492 * 1493 * This function is called in the Cy_Flash_Init() function - see the 1494 * \ref Cy_Flash_Init usage considerations. 1495 * 1496 *******************************************************************************/ 1497 void Cy_Flash_InitExt(cy_stc_flash_notify_t *ipcWaitMessageAddr); 1498 #endif /* !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) && !defined (CY_IP_MXS40FLASHC) */ 1499 1500 /** \} group_flash_functions */ 1501 1502 /** \cond INTERNAL */ 1503 #if (CY_CPU_CORTEX_M4) 1504 void Cy_Flash_ResumeIrqHandler(void); 1505 #endif 1506 1507 /******************************************************************************* 1508 Backward compatibility macro. The following code is DEPRECATED and must 1509 not be used in new projects 1510 *******************************************************************************/ 1511 #define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW) 1512 #define Cy_Flash_StartErase Cy_Flash_StartEraseRow 1513 1514 /** \endcond */ 1515 1516 1517 #endif //(defined(CY_IP_MXFLASHC_VERSION_ECT) || defined(CY_DOXYGEN)) 1518 1519 /** 1520 * \addtogroup group_flash_functions 1521 * \{ 1522 */ 1523 #if (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION >=2)) || defined (CY_IP_M7CPUSS) 1524 /******************************************************************************* 1525 * Function Name: Cy_Flashc_SetWorkBankMode 1526 ****************************************************************************//** 1527 * 1528 * \brief Sets bank mode for work flash 1529 * \note This function is applicable for CAT1C devices. 1530 * 1531 * 1532 * \param mode bank mode to be set 1533 * 1534 * \return none 1535 * 1536 * \funcusage 1537 * \snippet flash/snippet/main.c snippet_Cy_Flashc_WorkBankMode 1538 *******************************************************************************/ 1539 void Cy_Flashc_SetWorkBankMode(cy_en_bankmode_t mode); 1540 1541 /******************************************************************************* 1542 * Function Name: Cy_Flashc_GetWorkBankMode 1543 ****************************************************************************//** 1544 * 1545 * \brief Gets current bank mode for work flash 1546 * \note This function is applicable for CAT1C devices. 1547 * 1548 * 1549 * \return Current bank mode 1550 * 1551 * \funcusage 1552 * \snippet flash/snippet/main.c snippet_Cy_Flashc_WorkBankMode 1553 *******************************************************************************/ 1554 cy_en_bankmode_t Cy_Flashc_GetWorkBankMode(void); 1555 1556 /******************************************************************************* 1557 * Function Name: Cy_Flashc_SetMainBankMode 1558 ****************************************************************************//** 1559 * 1560 * \brief Sets bank mode for main flash 1561 * 1562 * \param mode bank mode to be set 1563 * 1564 * \return 1565 * 1566 * \funcusage 1567 * \snippet flash/snippet/main.c snippet_Cy_Flashc_MainBankMode 1568 *******************************************************************************/ 1569 void Cy_Flashc_SetMainBankMode(cy_en_bankmode_t mode); 1570 1571 /******************************************************************************* 1572 * Function Name: Cy_Flashc_GetMainBankMode 1573 ****************************************************************************//** 1574 * 1575 * \brief Gets current bank mode for main flash 1576 * \note This function is applicable for CAT1C devices. 1577 * 1578 * 1579 * \return Current bank mode 1580 * 1581 * \funcusage 1582 * \snippet flash/snippet/main.c snippet_Cy_Flashc_MainBankMode 1583 *******************************************************************************/ 1584 cy_en_bankmode_t Cy_Flashc_GetMainBankMode(void); 1585 1586 /******************************************************************************* 1587 * Function Name: Cy_Flashc_SetMain_Flash_Mapping 1588 ****************************************************************************//** 1589 * 1590 * \brief Sets mapping for main flash region. Applicable only in Dual Bank mode of Main flash region 1591 * 1592 * \param mapping mapping to be set 1593 * 1594 * \return none 1595 *******************************************************************************/ 1596 void Cy_Flashc_SetMain_Flash_Mapping(cy_en_maptype_t mapping); 1597 1598 /******************************************************************************* 1599 * Function Name: Cy_Flashc_SetWork_Flash_Mapping 1600 ****************************************************************************//** 1601 * 1602 * \brief Sets mapping for work flash region. Applicable only in Dual Bank mode of Work flash region 1603 * 1604 * \param mapping mapping to be set 1605 * 1606 * \return none 1607 *******************************************************************************/ 1608 void Cy_Flashc_SetWork_Flash_Mapping(cy_en_maptype_t mapping); 1609 1610 1611 #endif /* (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION >=2)) || defined (CY_IP_M7CPUSS) */ 1612 1613 /** \} group_flash_functions */ 1614 1615 /** 1616 * \addtogroup group_flash_functions 1617 * \{ 1618 */ 1619 1620 /******************************************************************************* 1621 * Function Name: Cy_Flash_IsOperationComplete 1622 ****************************************************************************//** 1623 * 1624 * Reports a successful operation result, reason of failure or busy status 1625 * ( \ref CY_FLASH_DRV_OPCODE_BUSY ). 1626 * 1627 * \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). 1628 * returns CY_FLASH_DRV_OPERATION_STARTED if operation in non blocking mode is not complete. 1629 * returns CY_FLASH_DRV_SUCCESS if the operation is complete. 1630 * 1631 *******************************************************************************/ 1632 cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void); 1633 1634 1635 /******************************************************************************* 1636 * Function Name: Cy_Flash_StartWrite 1637 ****************************************************************************//** 1638 * 1639 * Starts programming the flash row with 1640 * the input data. Returns immediately and reports a successful start 1641 * or reason for failure. Reports a \ref CY_FLASH_DRV_IPC_BUSY error 1642 * in the case when another process is writing to flash. User 1643 * firmware should not enter the Hibernate or Deep-Sleep mode until 1644 * flash Write is complete. The Flash operation is allowed in Sleep mode. 1645 * During the flash operation, the device should not be reset, including the 1646 * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage 1647 * detect circuits should be configured to generate an interrupt instead of a reset. 1648 * Otherwise, portions of flash may undergo unexpected changes. 1649 * \note Before reading data from previously programmed/erased flash rows, the 1650 * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() 1651 * function. 1652 * \note This is added as backword compatibility function in CAT1C devices. 1653 * This function will not erase the row before writing to the row. Erase ROW is not supported in CAT1C devices. 1654 * User can use \ref Cy_Flash_EraseSector or Cy_Flash_EraseAll functions. 1655 * \note A Read while Write violation occurs when a flash Read operation is initiated 1656 * in the same or neighboring flash sector where the flash Write, Erase, or 1657 * Program operation is working. This violation may cause a HardFault exception. 1658 * To avoid the Read while Write violation, 1659 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1660 * 1661 * \note This is a non blocking function and will not wait until the Write operation is complete. 1662 * 1663 * \note User needs to make sure that the data pointer passed to this function points to 32 byte aligned data for CAT1C devices. 1664 * 1665 * \param rowAddr Address of the flash row number. 1666 * The Read-while-Write violation occurs when the flash read operation is 1667 * initiated in the same flash sector where the flash write operation is 1668 * performing. Refer to the device datasheet for the details. 1669 * Address must match row start address. 1670 * 1671 * \param data The pointer to the data to be written to flash. The size 1672 * of the data array must be equal to the flash row size. The flash row size for 1673 * the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to 1674 * the device datasheet for the details. 1675 * For CAT1C devices this data pointer needs to point to 32 byte aligned data. 1676 * 1677 * \note In CAT1B devices with flash IP CY_IP_MXS40FLASHC 1678 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 1679 * User need to make sure that this data is not corrupted while writing and erasing the row data. 1680 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 1681 * 1682 * \return Returns the status of the Flash operation, 1683 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error. 1684 * see \ref cy_en_flashdrv_status_t. 1685 * 1686 *******************************************************************************/ 1687 cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data); 1688 1689 #if !defined(CY_IP_MXS40FLASHC) || defined(CY_DOXYGEN) 1690 /******************************************************************************* 1691 * Function Name: Cy_Flash_StartEraseSector 1692 ****************************************************************************//** 1693 * 1694 * Starts erasing a sector of flash. Returns immediately 1695 * and reports a successful start or reason for failure. 1696 * Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked 1697 * by another process. User firmware should not enter the Hibernate or Deep Sleep mode until 1698 * flash Erase is complete. The Flash operation is allowed in Sleep mode. 1699 * During the flash operation, the device should not be reset, including the 1700 * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage 1701 * detect circuits should be configured to generate an interrupt instead of a reset. 1702 * Otherwise, portions of flash may undergo unexpected changes. 1703 * \note Before reading data from previously programmed/erased flash rows, the 1704 * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() 1705 * function. 1706 * \note A Read while Write violation occurs when a flash Read operation is initiated 1707 * in the same or neighboring flash sector where the flash Write, Erase, or 1708 * Program operation is working. This violation may cause a HardFault exception. 1709 * To avoid the Read while Write violation, 1710 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1711 * 1712 * \note This is a non blocking function and will not wait until the operation is complete. 1713 * 1714 * \param sectorAddr Address of the flash row number. 1715 * The Read-while-Write violation occurs when the flash read operation is 1716 * initiated in the same flash sector where the flash erase operation is 1717 * performing. Refer to the device datasheet for the details. 1718 * Address must match row start address. 1719 * 1720 * \return Returns the status of the Flash operation, 1721 * returns CY_FLASH_DRV_OPERATION_STARTED if operation starts with out error. 1722 * see \ref cy_en_flashdrv_status_t. 1723 * 1724 *******************************************************************************/ 1725 cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr); 1726 1727 #endif /* !defined (CY_IP_MXS40FLASHC) */ 1728 1729 /******************************************************************************* 1730 * Function Name: Cy_Flash_ProgramRow 1731 ****************************************************************************//** 1732 * 1733 * This function writes an array of data to a single row of flash. Reports 1734 * success or a reason for failure. Does not return until the Program operation 1735 * is complete. 1736 * Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case 1737 * when another process is writing to flash. User firmware should not enter the 1738 * Hibernate or Deep-sleep mode until flash Write is complete. The Flash operation 1739 * is allowed in Sleep mode. During the Flash operation, the device should not be 1740 * reset, including the XRES pin, a software reset, and watchdog reset sources. 1741 * Also, low-voltage detect circuits should be configured to generate an interrupt 1742 * instead of a reset. Otherwise, portions of flash may undergo unexpected 1743 * changes.\n 1744 * Before calling this function, the target flash region must be erased by 1745 * the StartErase/EraseRow function.\n 1746 * Data to be programmed must be located in the SRAM memory region. 1747 * \note Before reading data from previously programmed/erased flash rows, the 1748 * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() 1749 * function. 1750 * \note A Read while Write violation occurs when a flash Read operation is initiated 1751 * in the same or neighboring flash sector where the flash Write, Erase, or 1752 * Program operation is working. This violation may cause a HardFault exception. 1753 * To avoid the Read while Write violation, 1754 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1755 * 1756 * \note This is a blocking function and will not return until the Write operation is complete. 1757 * 1758 * \note User needs to make sure that the data pointer passed to this function points to 32 byte aligned data for CAT1C devices. 1759 * 1760 * \param rowAddr Address of the flash row number. 1761 * The Read-while-Write violation occurs when the flash read operation is 1762 * initiated in the same flash sector where the flash write operation is 1763 * performing. Refer to the device datasheet for the details. 1764 * Address must match row start address. 1765 * 1766 * \param data The pointer to the data which has to be written to flash. The size 1767 * of the data array must be equal to the flash row size. The flash row size for 1768 * the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to 1769 * the device datasheet for the details. 1770 * For CAT1C devices this data pointer needs to point to 32 byte aligned data. 1771 * 1772 * \note In CAT1B devices with flash IP CY_IP_MXS40FLASHC 1773 * When refresh is enabled, for each row an extra 16 bytes is used for storing refresh related data. 1774 * User need to make sure that this data is not corrupted while writing and erasing the row data. 1775 * When refresh is enabled row size has to be considered as CY_FLASH_SIZEOF_ROW + 16Bytes 1776 * 1777 * \return Returns the status of the Flash operation, 1778 * see \ref cy_en_flashdrv_status_t. 1779 * 1780 *******************************************************************************/ 1781 cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data); 1782 #if !defined(CY_IP_MXS40FLASHC) || defined(CY_DOXYGEN) 1783 /******************************************************************************* 1784 * Function Name: Cy_Flash_EraseSector 1785 ****************************************************************************//** 1786 * 1787 * This function erases a sector of flash. Reports success or 1788 * a reason for failure. Does not return until the Erase operation is 1789 * complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in 1790 * the case when another process is writing to flash or erasing the row. 1791 * User firmware should not enter the Hibernate or Deep Sleep mode until flash Erase 1792 * is complete. The Flash operation is allowed in Sleep mode. 1793 * During the Flash operation, the device should not be reset, including the 1794 * XRES pin, a software reset, and watchdog reset sources. Also, low-voltage 1795 * detect circuits should be configured to generate an interrupt instead of a 1796 * reset. Otherwise, portions of flash may undergo unexpected changes. 1797 * 1798 * \note A Read while Write violation occurs when a flash Read operation is initiated 1799 * in the same or neighboring flash sector where the flash Write, Erase, or 1800 * Program operation is working. This violation may cause a HardFault exception. 1801 * To avoid the Read while Write violation, 1802 * use Cy_Flash_IsOperationComplete() to ensure flash operation is complete. 1803 * 1804 * \note This is a blocking function and will not return until the erase operation is complete. 1805 * 1806 * \param sectorAddr Address of the flash row number. 1807 * The Read-while-Write violation occurs when the flash read operation is 1808 * initiated in the same flash sector where the flash write operation is 1809 * performing. Refer to the device datasheet for the details. 1810 * Address must match row start address. 1811 * 1812 * \return Returns the status of the Flash operation, 1813 * see \ref cy_en_flashdrv_status_t. 1814 * 1815 *******************************************************************************/ 1816 cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr); 1817 #endif /* !defined (CY_IP_MXS40FLASHC) */ 1818 1819 /******************************************************************************* 1820 * Function Name: Cy_Flash_CalculateHash 1821 ****************************************************************************//** 1822 * 1823 * Returns a hash value of the specified region of flash. 1824 * 1825 * \param data Start the data address. 1826 * 1827 * \param numberOfBytes The hash value is calculated for the number of bytes after the 1828 * start data address (0 - 1 byte, 1- 2 bytes etc). 1829 * 1830 * \param hashPtr The pointer to the address where hash is to be stored 1831 * 1832 * \return Returns the status of the Flash operation. 1833 * 1834 *******************************************************************************/ 1835 cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr); 1836 1837 /******************************************************************************* 1838 * Function Name: Cy_Flash_RowChecksum 1839 ****************************************************************************//** 1840 * 1841 * Returns a checksum value of the specified flash row. 1842 * 1843 * \note Now Cy_Flash_RowChecksum() requires the row <b>address</b> (rowAddr) 1844 * as a parameter. In previous versions of the driver, this function used 1845 * the row <b>number</b> (rowNum) for this parameter. 1846 * 1847 * \param rowAddr The address of the flash row. 1848 * 1849 * \param checksumPtr The pointer to the address where checksum is to be stored 1850 * 1851 * \return Returns the status of the Flash operation. 1852 * 1853 *******************************************************************************/ 1854 cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowAddr, uint32_t* checksumPtr); 1855 1856 #if !defined(CY_IP_MXS40FLASHC) || defined(CY_DOXYGEN) 1857 /******************************************************************************* 1858 * Function Name: Cy_Flash_Init 1859 ****************************************************************************//** 1860 * 1861 * Initiates all needed prerequisites to support flash erase/write. 1862 * Should be called from each core. 1863 * 1864 * Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and 1865 * Cy_IPC_Pipe_Init() functions before use for CAT1A devices. 1866 * 1867 * This function is called in the SystemInit() function, for proper flash write 1868 * and erase operations. If the default startup file is not used, or the function 1869 * SystemInit() is not called in your project, ensure to perform the following steps 1870 * before any flash or EmEEPROM write/erase operations: 1871 * \snippet flash/snippet/main.c Flash Initialization 1872 * 1873 *******************************************************************************/ 1874 void Cy_Flash_Init(void); 1875 1876 #else 1877 /******************************************************************************* 1878 * Function Name: Cy_Flash_Init 1879 ****************************************************************************//** 1880 * 1881 * Initiates all needed prerequisites to support flash erase/write. 1882 * Should be once before starting any flash operations. 1883 * 1884 * \param refresh_enable enable disable refresh feature 1885 * 1886 * \return success if Init is complete else will return err 1887 * 1888 *******************************************************************************/ 1889 cy_en_flashdrv_status_t Cy_Flash_Init(bool refresh_enable); 1890 1891 /******************************************************************************* 1892 * Function Name: Cy_Flash_Refresh 1893 ****************************************************************************//** 1894 * 1895 * Refreshes the flash rows which were not updated by the user code. This is a blocking call. 1896 * If there are only limited number of flash row writes for each flash sector then 1897 * the flash rows in this flash sector (which were not updated during this number of row writes) start to wear out. 1898 * This refresh feature will prevent the flash sector from wear out 1899 * This is not allowed on sector which has SFLASH 1900 * 1901 * \param address of the row that needs to be refreshed. 1902 * 1903 * \return success if refresh is complete. Else will return error 1904 * 1905 * 1906 *******************************************************************************/ 1907 cy_en_flashdrv_status_t Cy_Flash_Refresh(uint32_t flashAddr); 1908 1909 /******************************************************************************* 1910 * Function Name: Cy_Flash_Refresh_Start 1911 ****************************************************************************//** 1912 * 1913 * Refreshes the flash rows which were not updated by the user code. This is a non-blocking call. 1914 * If there are only limited number of flash row writes for each flash sector then 1915 * the flash rows in this flash sector (which were not updated during this number of row writes) start to wear out. 1916 * This refresh feature will prevent the flash sector from wear out 1917 * This is not allowed on sector which has SFLASH 1918 * 1919 * \param address of the row that needs to be refreshed. 1920 * 1921 * \return success if refresh is started. Else will return error 1922 * 1923 * 1924 *******************************************************************************/ 1925 cy_en_flashdrv_status_t Cy_Flash_Refresh_Start(uint32_t flashAddr); 1926 1927 /******************************************************************************* 1928 * Function Name: Cy_Flash_Is_Refresh_Required 1929 ******************************************************************************** 1930 * Checks whether a flash refresh is needed for a sector. 1931 1932 * \returns 1933 * - TRUE, if a refresh is needed. 1934 * - FALSE, if a refresh is not needed. 1935 *******************************************************************************/ 1936 bool Cy_Flash_Is_Refresh_Required(void); 1937 1938 /******************************************************************************* 1939 * Function Name: Cy_Flashc_ECCEnable 1940 ****************************************************************************//** 1941 * 1942 * \brief Enables ECC for flash 1943 * ECC checking/reporting on FLASH interface is enabled. 1944 * Correctable or non-correctable faults are reported by enabling ECC. 1945 * 1946 * \return none 1947 * 1948 *******************************************************************************/ 1949 void Cy_Flashc_ECCEnable(void); 1950 1951 /******************************************************************************* 1952 * Function Name: Cy_Flashc_ECCDisable 1953 ****************************************************************************//** 1954 * 1955 * \brief Disables ECC for flash 1956 * ECC checking/reporting on FLASH interface is disabled. 1957 * Correctable or non-correctable faults are not reported by disabling ECC. 1958 * 1959 * \return none 1960 * 1961 *******************************************************************************/ 1962 void Cy_Flashc_ECCDisable(void); 1963 1964 /******************************************************************************* 1965 * Function Name: Cy_Flashc_INJ_ECCEnable 1966 ****************************************************************************//** 1967 * 1968 * \brief This function enable ECC error injection for FLASH interface 1969 * And is applicable while ECC is enabled. 1970 * 1971 * \return none 1972 * 1973 *******************************************************************************/ 1974 void Cy_Flashc_INJ_ECCEnable(void); 1975 1976 /******************************************************************************* 1977 * Function Name: Cy_Flashc_INJ_ECCDisable 1978 ****************************************************************************//** 1979 * 1980 * \brief This function disables ECC error injection for FLASH interface 1981 * 1982 * \return none 1983 * 1984 *******************************************************************************/ 1985 void Cy_Flashc_INJ_ECCDisable(void); 1986 1987 1988 /******************************************************************************* 1989 * Function Name: Cy_Flashc_InjectECC 1990 ****************************************************************************//** 1991 * 1992 * \brief This function enables ECC injection and sets the address where a parity will be injected 1993 * and the parity value. 1994 * Reports success or a reason for failure. 1995 * 1996 * \param address The address where ECC parity will be injected. 1997 * 1998 * \param parity The parity value which will be injected. 1999 * 2000 * \returns none. 2001 * 2002 *******************************************************************************/ 2003 void Cy_Flashc_InjectECC(uint32_t address, uint8_t parity); 2004 2005 /******************************************************************************* 2006 * Function Name: Cy_Flashc_Get_ECC_Error 2007 ****************************************************************************//** 2008 * 2009 * \brief This function when ECC injection is enabled and error is injected will return no of errors generated. 2010 * 2011 * \returns no of errors generated with ECC error injection \ref cy_en_flash_ecc_inject_errors_t. 2012 * 2013 *******************************************************************************/ 2014 cy_en_flash_ecc_inject_errors_t Cy_Flashc_Get_ECC_Error(void); 2015 2016 /******************************************************************************* 2017 * Function Name: Cy_Flashc_Dual_Bank_Mode_Enable 2018 ****************************************************************************//** 2019 * 2020 * \brief Enables Dual bank Mode for flash 2021 * 2022 * \param mapping : Mapping for the main and work regions. 2023 * 2024 * \return none 2025 * 2026 *******************************************************************************/ 2027 void Cy_Flashc_Dual_Bank_Mode_Enable(cy_en_flash_dual_bank_mapping_t mapping); 2028 2029 /******************************************************************************* 2030 * Function Name: Cy_Flashc_Dual_Bank_Mode_Disable 2031 ****************************************************************************//** 2032 * 2033 * \brief Disables Dual bank Mode for flash 2034 * 2035 * \return none 2036 * 2037 *******************************************************************************/ 2038 void Cy_Flashc_Dual_Bank_Mode_Disable(void); 2039 2040 #endif /* !defined (CY_IP_MXS40FLASHC) */ 2041 2042 /** \} group_flash_functions */ 2043 2044 /** \cond INTERNAL */ 2045 2046 /******************************************************************************* 2047 Backward compatibility macro. The following code is DEPRECATED and must 2048 not be used in new projects 2049 *******************************************************************************/ 2050 2051 #define Cy_Flash_IsWriteComplete(...) Cy_Flash_IsOperationComplete() 2052 #define Cy_Flash_IsProgramComplete(...) Cy_Flash_IsOperationComplete() 2053 #define Cy_Flash_IsEraseComplete(...) Cy_Flash_IsOperationComplete() 2054 /** \endcond */ 2055 2056 2057 #if defined(__cplusplus) 2058 } 2059 #endif 2060 2061 #endif /* CY_IP_M4CPUSS || CY_IP_M7CPUSS*/ 2062 2063 #endif /* #if !defined (CY_FLASH_H) */ 2064 2065 /** \} group_flash */ 2066 2067 2068 /* [] END OF FILE */ 2069
