1/*
2 * Copyright (c) 2023 Cypress Semiconductor Corporation.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/* Configure pin control bias mode for uart2 pins */
7&p3_1_scb2_uart_tx {
8	drive-push-pull;
9};
10
11&p3_0_scb2_uart_rx {
12	input-enable;
13};
14
15&p3_2_scb2_uart_rts {
16	drive-push-pull;
17};
18
19&p3_3_scb2_uart_cts {
20	input-enable;
21};
22
23/* Configure pin control bias mode for uart5 pins */
24&p5_1_scb5_uart_tx {
25	drive-push-pull;
26};
27
28&p5_0_scb5_uart_rx {
29	input-enable;
30};
31
32/* Configure pin control bias mode for i2c3 pins */
33&p6_0_scb3_i2c_scl {
34	drive-open-drain;
35	input-enable;
36};
37
38&p6_1_scb3_i2c_sda {
39	drive-open-drain;
40	input-enable;
41};
42
43&pinctrl {
44	/* Configure pin control bias mode for SDIO */
45	p2_5_sdio_clk: p2_5_sdio_clk {
46		pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_14)>;
47		drive-push-pull;
48		input-enable;
49	};
50
51	p2_4_sdio_cmd: p2_4_sdio_cmd  {
52		pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_14)>;
53		drive-push-pull;
54		input-enable;
55	};
56
57	p2_0_sdio_data0: p2_0_sdio_data0 {
58		pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_14)>;
59		drive-push-pull;
60		input-enable;
61	};
62
63	p2_1_sdio_data1: p2_1_sdio_data1 {
64		pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_14)>;
65		drive-push-pull;
66		input-enable;
67	};
68
69	p2_2_sdio_data2: p2_2_sdio_data2 {
70		pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_14)>;
71		drive-push-pull;
72		input-enable;
73	};
74
75	p2_3_sdio_data3: p2_3_sdio_data3 {
76		pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_14)>;
77		drive-push-pull;
78		input-enable;
79	};
80};
81