1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cy8c6xx7_cm4.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM4 core.
49; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
50; Using this memory region for other purposes will lead to unexpected behavior.
51; RAM
52#define RAM_START               0x08000000
53#define RAM_SIZE                0x00047780
54; Flash
55#define FLASH_START             0x10000000
56#define FLASH_SIZE              0x00100000
57
58; The size of the stack section at the end of CM4 SRAM
59#define STACK_SIZE              0x00001000
60
61; The following defines describe a 32K flash region used for EEPROM emulation.
62; This region can also be used as the general purpose flash.
63; You can assign sections to this memory region for only one of the cores.
64; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65; Therefore, repurposing this memory region will prevent such middleware from operation.
66#define EM_EEPROM_START         0x14000000
67#define EM_EEPROM_SIZE          0x8000
68
69; The following defines describe device specific memory regions and must not be changed.
70; Supervisory flash: User data
71#define SFLASH_USER_DATA_START  0x16000800
72#define SFLASH_USER_DATA_SIZE   0x00000800
73
74; Supervisory flash: Normal Access Restrictions (NAR)
75#define SFLASH_NAR_START        0x16001A00
76#define SFLASH_NAR_SIZE         0x00000200
77
78; Supervisory flash: Public Key
79#define SFLASH_PUBLIC_KEY_START 0x16005A00
80#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
81
82; Supervisory flash: Table of Content # 2
83#define SFLASH_TOC_2_START      0x16007C00
84#define SFLASH_TOC_2_SIZE       0x00000200
85
86; Supervisory flash: Table of Content # 2 Copy
87#define SFLASH_RTOC_2_START     0x16007E00
88#define SFLASH_RTOC_2_SIZE      0x00000200
89
90; External memory
91#define XIP_START               0x18000000
92#define XIP_SIZE                0x08000000
93
94; eFuse
95#define EFUSE_START             0x90700000
96#define EFUSE_SIZE              0x100000
97
98
99; Cortex-M4 application flash area
100LR_IROM1 FLASH_START FLASH_SIZE
101{
102    ER_FLASH_VECTORS +0
103    {
104        * (RESET, +FIRST)
105    }
106
107    ER_FLASH_CODE +0 FIXED
108    {
109        * (InRoot$$Sections)
110        * (+RO)
111    }
112
113    ER_RAM_VECTORS RAM_START UNINIT
114    {
115        * (RESET_RAM, +FIRST)
116    }
117
118    RW_RAM_DATA +0
119    {
120        * (.cy_ramfunc)
121        * (+RW, +ZI)
122    }
123
124    ; Place variables in the section that should not be initialized during the
125    ; device startup.
126    RW_IRAM1 +0 UNINIT
127    {
128        * (.noinit)
129        * (.bss.noinit)
130    }
131
132    ; Application heap area (HEAP)
133    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
134    {
135    }
136
137    ; Stack region growing down
138    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
139    {
140    }
141
142    ; Used for the digital signature of the secure application and the
143    ; Bootloader SDK application. The size of the section depends on the required
144    ; data size.
145    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
146    {
147        * (.cy_app_signature)
148    }
149}
150
151
152; Emulated EEPROM Flash area
153LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
154{
155    .cy_em_eeprom +0
156    {
157        * (.cy_em_eeprom)
158    }
159}
160
161; Supervisory flash: User data
162LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
163{
164    .cy_sflash_user_data +0
165    {
166        * (.cy_sflash_user_data)
167    }
168}
169
170; Supervisory flash: Normal Access Restrictions (NAR)
171LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
172{
173    .cy_sflash_nar +0
174    {
175        * (.cy_sflash_nar)
176    }
177}
178
179; Supervisory flash: Public Key
180LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
181{
182    .cy_sflash_public_key +0
183    {
184        * (.cy_sflash_public_key)
185    }
186}
187
188; Supervisory flash: Table of Content # 2
189LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
190{
191    .cy_toc_part2 +0
192    {
193        * (.cy_toc_part2)
194    }
195}
196
197; Supervisory flash: Table of Content # 2 Copy
198LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
199{
200    .cy_rtoc_part2 +0
201    {
202        * (.cy_rtoc_part2)
203    }
204}
205
206
207; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
208LR_EROM XIP_START XIP_SIZE
209{
210    cy_xip +0
211    {
212        * (.cy_xip)
213    }
214}
215
216
217; eFuse
218LR_EFUSE EFUSE_START EFUSE_SIZE
219{
220    .cy_efuse +0
221    {
222        * (.cy_efuse)
223    }
224}
225
226
227; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
228CYMETA 0x90500000
229{
230    .cymeta +0 { * (.cymeta) }
231}
232
233/* The following symbols used by the cymcuelftool. */
234/* Flash */
235#define __cy_memory_0_start 0x10000000
236#define __cy_memory_0_length  0x00100000
237#define __cy_memory_0_row_size 0x200
238
239/* Emulated EEPROM Flash area */
240#define __cy_memory_1_start    0x14000000
241#define __cy_memory_1_length   0x8000
242#define __cy_memory_1_row_size 0x200
243
244/* Supervisory Flash */
245#define __cy_memory_2_start    0x16000000
246#define __cy_memory_2_length   0x8000
247#define __cy_memory_2_row_size 0x200
248
249/* XIP */
250#define __cy_memory_3_start    0x18000000
251#define __cy_memory_3_length   0x08000000
252#define __cy_memory_3_row_size 0x200
253
254/* eFuse */
255#define __cy_memory_4_start    0x90700000
256#define __cy_memory_4_length   0x100000
257#define __cy_memory_4_row_size 1
258
259
260/* [] END OF FILE */
261