1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cy8c6xx7_cm0plus.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM0+ core.
49; You can change the memory allocation by editing the RAM and Flash defines.
50; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
51; Using this memory region for other purposes will lead to unexpected behavior.
52; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
53; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
54; RAM
55#define RAM_START               0x08000000
56#define RAM_SIZE                0x00002000
57; Flash
58#define FLASH_START             0x10000000
59#define FLASH_SIZE              0x00002000
60
61; The size of the stack section at the end of CM0+ SRAM
62#define STACK_SIZE              0x00001000
63
64; The following defines describe a 32K flash region used for EEPROM emulation.
65; This region can also be used as the general purpose flash.
66; You can assign sections to this memory region for only one of the cores.
67; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68; Therefore, repurposing this memory region will prevent such middleware from operation.
69#define EM_EEPROM_START         0x14000000
70#define EM_EEPROM_SIZE          0x8000
71
72; The following defines describe device specific memory regions and must not be changed.
73; Supervisory flash: User data
74#define SFLASH_USER_DATA_START  0x16000800
75#define SFLASH_USER_DATA_SIZE   0x00000800
76
77; Supervisory flash: Normal Access Restrictions (NAR)
78#define SFLASH_NAR_START        0x16001A00
79#define SFLASH_NAR_SIZE         0x00000200
80
81; Supervisory flash: Public Key
82#define SFLASH_PUBLIC_KEY_START 0x16005A00
83#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
84
85; Supervisory flash: Table of Content # 2
86#define SFLASH_TOC_2_START      0x16007C00
87#define SFLASH_TOC_2_SIZE       0x00000200
88
89; Supervisory flash: Table of Content # 2 Copy
90#define SFLASH_RTOC_2_START     0x16007E00
91#define SFLASH_RTOC_2_SIZE      0x00000200
92
93; External memory
94#define XIP_START               0x18000000
95#define XIP_SIZE                0x08000000
96
97; eFuse
98#define EFUSE_START             0x90700000
99#define EFUSE_SIZE              0x100000
100
101; Public RAM
102; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
103; This region is used to place objects that require full access from both cores.
104; Uncomment the following lines, define the region size and uncomment placement of
105; .cy_sharedmem section below.
106; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
107; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
108
109; Cortex-M0+ application flash area
110LR_IROM1 FLASH_START FLASH_SIZE
111{
112    .cy_app_header +0
113    {
114        * (.cy_app_header)
115    }
116
117    ER_FLASH_VECTORS +0
118    {
119        * (RESET, +FIRST)
120    }
121
122    ER_FLASH_CODE +0 FIXED
123    {
124        * (InRoot$$Sections)
125        * (+RO)
126    }
127
128    ER_RAM_VECTORS RAM_START UNINIT
129    {
130        * (RESET_RAM, +FIRST)
131    }
132
133    RW_RAM_DATA +0
134    {
135        * (.cy_ramfunc)
136        * (+RW, +ZI)
137    }
138
139    ; Place variables in the section that should not be initialized during the
140    ; device startup.
141    RW_IRAM1 +0 UNINIT
142    {
143        * (.noinit)
144        * (.bss.noinit)
145    }
146
147    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
148    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
149    ;{
150    ;    * (.cy_sharedmem)
151    ;}
152
153    ; Application heap area (HEAP)
154    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
155    {
156    }
157
158    ; Stack region growing down
159    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
160    {
161    }
162}
163
164
165; Emulated EEPROM Flash area
166LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
167{
168    .cy_em_eeprom +0
169    {
170        * (.cy_em_eeprom)
171    }
172}
173
174; Supervisory flash: User data
175LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
176{
177    .cy_sflash_user_data +0
178    {
179        * (.cy_sflash_user_data)
180    }
181}
182
183; Supervisory flash: Normal Access Restrictions (NAR)
184LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
185{
186    .cy_sflash_nar +0
187    {
188        * (.cy_sflash_nar)
189    }
190}
191
192; Supervisory flash: Public Key
193LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
194{
195    .cy_sflash_public_key +0
196    {
197        * (.cy_sflash_public_key)
198    }
199}
200
201; Supervisory flash: Table of Content # 2
202LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
203{
204    .cy_toc_part2 +0
205    {
206        * (.cy_toc_part2)
207    }
208}
209
210; Supervisory flash: Table of Content # 2 Copy
211LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
212{
213    .cy_rtoc_part2 +0
214    {
215        * (.cy_rtoc_part2)
216    }
217}
218
219
220; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
221LR_EROM XIP_START XIP_SIZE
222{
223    cy_xip +0
224    {
225        * (.cy_xip)
226    }
227}
228
229
230; eFuse
231LR_EFUSE EFUSE_START EFUSE_SIZE
232{
233    .cy_efuse +0
234    {
235        * (.cy_efuse)
236    }
237}
238
239
240; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
241CYMETA 0x90500000
242{
243    .cymeta +0 { * (.cymeta) }
244}
245
246/* The following symbols used by the cymcuelftool. */
247/* Flash */
248#define __cy_memory_0_start 0x10000000
249#define __cy_memory_0_length  0x00100000
250#define __cy_memory_0_row_size 0x200
251
252/* Emulated EEPROM Flash area */
253#define __cy_memory_1_start    0x14000000
254#define __cy_memory_1_length   0x8000
255#define __cy_memory_1_row_size 0x200
256
257/* Supervisory Flash */
258#define __cy_memory_2_start    0x16000000
259#define __cy_memory_2_length   0x8000
260#define __cy_memory_2_row_size 0x200
261
262/* XIP */
263#define __cy_memory_3_start    0x18000000
264#define __cy_memory_3_length   0x08000000
265#define __cy_memory_3_row_size 0x200
266
267/* eFuse */
268#define __cy_memory_4_start    0x90700000
269#define __cy_memory_4_length   0x100000
270#define __cy_memory_4_row_size 1
271
272
273/* [] END OF FILE */
274