1/***************************************************************************//**
2* \file cy8c6xx4_cm4_dual.ld
3* \version 2.95.1
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
39SEARCH_DIR(.)
40GROUP(-lgcc -lc -lnosys)
41ENTRY(Reset_Handler)
42
43/* The size of the stack section at the end of CM4 SRAM */
44STACK_SIZE = 0x1000;
45
46/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
47* More about CM0+ prebuilt images, see here:
48* https://github.com/Infineon/psoc6cm0p
49*/
50/* The size of the Cortex-M0+ application image at the start of FLASH */
51FLASH_CM0P_SIZE  = 0x2000;
52
53/* Force symbol to be entered in the output file as an undefined symbol. Doing
54* this may, for example, trigger linking of additional modules from standard
55* libraries. You may list several symbols for each EXTERN, and you may use
56* EXTERN multiple times. This command has the same effect as the -u command-line
57* option.
58*/
59EXTERN(Reset_Handler)
60
61/* The MEMORY section below describes the location and size of blocks of memory in the target.
62* Use this section to specify the memory regions available for allocation.
63*/
64MEMORY
65{
66    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
67     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
68     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
69     * Using this memory region for other purposes will lead to unexpected behavior.
70     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
71     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
72     */
73    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0x1D800
74    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x40000
75
76
77    /* The following regions define device specific memory regions and must not be changed. */
78    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
79    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
80    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
81    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
82    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
83    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
84    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
85}
86
87/* Library configurations */
88GROUP(libgcc.a libc.a libm.a libnosys.a)
89
90/* Linker script to place sections and symbol values. Should be used together
91 * with other linker script that defines memory regions FLASH and RAM.
92 * It references following symbols, which must be defined in code:
93 *   Reset_Handler : Entry of reset handler
94 *
95 * It defines following symbols, which code can use without definition:
96 *   __exidx_start
97 *   __exidx_end
98 *   __copy_table_start__
99 *   __copy_table_end__
100 *   __zero_table_start__
101 *   __zero_table_end__
102 *   __etext
103 *   __data_start__
104 *   __preinit_array_start
105 *   __preinit_array_end
106 *   __init_array_start
107 *   __init_array_end
108 *   __fini_array_start
109 *   __fini_array_end
110 *   __data_end__
111 *   __bss_start__
112 *   __bss_end__
113 *   __end__
114 *   end
115 *   __HeapLimit
116 *   __StackLimit
117 *   __StackTop
118 *   __stack
119 *   __Vectors_End
120 *   __Vectors_Size
121 */
122
123
124SECTIONS
125{
126     /* Cortex-M0+ application flash image area */
127    .cy_m0p_image ORIGIN(flash) :
128    {
129        . = ALIGN(4);
130        __cy_m0p_code_start = . ;
131        KEEP(*(.cy_m0p_image))
132        __cy_m0p_code_end = . ;
133    } > flash
134
135    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
136    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
137
138    /* Cortex-M4 application flash area */
139    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
140    {
141        . = ALIGN(4);
142        __Vectors = . ;
143        KEEP(*(.vectors))
144        . = ALIGN(4);
145        __Vectors_End = .;
146        __Vectors_Size = __Vectors_End - __Vectors;
147        __end__ = .;
148
149        . = ALIGN(4);
150        *(.text*)
151
152        KEEP(*(.init))
153        KEEP(*(.fini))
154
155        /* .ctors */
156        *crtbegin.o(.ctors)
157        *crtbegin?.o(.ctors)
158        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
159        *(SORT(.ctors.*))
160        *(.ctors)
161
162        /* .dtors */
163        *crtbegin.o(.dtors)
164        *crtbegin?.o(.dtors)
165        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
166        *(SORT(.dtors.*))
167        *(.dtors)
168
169        /* Read-only code (constants). */
170        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
171
172        KEEP(*(.eh_frame*))
173    } > flash
174
175
176    .ARM.extab :
177    {
178        *(.ARM.extab* .gnu.linkonce.armextab.*)
179    } > flash
180
181    __exidx_start = .;
182
183    .ARM.exidx :
184    {
185        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
186    } > flash
187    __exidx_end = .;
188
189
190    /* To copy multiple ROM to RAM sections,
191     * uncomment .copy.table section and,
192     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */
193    .copy.table :
194    {
195        . = ALIGN(4);
196        __copy_table_start__ = .;
197
198        /* Copy interrupt vectors from flash to RAM */
199        LONG (__Vectors)                                    /* From */
200        LONG (__ram_vectors_start__)                        /* To   */
201        LONG (__Vectors_End - __Vectors)                    /* Size */
202
203        /* Copy data section to RAM */
204        LONG (__etext)                                      /* From */
205        LONG (__data_start__)                               /* To   */
206        LONG (__data_end__ - __data_start__)                /* Size */
207
208        __copy_table_end__ = .;
209    } > flash
210
211
212    /* To clear multiple BSS sections,
213     * uncomment .zero.table section and,
214     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */
215    .zero.table :
216    {
217        . = ALIGN(4);
218        __zero_table_start__ = .;
219        LONG (__bss_start__)
220        LONG (__bss_end__ - __bss_start__)
221        __zero_table_end__ = .;
222    } > flash
223
224    __etext =  . ;
225
226
227    .ramVectors (NOLOAD) : ALIGN(8)
228    {
229        __ram_vectors_start__ = .;
230        KEEP(*(.ram_vectors))
231        __ram_vectors_end__   = .;
232    } > ram
233
234
235    .data __ram_vectors_end__ :
236    {
237        . = ALIGN(4);
238        __data_start__ = .;
239
240        *(vtable)
241        *(.data*)
242
243        . = ALIGN(4);
244        /* preinit data */
245        PROVIDE_HIDDEN (__preinit_array_start = .);
246        KEEP(*(.preinit_array))
247        PROVIDE_HIDDEN (__preinit_array_end = .);
248
249        . = ALIGN(4);
250        /* init data */
251        PROVIDE_HIDDEN (__init_array_start = .);
252        KEEP(*(SORT(.init_array.*)))
253        KEEP(*(.init_array))
254        PROVIDE_HIDDEN (__init_array_end = .);
255
256        . = ALIGN(4);
257        /* finit data */
258        PROVIDE_HIDDEN (__fini_array_start = .);
259        KEEP(*(SORT(.fini_array.*)))
260        KEEP(*(.fini_array))
261        PROVIDE_HIDDEN (__fini_array_end = .);
262
263        KEEP(*(.jcr*))
264        . = ALIGN(4);
265
266        KEEP(*(.cy_ramfunc*))
267        . = ALIGN(4);
268
269        __data_end__ = .;
270
271    } > ram AT>flash
272
273
274    /* Place variables in the section that should not be initialized during the
275    *  device startup.
276    */
277    .noinit (NOLOAD) : ALIGN(8)
278    {
279      KEEP(*(.noinit))
280    } > ram
281
282
283    /* The uninitialized global or static variables are placed in this section.
284    *
285    * The NOLOAD attribute tells linker that .bss section does not consume
286    * any space in the image. The NOLOAD attribute changes the .bss type to
287    * NOBITS, and that  makes linker to A) not allocate section in memory, and
288    * A) put information to clear the section with all zeros during application
289    * loading.
290    *
291    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
292    * This  makes linker to A) allocate zeroed section in memory, and B) copy
293    * this section to RAM during application loading.
294    */
295    .bss (NOLOAD):
296    {
297        . = ALIGN(4);
298        __bss_start__ = .;
299        *(.bss*)
300        *(COMMON)
301        . = ALIGN(4);
302        __bss_end__ = .;
303    } > ram
304
305
306    .heap (NOLOAD):
307    {
308        __HeapBase = .;
309        __end__ = .;
310        end = __end__;
311        KEEP(*(.heap*))
312        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
313        __HeapLimit = .;
314    } > ram
315
316
317    /* .stack_dummy section doesn't contains any symbols. It is only
318     * used for linker to calculate size of stack sections, and assign
319     * values to stack symbols later */
320    .stack_dummy (NOLOAD):
321    {
322        KEEP(*(.stack*))
323    } > ram
324
325
326    /* Set stack top to end of RAM, and stack limit move down by
327     * size of stack_dummy section */
328    __StackTop = ORIGIN(ram) + LENGTH(ram);
329    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
330    PROVIDE(__stack = __StackTop);
331
332    /* Check if data + heap + stack exceeds RAM limit */
333    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
334
335
336    /* Used for the digital signature of the secure application and the Bootloader SDK application.
337    * The size of the section depends on the required data size. */
338    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
339    {
340        KEEP(*(.cy_app_signature))
341    } > flash
342
343
344
345
346    /* Supervisory Flash: User data */
347    .cy_sflash_user_data :
348    {
349        KEEP(*(.cy_sflash_user_data))
350    } > sflash_user_data
351
352
353    /* Supervisory Flash: Normal Access Restrictions (NAR) */
354    .cy_sflash_nar :
355    {
356        KEEP(*(.cy_sflash_nar))
357    } > sflash_nar
358
359
360    /* Supervisory Flash: Public Key */
361    .cy_sflash_public_key :
362    {
363        KEEP(*(.cy_sflash_public_key))
364    } > sflash_public_key
365
366
367    /* Supervisory Flash: Table of Content # 2 */
368    .cy_toc_part2 :
369    {
370        KEEP(*(.cy_toc_part2))
371    } > sflash_toc_2
372
373
374    /* Supervisory Flash: Table of Content # 2 Copy */
375    .cy_rtoc_part2 :
376    {
377        KEEP(*(.cy_rtoc_part2))
378    } > sflash_rtoc_2
379
380
381    /* Places the code in the Execute in Place (XIP) section. See the smif driver
382    *  documentation for details.
383    */
384    cy_xip :
385    {
386        __cy_xip_start = .;
387        KEEP(*(.cy_xip))
388        __cy_xip_end = .;
389    } > xip
390
391
392    /* eFuse */
393    .cy_efuse :
394    {
395        KEEP(*(.cy_efuse))
396    } > efuse
397
398
399    /* These sections are used for additional metadata (silicon revision,
400    *  Silicon/JTAG ID, etc.) storage.
401    */
402    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
403}
404
405
406/* The following symbols used by the cymcuelftool. */
407/* Flash */
408__cy_memory_0_start    = 0x10000000;
409__cy_memory_0_length   = 0x00040000;
410__cy_memory_0_row_size = 0x200;
411
412
413/* Supervisory Flash */
414__cy_memory_2_start    = 0x16000000;
415__cy_memory_2_length   = 0x8000;
416__cy_memory_2_row_size = 0x200;
417
418/* XIP */
419__cy_memory_3_start    = 0x18000000;
420__cy_memory_3_length   = 0x08000000;
421__cy_memory_3_row_size = 0x200;
422
423/* eFuse */
424__cy_memory_4_start    = 0x90700000;
425__cy_memory_4_length   = 0x100000;
426__cy_memory_4_row_size = 1;
427
428/* EOF */
429