1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cy8c6xx4_cm0plus.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM0+ core.
49; You can change the memory allocation by editing the RAM and Flash defines.
50; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
51; Using this memory region for other purposes will lead to unexpected behavior.
52; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
53; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
54; RAM
55#define RAM_START               0x08000000
56#define RAM_SIZE                0x00002000
57; Flash
58#define FLASH_START             0x10000000
59#define FLASH_SIZE              0x00002000
60
61; The size of the stack section at the end of CM0+ SRAM
62#define STACK_SIZE              0x00001000
63
64
65; The following defines describe device specific memory regions and must not be changed.
66; Supervisory flash: User data
67#define SFLASH_USER_DATA_START  0x16000800
68#define SFLASH_USER_DATA_SIZE   0x00000800
69
70; Supervisory flash: Normal Access Restrictions (NAR)
71#define SFLASH_NAR_START        0x16001A00
72#define SFLASH_NAR_SIZE         0x00000200
73
74; Supervisory flash: Public Key
75#define SFLASH_PUBLIC_KEY_START 0x16005A00
76#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
77
78; Supervisory flash: Table of Content # 2
79#define SFLASH_TOC_2_START      0x16007C00
80#define SFLASH_TOC_2_SIZE       0x00000200
81
82; Supervisory flash: Table of Content # 2 Copy
83#define SFLASH_RTOC_2_START     0x16007E00
84#define SFLASH_RTOC_2_SIZE      0x00000200
85
86; External memory
87#define XIP_START               0x18000000
88#define XIP_SIZE                0x08000000
89
90; eFuse
91#define EFUSE_START             0x90700000
92#define EFUSE_SIZE              0x100000
93
94; Public RAM
95; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
96; This region is used to place objects that require full access from both cores.
97; Uncomment the following lines, define the region size and uncomment placement of
98; .cy_sharedmem section below.
99; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
100; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
101
102; Cortex-M0+ application flash area
103LR_IROM1 FLASH_START FLASH_SIZE
104{
105    .cy_app_header +0
106    {
107        * (.cy_app_header)
108    }
109
110    ER_FLASH_VECTORS +0
111    {
112        * (RESET, +FIRST)
113    }
114
115    ER_FLASH_CODE +0 FIXED
116    {
117        * (InRoot$$Sections)
118        * (+RO)
119    }
120
121    ER_RAM_VECTORS RAM_START UNINIT
122    {
123        * (RESET_RAM, +FIRST)
124    }
125
126    RW_RAM_DATA +0
127    {
128        * (.cy_ramfunc)
129        * (+RW, +ZI)
130    }
131
132    ; Place variables in the section that should not be initialized during the
133    ; device startup.
134    RW_IRAM1 +0 UNINIT
135    {
136        * (.noinit)
137        * (.bss.noinit)
138    }
139
140    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
141    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
142    ;{
143    ;    * (.cy_sharedmem)
144    ;}
145
146    ; Application heap area (HEAP)
147    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
148    {
149    }
150
151    ; Stack region growing down
152    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
153    {
154    }
155}
156
157
158
159; Supervisory flash: User data
160LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
161{
162    .cy_sflash_user_data +0
163    {
164        * (.cy_sflash_user_data)
165    }
166}
167
168; Supervisory flash: Normal Access Restrictions (NAR)
169LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
170{
171    .cy_sflash_nar +0
172    {
173        * (.cy_sflash_nar)
174    }
175}
176
177; Supervisory flash: Public Key
178LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
179{
180    .cy_sflash_public_key +0
181    {
182        * (.cy_sflash_public_key)
183    }
184}
185
186; Supervisory flash: Table of Content # 2
187LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
188{
189    .cy_toc_part2 +0
190    {
191        * (.cy_toc_part2)
192    }
193}
194
195; Supervisory flash: Table of Content # 2 Copy
196LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
197{
198    .cy_rtoc_part2 +0
199    {
200        * (.cy_rtoc_part2)
201    }
202}
203
204
205; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
206LR_EROM XIP_START XIP_SIZE
207{
208    cy_xip +0
209    {
210        * (.cy_xip)
211    }
212}
213
214
215; eFuse
216LR_EFUSE EFUSE_START EFUSE_SIZE
217{
218    .cy_efuse +0
219    {
220        * (.cy_efuse)
221    }
222}
223
224
225; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
226CYMETA 0x90500000
227{
228    .cymeta +0 { * (.cymeta) }
229}
230
231/* The following symbols used by the cymcuelftool. */
232/* Flash */
233#define __cy_memory_0_start 0x10000000
234#define __cy_memory_0_length  0x00040000
235#define __cy_memory_0_row_size 0x200
236
237
238/* Supervisory Flash */
239#define __cy_memory_2_start    0x16000000
240#define __cy_memory_2_length   0x8000
241#define __cy_memory_2_row_size 0x200
242
243/* XIP */
244#define __cy_memory_3_start    0x18000000
245#define __cy_memory_3_length   0x08000000
246#define __cy_memory_3_row_size 0x200
247
248/* eFuse */
249#define __cy_memory_4_start    0x90700000
250#define __cy_memory_4_length   0x100000
251#define __cy_memory_4_row_size 1
252
253
254/* [] END OF FILE */
255