1 /***************************************************************************//** 2 * \file cy8c6117fdi_f02.h 3 * 4 * \brief 5 * CY8C6117FDI-F02 device header 6 * 7 * \note 8 * Generator version: 1.6.0.414 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CY8C6117FDI_F02_H_ 29 #define _CY8C6117FDI_F02_H_ 30 31 /** 32 * \addtogroup group_device CY8C6117FDI-F02 33 * \{ 34 */ 35 36 /** 37 * \addtogroup Configuration_of_CMSIS 38 * \{ 39 */ 40 41 /******************************************************************************* 42 * Interrupt Number Definition 43 *******************************************************************************/ 44 45 typedef enum { 46 /* ARM Cortex-M4 Core Interrupt Numbers */ 47 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 48 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 49 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 50 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 51 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 52 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 53 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 54 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 55 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 56 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 57 /* CY8C6117FDI-F02 Peripheral Interrupt Numbers */ 58 ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ 59 ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ 60 ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ 61 ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ 62 ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ 63 ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ 64 ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ 65 ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ 66 ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ 67 ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ 68 ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ 69 ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ 70 ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ 71 ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ 72 ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ 73 ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ 74 ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ 75 lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ 76 scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ 77 srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 78 srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ 79 srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ 80 srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 81 pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ 82 bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ 83 cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ 84 cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ 85 cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ 86 cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ 87 cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ 88 cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ 89 cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ 90 cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ 91 cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ 92 cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ 93 cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ 94 cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ 95 cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ 96 cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ 97 cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ 98 cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ 99 scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ 100 scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ 101 scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ 102 scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ 103 scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ 104 scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ 105 scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ 106 scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ 107 csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ 108 cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ 109 cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ 110 cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ 111 cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ 112 cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ 113 cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ 114 cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ 115 cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ 116 cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ 117 cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ 118 cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ 119 cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ 120 cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ 121 cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ 122 cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ 123 cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ 124 cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ 125 cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ 126 cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ 127 cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ 128 cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ 129 cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ 130 cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ 131 cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ 132 cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ 133 cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ 134 cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ 135 cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ 136 cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ 137 cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ 138 cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ 139 cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ 140 cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ 141 cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ 142 cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ 143 cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ 144 cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ 145 cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ 146 cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ 147 cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ 148 tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ 149 tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ 150 tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ 151 tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ 152 tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ 153 tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ 154 tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ 155 tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ 156 tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ 157 tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ 158 tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ 159 tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ 160 tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ 161 tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ 162 tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ 163 tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ 164 tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ 165 tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ 166 tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ 167 tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ 168 tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ 169 tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ 170 tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ 171 tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ 172 tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ 173 tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ 174 tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ 175 tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ 176 tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ 177 tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ 178 tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ 179 tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ 180 udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ 181 udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ 182 udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ 183 udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ 184 udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ 185 udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ 186 udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ 187 udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ 188 udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ 189 udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ 190 udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ 191 udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ 192 udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ 193 udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ 194 udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ 195 udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ 196 pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ 197 audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ 198 audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ 199 profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ 200 smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ 201 usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ 202 usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ 203 usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ 204 pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ 205 unconnected_IRQn = 240 /*!< 240 Unconnected */ 206 } IRQn_Type; 207 208 209 /******************************************************************************* 210 * Processor and Core Peripheral Section 211 *******************************************************************************/ 212 213 /* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ 214 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 215 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 216 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 217 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 218 #define __MPU_PRESENT 1 /*!< MPU present or not */ 219 #define __FPU_PRESENT 1 /*!< FPU present or not */ 220 #define __CM0P_PRESENT 0 /*!< CM0P present or not */ 221 #define __DTCM_PRESENT 0 /*!< DTCM present or not */ 222 #define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ 223 #define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ 224 225 /** \} Configuration_of_CMSIS */ 226 227 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 228 229 230 /* Memory Blocks */ 231 #define CY_ROM_BASE 0x00000000UL 232 #define CY_ROM_SIZE 0x00020000UL 233 #define CY_SRAM_BASE 0x08000000UL 234 #define CY_SRAM_SIZE 0x00048000UL 235 #define CY_FLASH_BASE 0x10000000UL 236 #define CY_FLASH_SIZE 0x00100000UL 237 #define CY_EM_EEPROM_BASE 0x14000000UL 238 #define CY_EM_EEPROM_SIZE 0x00008000UL 239 #define CY_SFLASH_BASE 0x16000000UL 240 #define CY_SFLASH_SIZE 0x00008000UL 241 #define CY_XIP_BASE 0x18000000UL 242 #define CY_XIP_SIZE 0x08000000UL 243 #define CY_EFUSE_BASE 0x402C0800UL 244 #define CY_EFUSE_SIZE 0x00000200UL 245 246 #include "system_psoc6.h" /*!< PSoC 6 System */ 247 248 /* IP List */ 249 #define CY_IP_MXAUDIOSS 1u 250 #define CY_IP_MXAUDIOSS_INSTANCES 1u 251 #define CY_IP_MXAUDIOSS_VERSION 1u 252 #define CY_IP_M4CPUSS 1u 253 #define CY_IP_M4CPUSS_INSTANCES 1u 254 #define CY_IP_M4CPUSS_VERSION 1u 255 #define CY_IP_M4CPUSS_DMA 1u 256 #define CY_IP_M4CPUSS_DMA_INSTANCES 2u 257 #define CY_IP_M4CPUSS_DMA_VERSION 1u 258 #define CY_IP_MXCSDV2 1u 259 #define CY_IP_MXCSDV2_INSTANCES 1u 260 #define CY_IP_MXCSDV2_VERSION 1u 261 #define CY_IP_MXEFUSE 1u 262 #define CY_IP_MXEFUSE_INSTANCES 1u 263 #define CY_IP_MXEFUSE_VERSION 1u 264 #define CY_IP_MXS40IOSS 1u 265 #define CY_IP_MXS40IOSS_INSTANCES 1u 266 #define CY_IP_MXS40IOSS_VERSION 1u 267 #define CY_IP_MXLCD 1u 268 #define CY_IP_MXLCD_INSTANCES 1u 269 #define CY_IP_MXLCD_VERSION 1u 270 #define CY_IP_MXLPCOMP 1u 271 #define CY_IP_MXLPCOMP_INSTANCES 1u 272 #define CY_IP_MXLPCOMP_VERSION 1u 273 #define CY_IP_MXS40PASS 1u 274 #define CY_IP_MXS40PASS_INSTANCES 1u 275 #define CY_IP_MXS40PASS_VERSION 1u 276 #define CY_IP_MXS40PASS_SAR 1u 277 #define CY_IP_MXS40PASS_SAR_INSTANCES 1u 278 #define CY_IP_MXS40PASS_SAR_VERSION 1u 279 #define CY_IP_MXS40PASS_CTDAC 1u 280 #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u 281 #define CY_IP_MXS40PASS_CTDAC_VERSION 1u 282 #define CY_IP_MXPERI 1u 283 #define CY_IP_MXPERI_INSTANCES 1u 284 #define CY_IP_MXPERI_VERSION 1u 285 #define CY_IP_MXPERI_TR 1u 286 #define CY_IP_MXPERI_TR_INSTANCES 1u 287 #define CY_IP_MXPERI_TR_VERSION 1u 288 #define CY_IP_MXPROFILE 1u 289 #define CY_IP_MXPROFILE_INSTANCES 1u 290 #define CY_IP_MXPROFILE_VERSION 1u 291 #define CY_IP_MXSCB 1u 292 #define CY_IP_MXSCB_INSTANCES 9u 293 #define CY_IP_MXSCB_VERSION 1u 294 #define CY_IP_MXSMIF 1u 295 #define CY_IP_MXSMIF_INSTANCES 1u 296 #define CY_IP_MXSMIF_VERSION 1u 297 #define CY_IP_MXS40SRSS 1u 298 #define CY_IP_MXS40SRSS_INSTANCES 1u 299 #define CY_IP_MXS40SRSS_VERSION 1u 300 #define CY_IP_MXS40SRSS_RTC 1u 301 #define CY_IP_MXS40SRSS_RTC_INSTANCES 1u 302 #define CY_IP_MXS40SRSS_RTC_VERSION 1u 303 #define CY_IP_MXS40SRSS_MCWDT 1u 304 #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u 305 #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u 306 #define CY_IP_MXTCPWM 1u 307 #define CY_IP_MXTCPWM_INSTANCES 2u 308 #define CY_IP_MXTCPWM_VERSION 1u 309 #define CY_IP_MXUSBFS 1u 310 #define CY_IP_MXUSBFS_INSTANCES 1u 311 #define CY_IP_MXUSBFS_VERSION 1u 312 313 #include "psoc6_01_config.h" 314 #include "gpio_psoc6_01_80_wlcsp.h" 315 316 #define CY_DEVICE_PSOC6ABLE2 317 #define CY_SILICON_ID 0xE2312100UL 318 #define CY_HF_CLK_MAX_FREQ 50000000UL 319 320 #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL 321 322 /******************************************************************************* 323 * SFLASH 324 *******************************************************************************/ 325 326 #define SFLASH_BASE 0x16000000UL 327 #define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ 328 329 /******************************************************************************* 330 * PERI 331 *******************************************************************************/ 332 333 #define PERI_BASE 0x40010000UL 334 #define PERI_PPU_GR_MMIO0_BASE 0x40015000UL 335 #define PERI_PPU_GR_MMIO1_BASE 0x40015040UL 336 #define PERI_PPU_GR_MMIO2_BASE 0x40015080UL 337 #define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL 338 #define PERI_PPU_GR_MMIO4_BASE 0x40015100UL 339 #define PERI_PPU_GR_MMIO6_BASE 0x40015180UL 340 #define PERI_PPU_GR_MMIO9_BASE 0x40015240UL 341 #define PERI_PPU_GR_MMIO10_BASE 0x40015280UL 342 #define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL 343 #define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL 344 #define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL 345 #define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL 346 #define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL 347 #define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL 348 #define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL 349 #define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL 350 #define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL 351 #define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL 352 #define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL 353 #define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL 354 #define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL 355 #define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL 356 #define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL 357 #define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL 358 #define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL 359 #define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL 360 #define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL 361 #define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL 362 #define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL 363 #define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL 364 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL 365 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL 366 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL 367 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL 368 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL 369 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL 370 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL 371 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL 372 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL 373 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL 374 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL 375 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL 376 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL 377 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL 378 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL 379 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL 380 #define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL 381 #define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL 382 #define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL 383 #define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL 384 #define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL 385 #define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL 386 #define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL 387 #define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL 388 #define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL 389 #define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL 390 #define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL 391 #define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL 392 #define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL 393 #define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL 394 #define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL 395 #define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL 396 #define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL 397 #define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL 398 #define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL 399 #define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL 400 #define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL 401 #define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL 402 #define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL 403 #define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL 404 #define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL 405 #define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL 406 #define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL 407 #define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL 408 #define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL 409 #define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL 410 #define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL 411 #define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL 412 #define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL 413 #define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL 414 #define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ 415 #define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ 416 #define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ 417 #define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ 418 #define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ 419 #define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ 420 #define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ 421 #define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ 422 #define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ 423 #define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ 424 #define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ 425 #define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ 426 #define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ 427 #define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ 428 #define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ 429 #define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ 430 #define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ 431 #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ 432 #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ 433 #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ 434 #define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ 435 #define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ 436 #define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ 437 #define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ 438 #define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ 439 #define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ 440 #define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ 441 #define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ 442 #define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ 443 #define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ 444 #define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ 445 #define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ 446 #define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ 447 #define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ 448 #define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ 449 #define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ 450 #define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ 451 #define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ 452 #define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ 453 #define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ 454 #define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ 455 #define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ 456 #define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ 457 #define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ 458 #define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ 459 #define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ 460 #define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ 461 #define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ 462 #define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ 463 #define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ 464 #define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ 465 #define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ 466 #define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ 467 #define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ 468 #define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ 469 #define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ 470 #define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ 471 #define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ 472 #define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ 473 #define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ 474 #define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ 475 #define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ 476 #define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ 477 #define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ 478 #define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ 479 #define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ 480 #define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ 481 #define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ 482 #define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ 483 #define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ 484 #define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ 485 #define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ 486 #define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ 487 #define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ 488 #define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ 489 #define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ 490 #define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ 491 #define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ 492 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ 493 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ 494 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ 495 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ 496 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ 497 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ 498 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ 499 #define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ 500 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ 501 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ 502 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ 503 #define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ 504 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ 505 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ 506 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ 507 #define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ 508 #define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ 509 #define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ 510 #define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ 511 #define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ 512 #define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ 513 #define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ 514 #define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ 515 #define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ 516 #define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ 517 #define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ 518 #define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ 519 #define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ 520 #define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ 521 #define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ 522 #define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ 523 #define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ 524 #define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ 525 #define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ 526 #define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ 527 #define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ 528 #define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ 529 #define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ 530 #define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ 531 #define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ 532 #define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ 533 #define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ 534 #define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ 535 #define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ 536 #define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ 537 #define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ 538 #define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ 539 #define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ 540 #define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ 541 #define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ 542 543 /******************************************************************************* 544 * CPUSS 545 *******************************************************************************/ 546 547 #define CPUSS_BASE 0x40210000UL 548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ 549 550 /******************************************************************************* 551 * FAULT 552 *******************************************************************************/ 553 554 #define FAULT_BASE 0x40220000UL 555 #define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ 556 #define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ 557 #define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ 558 559 /******************************************************************************* 560 * IPC 561 *******************************************************************************/ 562 563 #define IPC_BASE 0x40230000UL 564 #define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ 565 #define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ 566 #define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ 567 #define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ 568 #define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ 569 #define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ 570 #define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ 571 #define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ 572 #define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ 573 #define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ 574 #define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ 575 #define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ 576 #define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ 577 #define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ 578 #define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ 579 #define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ 580 #define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ 581 #define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ 582 #define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ 583 #define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ 584 #define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ 585 #define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ 586 #define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ 587 #define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ 588 #define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ 589 #define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ 590 #define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ 591 #define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ 592 #define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ 593 #define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ 594 #define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ 595 #define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ 596 #define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ 597 598 /******************************************************************************* 599 * PROT 600 *******************************************************************************/ 601 602 #define PROT_BASE 0x40240000UL 603 #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ 604 #define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ 605 #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ 606 #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ 607 #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ 608 #define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ 609 #define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ 610 #define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ 611 #define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ 612 #define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ 613 #define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ 614 #define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ 615 #define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ 616 #define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ 617 #define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ 618 #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ 619 #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ 620 #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ 621 #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ 622 #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ 623 #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ 624 #define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ 625 #define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ 626 #define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ 627 #define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ 628 #define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ 629 #define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ 630 #define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ 631 #define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ 632 #define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ 633 #define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ 634 #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ 635 #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ 636 #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ 637 #define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ 638 #define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ 639 #define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ 640 #define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ 641 #define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ 642 #define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ 643 #define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ 644 #define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ 645 #define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ 646 #define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ 647 #define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ 648 #define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ 649 #define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ 650 #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ 651 #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ 652 #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ 653 654 /******************************************************************************* 655 * FLASHC 656 *******************************************************************************/ 657 658 #define FLASHC_BASE 0x40250000UL 659 #define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ 660 #define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ 661 662 /******************************************************************************* 663 * SRSS 664 *******************************************************************************/ 665 666 #define SRSS_BASE 0x40260000UL 667 #define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ 668 #define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ 669 #define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ 670 671 /******************************************************************************* 672 * BACKUP 673 *******************************************************************************/ 674 675 #define BACKUP_BASE 0x40270000UL 676 #define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ 677 678 /******************************************************************************* 679 * DW 680 *******************************************************************************/ 681 682 #define DW0_BASE 0x40280000UL 683 #define DW1_BASE 0x40281000UL 684 #define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ 685 #define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ 686 #define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ 687 #define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ 688 #define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ 689 #define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ 690 #define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ 691 #define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ 692 #define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ 693 #define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ 694 #define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ 695 #define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ 696 #define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ 697 #define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ 698 #define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ 699 #define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ 700 #define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ 701 #define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ 702 #define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ 703 #define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ 704 #define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ 705 #define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ 706 #define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ 707 #define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ 708 #define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ 709 #define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ 710 #define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ 711 #define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ 712 #define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ 713 #define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ 714 #define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ 715 #define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ 716 #define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ 717 #define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ 718 719 /******************************************************************************* 720 * EFUSE 721 *******************************************************************************/ 722 723 #define EFUSE_BASE 0x402C0000UL 724 #define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ 725 726 /******************************************************************************* 727 * PROFILE 728 *******************************************************************************/ 729 730 #define PROFILE_BASE 0x402D0000UL 731 #define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ 732 #define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ 733 #define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ 734 #define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ 735 #define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ 736 #define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ 737 #define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ 738 #define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ 739 #define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ 740 741 /******************************************************************************* 742 * HSIOM 743 *******************************************************************************/ 744 745 #define HSIOM_BASE 0x40310000UL 746 #define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ 747 #define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ 748 #define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ 749 #define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ 750 #define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ 751 #define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ 752 #define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ 753 #define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ 754 #define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ 755 #define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ 756 #define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ 757 #define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ 758 #define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ 759 #define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ 760 #define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ 761 #define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ 762 763 /******************************************************************************* 764 * GPIO 765 *******************************************************************************/ 766 767 #define GPIO_BASE 0x40320000UL 768 #define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ 769 #define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ 770 #define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ 771 #define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ 772 #define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ 773 #define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ 774 #define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ 775 #define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ 776 #define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ 777 #define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ 778 #define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ 779 #define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ 780 #define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ 781 #define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ 782 #define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ 783 #define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ 784 785 /******************************************************************************* 786 * SMARTIO 787 *******************************************************************************/ 788 789 #define SMARTIO_BASE 0x40330000UL 790 #define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ 791 #define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ 792 #define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ 793 794 /******************************************************************************* 795 * LPCOMP 796 *******************************************************************************/ 797 798 #define LPCOMP_BASE 0x40350000UL 799 #define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ 800 801 /******************************************************************************* 802 * CSD 803 *******************************************************************************/ 804 805 #define CSD0_BASE 0x40360000UL 806 #define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ 807 808 /******************************************************************************* 809 * TCPWM 810 *******************************************************************************/ 811 812 #define TCPWM0_BASE 0x40380000UL 813 #define TCPWM1_BASE 0x40390000UL 814 #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ 815 #define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ 816 #define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ 817 #define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ 818 #define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ 819 #define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ 820 #define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ 821 #define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ 822 #define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ 823 #define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ 824 #define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ 825 #define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ 826 #define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ 827 #define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ 828 #define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ 829 #define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ 830 #define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ 831 #define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ 832 #define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ 833 #define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ 834 #define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ 835 #define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ 836 #define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ 837 #define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ 838 #define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ 839 #define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ 840 #define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ 841 #define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ 842 #define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ 843 #define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ 844 #define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ 845 #define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ 846 #define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ 847 #define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ 848 849 /******************************************************************************* 850 * LCD 851 *******************************************************************************/ 852 853 #define LCD0_BASE 0x403B0000UL 854 #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ 855 856 /******************************************************************************* 857 * USBFS 858 *******************************************************************************/ 859 860 #define USBFS0_BASE 0x403F0000UL 861 #define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ 862 #define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ 863 #define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ 864 #define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ 865 866 /******************************************************************************* 867 * SMIF 868 *******************************************************************************/ 869 870 #define SMIF0_BASE 0x40420000UL 871 #define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ 872 #define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ 873 #define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ 874 #define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ 875 #define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ 876 877 /******************************************************************************* 878 * SCB 879 *******************************************************************************/ 880 881 #define SCB0_BASE 0x40610000UL 882 #define SCB1_BASE 0x40620000UL 883 #define SCB2_BASE 0x40630000UL 884 #define SCB3_BASE 0x40640000UL 885 #define SCB4_BASE 0x40650000UL 886 #define SCB5_BASE 0x40660000UL 887 #define SCB6_BASE 0x40670000UL 888 #define SCB7_BASE 0x40680000UL 889 #define SCB8_BASE 0x40690000UL 890 #define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ 891 #define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ 892 #define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ 893 #define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ 894 #define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ 895 #define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ 896 #define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ 897 #define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ 898 #define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ 899 900 /******************************************************************************* 901 * CTBM 902 *******************************************************************************/ 903 904 #define CTBM0_BASE 0x41100000UL 905 #define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ 906 907 /******************************************************************************* 908 * CTDAC 909 *******************************************************************************/ 910 911 #define CTDAC0_BASE 0x41140000UL 912 #define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ 913 914 /******************************************************************************* 915 * SAR 916 *******************************************************************************/ 917 918 #define SAR_BASE 0x411D0000UL 919 #define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ 920 921 /******************************************************************************* 922 * PASS 923 *******************************************************************************/ 924 925 #define PASS_BASE 0x411F0000UL 926 #define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ 927 #define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ 928 929 /******************************************************************************* 930 * I2S 931 *******************************************************************************/ 932 933 #define I2S0_BASE 0x42A10000UL 934 #define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ 935 936 /******************************************************************************* 937 * PDM 938 *******************************************************************************/ 939 940 #define PDM0_BASE 0x42A20000UL 941 #define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ 942 943 944 /* Backward compatibility definitions */ 945 #define CY_SRAM0_BASE CY_SRAM_BASE 946 #define CY_SRAM0_SIZE CY_SRAM_SIZE 947 #define I2S I2S0 948 #define PDM PDM0 949 950 /** \} CY8C6117FDI-F02 */ 951 952 #endif /* _CY8C6117FDI_F02_H_ */ 953 954 955 /* [] END OF FILE */ 956
