1 /**************************************************************************//** 2 * @file crc_reg.h 3 * @version V1.00 4 * @brief CRC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRC_REG_H__ 10 #define __CRC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Cyclic Redundancy Check Controller -------------------------*/ 20 /** 21 @addtogroup CRC Cyclic Redundancy Check Controller(CRC) 22 Memory Mapped Structure for CRC Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var CRC_T::CTL 32 * Offset: 0x00 CRC Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |CRCEN |CRC Channel Generator Enable Bit 37 * | | |Set this bit 1 to enable CRC generator for CRC operation. 38 * | | |0 = No effect. 39 * | | |1 = CRC operation generator is active. 40 * |[1] |CHKSINIT |Checksum Initialization 41 * | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value. 42 * | | |0 = No effect. 43 * | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value. 44 * | | |The others contents of CRC_CTL register will not be cleared. 45 * | | |Note1: This bit will be cleared automatically 46 * | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value. 47 * |[24] |DATREV |Write Data Bit Order Reverse Enable Bit 48 * | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register. 49 * | | |0 = Bit order reversed for CRC_DATA write data in Disabled. 50 * | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte). 51 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 52 * |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit 53 * | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]). 54 * | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled. 55 * | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled. 56 * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB. 57 * |[26] |DATFMT |Write Data 1's Complement Enable Bit 58 * | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]). 59 * | | |0 = 1's complement for CRC_DATA writes data in Disabled. 60 * | | |1 = 1's complement for CRC_DATA writes data in Enabled. 61 * |[27] |CHKSFMT |Checksum 1's Complement Enable Bit 62 * | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register. 63 * | | |0 = 1's complement for CRC CHECKSUM Disabled. 64 * | | |1 = 1's complement for CRC CHECKSUMCRC Enabled. 65 * |[29:28] |DATLEN |CPU Write Data Length 66 * | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]). 67 * | | |00 = Data length is 8-bit mode. 68 * | | |01 = Data length is 16-bit mode. 69 * | | |1x = Data length is 32-bit mode. 70 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] 71 * |[31:30] |CRCMODE |CRC Polynomial Mode 72 * | | |This field indicates the CRC operation polynomial mode. 73 * | | |00 = CRC-CCITT Polynomial mode. 74 * | | |01 = CRC-8 Polynomial mode. 75 * | | |10 = CRC-16 Polynomial mode. 76 * | | |11 = CRC-32 Polynomial mode. 77 * @var CRC_T::DAT 78 * Offset: 0x04 CRC Write Data Register 79 * --------------------------------------------------------------------------------------------------- 80 * |Bits |Field |Descriptions 81 * | :----: | :----: | :---- | 82 * |[31:0] |DATA |CRC Write Data Bits 83 * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. 84 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 85 * @var CRC_T::SEED 86 * Offset: 0x08 CRC Seed Register 87 * --------------------------------------------------------------------------------------------------- 88 * |Bits |Field |Descriptions 89 * | :----: | :----: | :---- | 90 * |[31:0] |SEED |CRC Seed Value 91 * | | |This field indicates the CRC seed value. 92 * | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1. 93 * | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). 94 * @var CRC_T::CHECKSUM 95 * Offset: 0x0C CRC Checksum Register 96 * --------------------------------------------------------------------------------------------------- 97 * |Bits |Field |Descriptions 98 * | :----: | :----: | :---- | 99 * |[31:0] |CHECKSUM |CRC Checksum Results 100 * | | |This field indicates the CRC checksum result. 101 * | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). 102 */ 103 __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ 104 __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ 105 __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ 106 __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ 107 108 } CRC_T; 109 110 /** 111 @addtogroup CRC_CONST CRC Bit Field Definition 112 Constant Definitions for CRC Controller 113 @{ 114 */ 115 116 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ 117 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ 118 119 #define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ 120 #define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ 121 122 #define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ 123 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ 124 125 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ 126 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ 127 128 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ 129 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ 130 131 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ 132 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ 133 134 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ 135 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ 136 137 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ 138 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ 139 140 #define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ 141 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ 142 143 #define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ 144 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ 145 146 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ 147 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ 148 149 /**@}*/ /* CRC_CONST */ 150 /**@}*/ /* end of CRC register group */ 151 /**@}*/ /* end of REGISTER group */ 152 153 #endif /* __CLK_REG_H__ */ 154
