1 /*
2 * Copyright (c) 2022 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/devicetree.h>
9 #include <zephyr/drivers/counter.h>
10 #include <zephyr/kernel.h>
11 #include <zephyr/spinlock.h>
12 #include <soc.h>
13 #include <counter/counter_ace_v1x_art_regs.h>
14
15 static struct k_spinlock lock;
16
counter_ace_v1x_art_ionte_set(bool new_timestamp_enable)17 static void counter_ace_v1x_art_ionte_set(bool new_timestamp_enable)
18 {
19 uint32_t val;
20
21 val = sys_read32(ACE_TSCTRL);
22 val &= ~ACE_TSCTRL_IONTE_MASK;
23 val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable);
24 sys_write32(val, ACE_TSCTRL);
25 }
26
counter_ace_v1x_art_cdmas_set(uint32_t cdmas)27 static void counter_ace_v1x_art_cdmas_set(uint32_t cdmas)
28 {
29 uint32_t val;
30
31 val = sys_read32(ACE_TSCTRL);
32 val &= ~ACE_TSCTRL_CDMAS_MASK;
33 val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas);
34 sys_write32(val, ACE_TSCTRL);
35 }
36
counter_ace_v1x_art_ntk_set(bool new_timestamp_taken)37 static void counter_ace_v1x_art_ntk_set(bool new_timestamp_taken)
38 {
39 uint32_t val;
40
41 val = sys_read32(ACE_TSCTRL);
42 val &= ~ACE_TSCTRL_NTK_MASK;
43 val |= FIELD_PREP(ACE_TSCTRL_NTK_MASK, new_timestamp_taken);
44 sys_write32(val, ACE_TSCTRL);
45 }
46
counter_ace_v1x_art_ntk_get(void)47 static uint32_t counter_ace_v1x_art_ntk_get(void)
48 {
49 return FIELD_GET(ACE_TSCTRL_NTK_MASK, sys_read32(ACE_TSCTRL));
50 }
51
counter_ace_v1x_art_hhtse_set(bool enable)52 static void counter_ace_v1x_art_hhtse_set(bool enable)
53 {
54 uint32_t val;
55
56 val = sys_read32(ACE_TSCTRL);
57 val &= ~ACE_TSCTRL_HHTSE_MASK;
58 val |= FIELD_PREP(ACE_TSCTRL_HHTSE_MASK, enable);
59 sys_write32(val, ACE_TSCTRL);
60 }
61
counter_ace_v1x_art_counter_get(void)62 static uint64_t counter_ace_v1x_art_counter_get(void)
63 {
64 uint32_t hi0, lo, hi1;
65
66 do {
67 hi0 = sys_read32(ACE_ARTCS_HI);
68 lo = sys_read32(ACE_ARTCS_LO);
69 hi1 = sys_read32(ACE_ARTCS_HI);
70 } while (hi0 != hi1);
71
72 return (((uint64_t)hi1) << 32) | lo;
73 }
74
counter_ace_v1x_art_get_value(const struct device * dev,uint64_t * value)75 int counter_ace_v1x_art_get_value(const struct device *dev, uint64_t *value)
76 {
77 ARG_UNUSED(dev);
78
79 k_spinlock_key_t key = k_spin_lock(&lock);
80
81 counter_ace_v1x_art_ionte_set(1);
82 counter_ace_v1x_art_cdmas_set(1);
83
84 if (counter_ace_v1x_art_ntk_get()) {
85 counter_ace_v1x_art_ntk_set(1);
86 while (counter_ace_v1x_art_ntk_get()) {
87 k_busy_wait(10);
88 }
89 }
90
91 counter_ace_v1x_art_hhtse_set(1);
92
93 while (!counter_ace_v1x_art_ntk_get()) {
94 k_busy_wait(10);
95 }
96
97 *value = counter_ace_v1x_art_counter_get();
98
99 counter_ace_v1x_art_ntk_set(1);
100 k_spin_unlock(&lock, key);
101
102 return 0;
103 }
104
105 static const struct counter_driver_api ace_v1x_art_counter_apis = {
106 .get_value_64 = counter_ace_v1x_art_get_value
107 };
108
109 DEVICE_DT_DEFINE(DT_NODELABEL(ace_art_counter), NULL, NULL, NULL, NULL,
110 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
111 &ace_v1x_art_counter_apis);
112
