1# ARM Cortex-A and Cortex-R platform configuration options
2
3# Copyright (c) 2018 Marvell
4# Copyright (c) 2018 Lexmark International, Inc.
5# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
6#
7# SPDX-License-Identifier: Apache-2.0
8
9# NOTE: We have the specific core implementations first and outside of the
10# if CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R block so that SoCs can
11# select which core they are using without having to select all the options
12# related to that core. Everything else is captured inside the if
13# CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not
14# exposed if one selects a different ARM Cortex Family (Cortex-M).
15
16config CPU_CORTEX_A9
17	bool
18	select CPU_AARCH32_CORTEX_A
19	select ARMV7_A
20	help
21	  This option signifies the use of a Cortex-A9 CPU.
22
23if CPU_AARCH32_CORTEX_A
24
25config ARMV7_A
26	bool
27	select ATOMIC_OPERATIONS_BUILTIN
28	select ISA_ARM
29
30config ARMV7_EXCEPTION_STACK_SIZE
31	int "Undefined Instruction and Abort stack size (in bytes)"
32	default 256
33	help
34	  This option specifies the size of the stack used by the undefined
35	  instruction and data abort exception handlers.
36
37config ARMV7_FIQ_STACK_SIZE
38	int "FIQ stack size (in bytes)"
39	default 256
40	help
41	  This option specifies the size of the stack used by the FIQ handler.
42
43config ARMV7_SVC_STACK_SIZE
44	int "SVC stack size (in bytes)"
45	default 512
46	help
47	  This option specifies the size of the stack used by the SVC handler.
48
49config ARMV7_SYS_STACK_SIZE
50	int "SYS stack size (in bytes)"
51	default 1024
52	help
53	  This option specifies the size of the stack used by the system mode.
54
55config RUNTIME_NMI
56	default y
57
58config GEN_ISR_TABLES
59	default y
60
61config GEN_IRQ_VECTOR_TABLE
62	default n
63
64config DCACHE_LINE_SIZE
65	default 32
66
67config ICACHE_LINE_SIZE
68	default 32
69
70endif # CPU_AARCH32_CORTEX_A
71
72config CPU_CORTEX_R4
73	bool
74	select CPU_AARCH32_CORTEX_R
75	select ARMV7_R
76	select ARMV7_R_FP if CPU_HAS_FPU
77	help
78	  This option signifies the use of a Cortex-R4 CPU
79
80config CPU_CORTEX_R5
81	bool
82	select CPU_AARCH32_CORTEX_R
83	select ARMV7_R
84	select ARMV7_R_FP if CPU_HAS_FPU
85	select CPU_HAS_ICACHE
86	select CPU_HAS_DCACHE
87	help
88	  This option signifies the use of a Cortex-R5 CPU
89
90config CPU_CORTEX_R7
91	bool
92	select CPU_AARCH32_CORTEX_R
93	select ARMV7_R
94	select ARMV7_R_FP if CPU_HAS_FPU
95	help
96	  This option signifies the use of a Cortex-R7 CPU
97
98config CPU_CORTEX_R8
99	bool
100	select CPU_AARCH32_CORTEX_R
101	select ARMV7_R
102	select ARMV7_R_FP if CPU_HAS_FPU
103	help
104	  This option signifies the use of a Cortex-R8 CPU
105
106config CPU_CORTEX_R52
107	bool
108	select CPU_AARCH32_CORTEX_R
109	select AARCH32_ARMV8_R
110	select CPU_HAS_ICACHE
111	select CPU_HAS_DCACHE
112	select VFP_SP_D16 if !USE_SWITCH
113	help
114	  This option signifies the use of a Cortex-R52 CPU
115
116config CPU_CORTEX_R52_CACHE_SEGREGATION
117	bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
118	depends on CPU_CORTEX_R52
119	help
120	  Control segregation of L1 I/D-Cache ways between Flash and AXIM.
121	  Updates to the cache segregation controls are only permitted before the caches
122	  have ever been enabled, following a system reset, otherwise the update is ignored.
123
124config CPU_CORTEX_R52_ICACHE_FLASH_WAY
125	int "L1 I-Cache Flash way"
126	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
127	range 0 4
128	default 0
129	help
130	  Configure L1 I-Cache ways for Flash interface. Default is reset value, all
131	  I-Cache ways are allocated for AXIM interface.
132
133config CPU_CORTEX_R52_DCACHE_FLASH_WAY
134	int "L1 D-Cache Flash way"
135	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
136	range 0 4
137	default 0
138	help
139	  Configure L1 D-Cache ways for Flash interface. Default is reset value,
140	  all D-Cache ways are allocated for AXIM interface.
141
142if CPU_AARCH32_CORTEX_R
143
144config ARMV7_R
145	bool
146	select ATOMIC_OPERATIONS_BUILTIN
147	select ISA_ARM
148	select ISA_THUMB2
149	help
150	  This option signifies the use of an ARMv7-R processor
151	  implementation.
152
153	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
154	  The Armv7-R architecture implements a traditional Arm architecture with
155	  multiple modes and supports a Protected Memory System Architecture
156	  (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32)
157	  and Thumb (T32) instruction sets.
158
159config ARMV7_R_FP
160	bool
161	depends on ARMV7_R
162	help
163	  This option signifies the use of an ARMv7-R processor
164	  implementation supporting the Floating-Point Extension.
165
166config AARCH32_ARMV8_R
167	bool
168	select ATOMIC_OPERATIONS_BUILTIN
169	select SCHED_IPI_SUPPORTED if SMP
170	select ARCH_HAS_DIRECTED_IPIS
171	help
172	  This option signifies the use of an ARMv8-R AArch32 processor
173	  implementation.
174
175	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
176	  The Armv8-R architecture targets at the Real-time profile. It introduces
177	  virtualization at the highest security level while retaining the
178	  Protected Memory System Architecture (PMSA) based on a Memory Protection
179	  Unit (MPU). It supports the A32 and T32 instruction sets.
180
181config ARMV7_EXCEPTION_STACK_SIZE
182	int "Undefined Instruction and Abort stack size (in bytes)"
183	default 256
184	help
185	  This option specifies the size of the stack used by the undefined
186	  instruction and data abort exception handlers.
187
188config ARMV7_FIQ_STACK_SIZE
189	int "FIQ stack size (in bytes)"
190	default 256
191	help
192	  This option specifies the size of the stack used by the FIQ handler.
193
194config ARMV7_SVC_STACK_SIZE
195	int "SVC stack size (in bytes)"
196	default 512
197	help
198	  This option specifies the size of the stack used by the SVC handler.
199
200config ARMV7_SYS_STACK_SIZE
201	int "SYS stack size (in bytes)"
202	default 1024
203	help
204	  This option specifies the size of the stack used by the system mode.
205
206config RUNTIME_NMI
207	default y
208
209config GEN_ISR_TABLES
210	default y
211
212config GEN_IRQ_VECTOR_TABLE
213	default n
214
215config DISABLE_TCM_ECC
216	bool "Disable ECC on TCM"
217	help
218	  This option disables ECC checks on Tightly Coupled Memory.
219
220config DCACHE_LINE_SIZE
221	default 64 if CPU_CORTEX_R52
222	default 32
223
224config ICACHE_LINE_SIZE
225	default 64 if CPU_CORTEX_R52
226	default 32
227
228endif # CPU_AARCH32_CORTEX_R
229
230config TEST_EXTRA_STACK_SIZE
231	default 1024 if SMP
232