1# ARM Cortex-A and Cortex-R platform configuration options
2
3# Copyright (c) 2018 Marvell
4# Copyright (c) 2018 Lexmark International, Inc.
5# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
6#
7# SPDX-License-Identifier: Apache-2.0
8
9# NOTE: We have the specific core implementations first and outside of the
10# if CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R block so that SoCs can
11# select which core they are using without having to select all the options
12# related to that core. Everything else is captured inside the if
13# CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not
14# exposed if one selects a different ARM Cortex Family (Cortex-M).
15
16config CPU_CORTEX_A9
17	bool
18	select CPU_AARCH32_CORTEX_A
19	select ARMV7_A
20	help
21	  This option signifies the use of a Cortex-A9 CPU.
22
23if CPU_AARCH32_CORTEX_A
24
25config ARMV7_A
26	bool
27	select ATOMIC_OPERATIONS_BUILTIN
28	select ISA_ARM
29
30config ARMV7_EXCEPTION_STACK_SIZE
31	int "Undefined Instruction and Abort stack size (in bytes)"
32	default 256
33	help
34	  This option specifies the size of the stack used by the undefined
35	  instruction and data abort exception handlers.
36
37config ARMV7_FIQ_STACK_SIZE
38	int "FIQ stack size (in bytes)"
39	default 256
40	help
41	  This option specifies the size of the stack used by the FIQ handler.
42
43config ARMV7_SVC_STACK_SIZE
44	int "SVC stack size (in bytes)"
45	default 512
46	help
47	  This option specifies the size of the stack used by the SVC handler.
48
49config ARMV7_SYS_STACK_SIZE
50	int "SYS stack size (in bytes)"
51	default 1024
52	help
53	  This option specifies the size of the stack used by the system mode.
54
55config RUNTIME_NMI
56	default y
57
58config GEN_ISR_TABLES
59	default y
60
61config GEN_IRQ_VECTOR_TABLE
62	default n
63
64config DCACHE_LINE_SIZE
65	default 32
66
67config ICACHE_LINE_SIZE
68	default 32
69
70endif # CPU_AARCH32_CORTEX_A
71
72config CPU_CORTEX_R4
73	bool
74	select CPU_AARCH32_CORTEX_R
75	select ARMV7_R
76	select ARMV7_R_FP if CPU_HAS_FPU
77	help
78	  This option signifies the use of a Cortex-R4 CPU
79
80config CPU_CORTEX_R5
81	bool
82	select CPU_AARCH32_CORTEX_R
83	select ARMV7_R
84	select ARMV7_R_FP if CPU_HAS_FPU
85	help
86	  This option signifies the use of a Cortex-R5 CPU
87
88config CPU_CORTEX_R7
89	bool
90	select CPU_AARCH32_CORTEX_R
91	select ARMV7_R
92	select ARMV7_R_FP if CPU_HAS_FPU
93	help
94	  This option signifies the use of a Cortex-R7 CPU
95
96config CPU_CORTEX_R52
97	bool
98	select CPU_AARCH32_CORTEX_R
99	select AARCH32_ARMV8_R
100	select CPU_HAS_ICACHE
101	select CPU_HAS_DCACHE
102	select VFP_SP_D16 if !USE_SWITCH
103	help
104	  This option signifies the use of a Cortex-R52 CPU
105
106if CPU_AARCH32_CORTEX_R
107
108config ARMV7_R
109	bool
110	select ATOMIC_OPERATIONS_BUILTIN
111	select ISA_ARM
112	select ISA_THUMB2
113	help
114	  This option signifies the use of an ARMv7-R processor
115	  implementation.
116
117	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
118	  The Armv7-R architecture implements a traditional Arm architecture with
119	  multiple modes and supports a Protected Memory System Architecture
120	  (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32)
121	  and Thumb (T32) instruction sets.
122
123config ARMV7_R_FP
124	bool
125	depends on ARMV7_R
126	help
127	  This option signifies the use of an ARMv7-R processor
128	  implementation supporting the Floating-Point Extension.
129
130config AARCH32_ARMV8_R
131	bool
132	select ATOMIC_OPERATIONS_BUILTIN
133	select SCHED_IPI_SUPPORTED if SMP
134	select ARCH_HAS_DIRECTED_IPIS
135	help
136	  This option signifies the use of an ARMv8-R AArch32 processor
137	  implementation.
138
139	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
140	  The Armv8-R architecture targets at the Real-time profile. It introduces
141	  virtualization at the highest security level while retaining the
142	  Protected Memory System Architecture (PMSA) based on a Memory Protection
143	  Unit (MPU). It supports the A32 and T32 instruction sets.
144
145config ARMV7_EXCEPTION_STACK_SIZE
146	int "Undefined Instruction and Abort stack size (in bytes)"
147	default 256
148	help
149	  This option specifies the size of the stack used by the undefined
150	  instruction and data abort exception handlers.
151
152config ARMV7_FIQ_STACK_SIZE
153	int "FIQ stack size (in bytes)"
154	default 256
155	help
156	  This option specifies the size of the stack used by the FIQ handler.
157
158config ARMV7_SVC_STACK_SIZE
159	int "SVC stack size (in bytes)"
160	default 512
161	help
162	  This option specifies the size of the stack used by the SVC handler.
163
164config ARMV7_SYS_STACK_SIZE
165	int "SYS stack size (in bytes)"
166	default 1024
167	help
168	  This option specifies the size of the stack used by the system mode.
169
170config RUNTIME_NMI
171	default y
172
173config GEN_ISR_TABLES
174	default y
175
176config GEN_IRQ_VECTOR_TABLE
177	default n
178
179config DISABLE_TCM_ECC
180	bool "Disable ECC on TCM"
181	help
182	  This option disables ECC checks on Tightly Coupled Memory.
183
184config DCACHE_LINE_SIZE
185	default 64 if CPU_CORTEX_R52
186	default 32
187
188config ICACHE_LINE_SIZE
189	default 64 if CPU_CORTEX_R52
190	default 32
191
192endif # CPU_AARCH32_CORTEX_R
193
194config TEST_EXTRA_STACK_SIZE
195	default 1024 if SMP
196